ACTAR GEMs readout proposal with ASIC & ADC per pad.

Patrick Coleman-Smith

Daresbury LaboratoryDaresbury June 2006

ACTAR

GEMs readout proposal with ASIC & ADC per pad.

Daresbury June 2006


Daresbury Laboratory

ACTAR


Daresbury June 2006



ACTAR


128 Pad GEM Readout Board

16 of 128 Channel s

P re-amp/ShaperASIC

Virtex 4 FPGA

16GEMPads

Time Clock Communications

Outside the Gas

Communication s with adjacen t boards

Communication s with adjacen t boards

16 20 LVDS links

Two 8 x 1 2bit50Mhz FADC

Daresbury June 2006



ACTAR


0.8mm

pitch connector

Virtex 4 FPGA

64mm

~130mm

Pre-am p/Shaper ASIC16 channels/chip ?

4 per side

128 channels FADCin 16 devices

8 per side

Daresbury June 2006



ACTAR


GEMs pcb

Pad readoutBeam

Cooling for the electronicsSerial communications

&Power distribution

Daresbury June 2006



ACTAR


Daresbury June 2006



ACTAR


Controls8 x ASICS

Ether-net

Virtex4 module

FADC

ASICcontrolsbnuffers

Clock,clear,hold

Triggers

MetronomeInterface100Mhz

clock

clock, sync,reset

error

DC- DC3.3V2.5V1.8V

from external+12Volts

Clock conditioning

Filters?

20MhzLow Pass

Board design in progress

•Prisma SED with Gassiplex

•Single channel development with PreShape32, FREDA.

Daresbury June 2006



ACTAR


2

3 4

1. GASSIPLEX 32 channel board under test.

2. MAXIM Flash ADC evaluation board with Virtex2 FPGA for readout conversion, and GASSIPLEX control

3. Parallel connection between the two FPGAs

4. Virtex2Pro development board on loan from RAL with link to PC via Ethernet.

1

Current Test setup

ACTAR GEMs readout proposal with ASIC & ADC per pad.

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