MACHINE ARCHITECTURE

© Cutajar & Cutajar 2012

MACHINE ARCHITECTURE

In its simplest form, a computer consists of five basic functional units: – the control unit, the arithmetic and logic unit, memory unit, the input unit and the output unit.

I/O

PROCESSOR

ARITHMETIC & LOGIC UNIT

CONTROL UNIT

OUTPUT UNIT

MEMORY UNIT

INPUT UNIT

BASIC FUNCTIONAL UNITS OF COMPUTER

Input Unit: is the means by which computers can accept coded information.

Memory Unit: its function is to store programs and data that are currently in use.

Semiconductor storage cells are used for primary storage.

Arithmetic and Logic Unit (ALU): Execution of most operations within a computer takes place in the ALU.

e.g. the addition of two numbers currently in main memory

Output Unit: Its function is to return processed results to the outside world.

Control Unit: Its function is to co-ordinate the operations of the other units in an organized way.

OPERATION OF A COMPUTER

The operation of a computer can be briefly described as follows:

It accepts information (programs and data) through an input unit and transfers it to main memory

Information stored in memory is fetched under program control into an ALU to be processed

Processed information leaves the computer through an output unit

The control unit directs all activities inside the machine. The system clock generates a continuous sequence of clock pulses to step the control unit through its operation.

OVERALL BLOCK STRUCTURE OF A COMPUTER

Input port

Output port

External Address/Data Bus

Control Unit

Arithmetic & Logic Unit

Memory Unit

Input/Output Unit

Internal Address/data

buses

System clock

The functional units are connected by BUSES and control links. The latter are not shown on the above diagram.

WHAT IS A BUS

A bus is a pathway along which data, addresses and control signals pass within the computer.

Physically a bus is a parallel group of wires, usually 16, 32, 64 … bits wide.

The capacity of a bus is determined by how many bits can travel through the circuitry at one time. The greater the capacity of a bus, the more powerful and faster the operation.

The speed of the bus is another factor that influences the processing power of a computer

To represent a bus we usually use the large arrow as shown in the diagram below.

Bus 16 bits wide

(i) (ii)

TYPES OF BUSES

A data bus is used in order to transfer data from one functional unit to the other (say between the CPU and memory) inside the computer. The data bus is two way The width of the data bus determines how many bits can be transferred simultaneously. It is

usually (but not always) the same as the word size o The width of the data bus is usually - but not always – the same as the word size. The

word size of a computer is the number of bits that the CPU can process simultaneously. Word size is an important factor in determining the speed of a processor

An address bus is used to transfer addresses from the control unit to other parts of the computer unit The address bus is one way only The width of the address bus determines the maximum address that can be directly

referenced Example: Given an 8-bit address bus, you can directly address 256 locations 0000 0000 – 1111 1111 (0-255)

The control bus carries control signals to different parts of the computer such as ‘read’ and ‘write’

System bus is a general term for the bus system connecting the CPU to main memory.

BANDWIDTH AND BUS SYSTEMS

The bandwidth of the bus, measured in bits/sec, signifies the number of bits that can be transmitted along the bus.

There are several ways in which this physical limitation and others of a bus system may be overcome in order to improve system performance:

Increase the bus system bandwidth

The use of caching technique

Multiple buses. Apart from the added buses this would require extra hardware so that a processor may switch from one bus to another according to which bus is not in use at the time.

THE SYSTEM CLOCK

Clock pulses

Clock

pulse

The clock is an electronic system which produces a train of binary pulses which represent the pattern 01010101 . Each clock pulse represents one cycle of the square wave as shown above.

The System clock also called Control Pulse Generator.

Processors have an internal clock which generates regularly timed pulses in order to synchronize the various operations being carried out inside the computer.

CLOCK SPEED

All processor activities, such as fetching an instruction, reading a data item from main memory into the CPU, etc., must begin on a clock pulse. Some activities may take more than one clock pulse to complete.

The speed (frequency) of the clock is measured in Hz (hertz), i.e. cycles per second.

Say, given an 800MHz Pentium processor, 800MHz = 800 * 106 Hz

= 800 000 000 cycles per second

i.e. the processor is being told to do different things at a rate of 800 million times per second

Hence, the clock speed is one of the factors that influence the processing power of a computer.

MAIN MEMORY ORGANISATION

Main memory is used to store data.

Data may represent instructions, ASCII character codes, numeric codes … a host of different data codes.

A single storage location is called a register.

REGISTER

n bits

Storage consists of an array of such registers.

Say, a 1 Mb memory bank with 8-bit registers:

1Mb = 1024*1024 bytes (220)

= 1048576 bytes hence 1048576 memory registers of 1 byte each.

Furthermore, a 20-bit address is required to address all registers directly.

MEMORY MAP

Physically the storage used inside computer unit is of the semiconductor type. Different types of memory chips exist and are in use.

The main memory of a computer consists of a mixture of semiconductor types. Different parts of main memory are used for specific purposes. How the memory of the computer is utilized, is called the MEMORY MAP and is usually dictated by the operating system. Below is a simplistic example of a memory map.

In order to be able to store and retrieve information in memory locations, each location is identified by means of an identification number called ADDRESS. Knowing the address, a memory location may be accessed immediately – hence random access (memory). We usually denote memory addresses in hex.

Addresses (Hex)

Operating system

FFF001 FFFFF

User programs

0F4241 FFF000

Operating System

010000 – 0F4240

BIOS 000000 – 00FFFF

(Bradley, 1999)

MEMORY CYCLE

In order to read an item from store to the CPU, the address of the item is sent across to main memory via the address bus and the read signal is sent via the control bus so that the required item is retrieved into the CPU via the data bus.

Similarly, in order to write an item to store, the address where to store the data item is sent across the address bus, the item to be stored is sent via the data bus, while the write signal is sent via the control bus.

One sequence for reading/writing is called a MEMORY CYCLE. The complexity of an operation often depends on the number of memory cycles involved.

The duration of a memory cycle is a determining factor of the overall speed of a computer.

INPUT/OUTPUT ORGANIZATION

Below is a more elaborated block diagram of the computer.

Most microcomputers use a single bus arrangement as shown below.

Address bus

CPU

Data bus

System clock

RAM ROM VDU & keyboard

HardDisk CD ROM

Printer Plotter

Scanner

Digital I/O

A/D D/A

Process control

Control bus is not shown →—

(Adapted from Bradley, 1999)

HANDLING INPUT-OUTPUT

The processor, memory and I/O devices are connected to the bus, which consists of three sets of lines used to carry address, data and control signals.

Each I/O device is assigned a unique address. When the processor places a particular address on the address lines, the device that recognizes its address responds to the commands issued on the control lines.

When I/O devices and the memory share the same address space, the arrangement is called MEMORY-MAPPED I/O.

An alternative way of handling input-output is to have special instructions to perform I/O transfers and separate address space for I/O devices – ISOLATED I/O.

I/O INTERFACE

The diagram below illustrates the I/O interface for an input device.

Address decoder

Control circuits

Data & status registers

Bus

Address lines

Data lines

Control lines

Input device

I/O Interface

In order to input data, the address decoder identifies its own address on the address bus and the read signal on the control line; the input device sends data to the data register and sets the status register to signal that the input is complete. The data is then copied from the input data register into the computer.

A similar procedure is used to output data to an output device.

(Hamacher et al. 1996)

THE CENTRAL PROCESSING UNIT (PROCESSOR)

Traditionally, in microcomputers the CPU (or processor) is contained on a single integrated circuit, and is known as a microprocessor. In larger computer systems, the term CPU is often referred to as the main processing unit and houses a number of processors.

Nowadays, the processor of a personal computer may consist of a number of execution units or ‘cores’ – example quad core technology. More execution cores implies more processing power but it does not necessarily mean more speed.

The control unit and arithmetic unit together, form the central processing unit (CPU).

Popularly, the clock speed of the chip is quoted as CPU speed measurement; but the count of instructions processed per second (MIPS, BIPS, TIPS for Millions, Billions or Trillions of Instructions processed per Second) gives a better indication of CPU speed.

The Arithmetic and logic unit is that part of the CPU where the actual

manipulation of the data takes place.

The task of the Control Unit is to direct the step-by-step workings of the processor as it carries out each instruction of a program

TASK OF CONTROL UNIT

The task of the Control Unit is to direct the step-by-step workings of the processor as it carries out each instruction of a program, i.e.

to control the sequence in which the instructions are executed

to control access to the main store of the computer

to regulate the timing of all operations carried out within the processor

to send control signals to, and receive control signals from peripheral devices

The CPU contains circuitry and registers to enable it to carry out its tasks.

CPU REGISTERS (1)

The block diagram below represents the CPU with some of the registers involved. Note that some of the registers have a special purpose while others are general purpose storage registers.

Memory address Register (MAR)

Memory Data Register (MDR)

Control Unit

Status Register

Program Counter (PC)

Arithmetic and Logic Unit

R0

R1

R2

R3

R4

R5

External bus

Instruction Register (CIR)

Accumulator

Memory

CPU REGISTERS (2)

The Memory Address Register (MAR) holds the address of the memory location currently being accessed (i.e. from which data is being read or data is being written.

The Memory Data Register (MDR) or Memory Buffer Register (MBR) is used to temporarily store data read or written to main memory.

(Note that, at any moment it time, it holds the data that was read from or written to main memory the last time that this read/write operation was carried out.)

CPU REGISTERS (3)

The program counter (PC) or Sequence Control register contains the address of the next program instruction to be executed It determines the sequence in which the program instructions are to be

executed.

After an instruction is fetched from main store, the content of the program counter is increased ready for the next instruction. Depending on the length of the current instruction, 1 or 2 or is added to the program counter in order to reset it.

If an instruction transfers control to another part of the program, the address to which control is transferred, is loaded into the program counter.

The Current Instruction Register (CIR) stores a copy of the current program instruction. The register is connected to a decoder that connects the control switches at various points throughout the processor according to the instruction in the instruction register.

CPU REGISTERS (4)

The Status Register (SR) contains bits that are set or cleared based on the result of an instruction. Different bits within this register represent different flags or status bits (sometimes also known as condition codes) such as:

Zero (Z) is set to 1 if the output from the current operation is 0

Negative (N) is set to 1 if the output from the current instruction is negative.

Carry (C) is set to 1 if there is a carry to the MSB during addition or shift

Overflow (O) is set to 1 if there is an overflow when an arithmetic operation is carried out

The values of these flags are used to control the program.

The Accumulator is the principal ‘working area’ of the computer. It stores the data item currently being processed.

CPU REGISTERS (5)

Other special purpose registers found within the CPU:

The Stack Pointer (SP) stores the current address of the top of stack. Some uses of stack are: When execution of a program is interrupted, the status of the current program and the

current contents of all the registers are saved on the stack and the stack pointer updated. Stores intermediate results of arithmetic operations. Holds return address (contents of program counter) and parameter information when

subroutines are called.

Index Register is used to implement a particular mode of memory addressing called indexed addressing. The index register holds the base address of an array of locations. In order to access a specific location of the array the offset is added to the base address. This is ideal for handling array structures.

CPU REGISTERS (6)

The general-purpose registers are used to temporarily store data (including addresses)

In some computers there is only one general-purpose register i.e. the accumulator.

Other computers have a number of general-purpose registers. In some processors the program counter, instruction register are not

dedicated registers but general purpose registers in the CPU and each may be used as PC, CIR …

Distinguish between theoretical and practical perspectives: Compare and contrast the above-mentioned processor registers discussed from a theoretical perspective to a practical implementation such as the setup of registers of the processor 8086.

ARITHMETIC AND LOGIC CIRCUITS (1)

NOT operates on a single operand

Hence, NOT(1010 0110) 0101 1001

AND operates on two operands

Hence,

AND (1010 0110, 1111 0000) 1010 0000

A NOT A

0 1

1 0

A B A AND B

0 0 0

0 1 0

1 0 0

1 1 1

The ALU holds a number of arithmetic and logic circuits. These circuits carry out various operations on one or two data items.

ADD a pair of data items / increment by one a single data item

ARITHMETIC AND LOGIC CIRCUITS (2)

A B A XOR B

0 0 0

0 1 1

1 0 1

1 1 0

A B A OR B

0 0 0

0 1 1

1 0 1

1 1 1

OR operates on two operands Hence, OR(1010 0110, 1111 0000) 1111 0110

XOR (Exclusive OR) operates on two operands Hence, XOR(1010 0110, 1111 0000) 0101 0110

ARITHMETIC AND LOGIC CIRCUITS (3)

LOGICAL SHIFT operates on a single operand

Logical SHIFT LEFT moves the individual bits of the operand one place to the left. The leftmost bit is lost and ‘0’ is added as the rightmost bit

Hence, A Logical Shift Left:- 1010 0110 10100 1100

Similarly, Logical SHIFT RIGHT:- 1010 0110 0101 00110

ARITHMETIC SHIFT operates on a single operand

Arithmetic SHIFT LEFT moves the individual bits of the operand one place to the left. The rightmost bit after the most significant bit (MSB) is lost and ‘0’ is added as the least significant bit (LSB).

Arithmetic SHIFT RIGHT moves the individual bits of the operand one place to the right. The leftmost bit is lost and a ‘0’ or a ‘1’ is added to the rightmost bit after the most significant bit (MSB)

Note that in arithmetic shifts the sign of the number must be preserved

If the shift operations are through the carry bit then the ‘lost bit’ is copied into the carry bit.

Assuming sign-and-magnitude code:

Arithmetic Shift Left

(1010 0110) 1100 1100

out / \ in

Arithmetic Shift Right

(1010 0110) 1001 0011

\ out \in

Assuming two’s complement code:

Arithmetic Shift Left

(1010 0110) 1100 1100

out / \ in

Arithmetic Shift Right - because of complementation when negative insert a 1

(1010 0110) 1101 0011

\ out \in

ARITHMETIC SHIFT OPERATIONS

THE FETCH-EXECUTE CYCLE (1)

The Fetch-Execute cycle is also known as the Instruction Cycle.

The sequence of operations involved in executing an instruction can be subdivided into two phases – the fetch cycle and the execution cycle.

The fetch-execute cycle involves the following steps:

• (Fetch phase)

The address of the next instruction is copied from the PC to the MAR

The instruction held at the address is copied to the MDR. At the same time the content of the PC is incremented so that it holds the address of the next instruction.

The contents of the MDR are copied to the CIR

• (Execute phase)

The instruction held in the CIR is decoded

The instruction is executed

THE FETCH-EXECUTE CYCLE (2)

N

Y

N

Y

START

Transfer control to interrupt handling program

Any instructions to execute?

Fetch next instruction

Decode instruction

Execute instruction

Any interrupts to be processed?

OTHER PROCESSOR FUNCTIONS

In addition to fetching and executing program sequence instructions, the CPU has to supervise other operations such as data transfers between input/output devices and main memory.

When an I/O device needs to transfer data, it generates an interrupt and the CPU suspends execution of the program and transfers control to an appropriate interrupt handling program. A test for the presence of interrupts is carried out at the end of each instruction cycle.

INTERRUPTS

An interrupt is a signal from some device or source that causes the running program to be suspended.

The interrupt signal is sent along one or more interrupt lines (part of the control bus) to the processor.

Common causes of interrupt: input and output of data e.g. to signal to the processor that input

required is complete

timed interrupts e.g.: in a time-sharing system, user process is interrupted its time-slice.

error detection in a program e.g. division by zero, type mismatch.

malfunctioning of hardware e.g. memory violation error

INTERRUPT HANDLING

When an interrupt occurs:

The instruction cycle is completed

The current contents of all the processor registers are saved

The source of interrupt is identified

Interrupts of lower priority are disabled

Initiation and execution of relevant interrupt servicing routine

Interrupts are enabled

The interrupted program is resumed from the point at which it was interrupted (or the most suitable process to run).

DETERMINATION OF SOURCE OF INTERRUPT (1)

Determination of the source of interrupt may be implemented in various ways:

Directly by hardware

Given ‘n’ interrupt lines, it is possible to identify 2n different sources of interrupt

Software-based identification

Polling method: a skip chain polls each different source:

Interrupt Service Routine (ISR) for source 2

Interrupt Service Routine (ISR) for source 1

Source 1?

Source 2?

DETERMINATION OF SOURCE OF INTERRUPT (2)

Most often a combination of hardware and software is used in order to identify different sources of interrupt

One interrupt identification scheme may be as follows:

After each instruction cycle an interrupt register within the CPU is checked. Each bit of this register represents a different type of interrupt. When an interrupt occurs one of the bits is set to ‘1’. If a bit is set, the interrupt is identified and serviced.

Another interrupt identification is the vectored interrupt scheme (next slide)

Vectored Interrupt Mechanism

The Vectored Interrupt Mechanism is a technique for used for locating the start address of the relevant ISR and which reduces the time involved by the polling process

An interrupt vector table stores the list of interrupts and associated starting address of interrupt handlers

Interrupting device supplies a vector number (the offset) which is added to the base address to obtain the pointer to the start address of the ISR

The pointer value extracted from the interrupt vector table is copied into the program counter (hence to initiate the execution of the ISR)

PRIORITY OF INTERRUPTS

Some interrupts such as hardware failure must be dealt with immediately while others may be temporarily ignored.

Interrupts are assigned priorities so that when two interrupts are received simultaneously, the one with higher priority is dealt with first.

Only an interrupt of higher priority may interrupt the servicing of another interrupt.

SOME FEATURES TO IMPROVE PERFORMANCE

Some machine architectural features which are intended to improve the performance of the computer are:

Pipelining – single-pipeline architecture…multi-pipeline architecture

Multi-processor architecture

Bus systems and bandwidth (refer to earlier slides)

Cache Memory (refer to OS course module)

Direct Memory Access (DMA)

PIPE-LINING

If the next instruction in the queue is not the required one then the pipe-line is ‘flushed’ and the process started again with the required instruction.

Multiple pipe-line architecture signifies a number of pipe-lines working in parallel. If the instructions being carried out in parallel are not connected in any way, this will result in a much faster execution rate.

instruction 15 instruction 16 instruction 17

instruction 1

instruction 2 instruction 1

instruction 3 instruction 2 instruction 1

instruction 4 instruction 3 instruction 2

wrong instruction – flush pipeline!

instruction 15 instruction 16 instruction 17

IN OUT

decode execute fetch

Pictorial illustration of single pipe-line architecture

MULTI-PROCESSOR ARCHITECTURE

Multiple-processor architectures employ a number of processors to work together ‘as a team’.

Different processors may be housed inside the same chip, say dual-core (quad core …) technology.

There exists a whole spectrum of multi-processor architectures ranging from very tightly coupled systems sharing the same buses and memory, to massive parallel architectures where each processor uses multiple communication lines to connect to other processors in the system.

CPU 1 CPU 2 CPU 3 CPU 4

Main memory

DIRECT MEMORY ACCESS

The Direct Memory Access (DMA) technique is used for servicing high-speed peripherals such as the hard-disk, hence avoiding continuous intervention by the processor.

DMA transfers are performed by a control circuit – the DMA controller, associated with the I/O device.

For each word transferred, the DMA controller performs the functions normally performed by the processor when accessing memory,

Bus

DMA Controller

Main memory CPU

Disk

i.e. for each word transferred it must provide the memory address and all the bus signals which control the transfer.

DMA CONTROLLER

Although the DMA controller can perform data transfer without intervention from the processor, its operation is under processor control.

To initiate block transfer under DMA control the processor sends the following data to the controller: the starting memory address, the number of words in the block and the direction of transfer.

The DMA controller then handles the transfer. Memory accesses by the processor and the DMA controller are interwoven. Since the processor originates most memory access cycles, the DMA controller is said to “steal” memory cycles from the processor and hence this interleaving technique is known as cycle stealing.

When the entire block is transferred the DMA controller informs the processor by raising an interrupt signal.

<starting address>

<word count>

<status and control>

R/W

done IRQ

IE DMA controller

IRQ – Interrupt Request flag IE- Interrupt enable flag R/W – Read/Write flag Done – Ready flag

HANDSHAKING

When data is being transferred between two computer components or devices - for example between the computer and the printer – there is involved a two-way dialogue between the two parties. This dialogue fundamentally involving signals “request to send” and “clear to send” is called handshaking

Handshaking might involve a status word – a bit pattern generated by the peripheral device and sent to the (device) controller. The bits of the status word indicate different conditions of the device – example for a given printer the least significant bit (LSB) of the status register may signify ‘out of paper’, another a ‘paper jam’, and so on. It may be the controller itself or the CPU (which is informed beforehand) which responds to status information.

SYNCHRONOUS & ASYNCHRONOUS TRANSFERS

In general there are two main ways for timing data transfers over a bus:

synchronous bus

asynchronous bus

In a synchronous bus, all components share a common clock.

In an asynchronous bus, components do not share a common clock giving rise to two control signals ‘Ready’ and ‘Accept’ to control data transfers. Hence data transfers are based on a hand-shaking protocol (described in the previous slide).