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Proceedings

2002 Design, Automation and Test in Europe

Conference and Exhibition

Proceedings

2002 Design, Automation and Test in Europe

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March 4 – 8, 2002 Paris, France

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v

Contents Design, Automation, and Test in Europe DATE 2002

DATE Executive Committee ________________________________________________xxiii Technical Program Chairs__________________________________________________xxvi Vendors Committee _______________________________________________________ xxx DATE Sponsors Committee_________________________________________________ xxx Technical Program Committee ______________________________________________xxxi Reviewers_______________________________________________________________xxxvi Welcome to DATE 2002 __________________________________________________xxxviii Best Paper Awards _______________________________________________________xxxix Tutorials___________________________________________________________________xl Master Courses ___________________________________________________________ xliv Call for Papers DATE 2003 ________________________________________________ 1149 Plenary Keynote Session Moderator: J. da Franca, ChipIdea, PT On Nanoscale Integration and Gigascale Complexity in the Post .Com World ___________________________ 12 Hugo De Man, Professor, KU Leuven, Senior Research Fellow, IMEC, BE Global Responsibilities in SOC Design _________________________________________________________ 12 Taylor Scanlon, President & CEO, Virtual Silicon Technology, US 1A: Hot Topic How to Choose Semiconductor IP? Organizer: Yervant Zorian, Virage Logic, US Moderator: Nic Mokhoff, EE Times, US How to Choose Semiconductor IP? Embedded Processors ________________________________________ 14 I. Phillips Make Your SoC Design a Winner: Select the Right Memory IP ______________________________________ 15 V. Ratford How to Choose Semiconductor IP: Embedded Software ____________________________________________ 16 G. Martin IP Day: How to Choose Semiconductor IP?______________________________________________________ 17 P. Bricaud 1B: Formal Verification of Complex Designs Moderators: L Fix, Intel, ISR; T. Kropf, Bosch, DE Formal Verification of the Pentium 4 Floating-Point Multiplier_____________________________________ 20 R. Kaivola and N. Narasimhan

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Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer _________________________________________________________ 28 M. Velev Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units __________________________________________________________________ 36 P. Mishra, N. Dutt, A. Nicolau, and H. Tomiyama A Case Study for the Verification of Complex Timed Circuits: IPCMOS_______________________________ 44 M. Peña, J. Cortadella, E. Pastor, and A. Smirnov 1C: Cooling Layout Arrangements Moderators: R.H.J.M. Otten, TU Eindhoven, NL; M.D.F. Wong, Texas U, US FPGA Placement by Thermodynamic Combinatorial Optimization ___________________________________ 54 J. De Vicente, J. Lanchares, and R. Hermida An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees_________________ 61 C. Zhuang, Y. Kajitani, K. Sakanushi, and L. Jin Arbitrary Convex and Concave Rectilinear Module Packing Using TCG _______________________________ 69 J. Lin, H. Chen, and Y. Chang 1D: Defect Oriented Test Moderators: J. Segura, Illes Balears U, ES; H. Manhaeve, Q-Star Test, BE A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits ____________________ 78 M. Pronath, H. Graeb, and K. Antreich Exact Grading of Multiple Path Delay Faults_____________________________________________________ 84 S. Padmanaban and S. Tragoudas Modeling Techniques and Tests for Partial Faults in Memory Devices_________________________________ 89 Z. Al-Ars and A. van de Goor A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults _____________ 94 S. Lee, B. Cobb, J. Dworak, M. Grimaila, and M. Mercer 1E: Power Analysis and Management in Networks and Processors Moderators: E. Macii, Politecnico di Torino, IT; K. Roy, Purdue U, US Low Power Error Resilient Encoding for On-Chip Data Buses ______________________________________ 102 D. Bertozzi, L. Benini, and G. De Micheli Managing Power Consumption in Networks on Chip _____________________________________________ 110 T. Simunic and S. Boyd Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States _______________________________________________________________ 117 S. Irani, R. Gupta, and S. Shukla AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors______________________ 124 D. Ponomarev, G. Kucuk, and K. Ghose

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2A: Panel What is the Right IP Business Model? Organizer: Y. Zorian, Virage Logic, US Moderator: K. Bartleson, Synopsys, US Panellists: J. Tully, Gartner Dataquest, US; G. Toomajanian, Dain Rauscher Wessels, US; E. Desai, Desaisive Technology Research, US; M. Hosseini, WIT Soundview, US; V. Essi, AH&H, UA IP is All About Implementation and Customer Satisfaction_________________________________________ 132 V. Essi, Jr. 2B: SAT and BDD Techniques Moderators: T. Shiple, Synopsys, FR; R. Drechsler, Bremen U, DE Using Problem Symmetry in Search Based Satisfiability Algorithms _________________________________ 134 E. Goldberg, M. Prasad, and R. Brayton BerkMin: A Fast and Robust Sat-Solver _______________________________________________________ 142 E. Goldberg and Y. Novikov Dynamic Scheduling and Clustering in Symbolic Image Computation ________________________________ 150 G. Cabodi, P. Camurati, and S. Quer 2C: Technology and Interconnect Issues in Low Power Design Moderators: S. Huss, TU Darmstadt, DE; D. Auvergne, LIRMM, F Wire Placement for Crosstalk Energy Minimization in Address Buses ________________________________ 158 L. Macchiarulo, E. Macii, and M. Poncino Dynamic VTH Scaling Scheme for Active Leakage Power Reduction_________________________________ 163 C. Kim and K. Roy Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints _____________________________ 168 A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau Sizing Power/Ground Meshes for Clocking and Computing Circuit Components________________________ 176 A. Mukherjee, K. Wang, L. Chen, and M. Marek-Sadowska 2D: Advanced Mixed Signal Test Moderators: J. Huertas, CNM-IMSE, ES; B. Kaminska, Fluence Technology, US A Signature Test Framework for Rapid Production Testing of RF Circuits_____________________________ 186 R. Voorakaranam, S. Cherubal, and A. Chatterjee Analog IP Testing: Diagnosis and Optimization _________________________________________________ 192 C. Guardiani, P. McNamara, L. Daldoss, S. Saxena, S. Zanella, W. Xiang, and S. Liu A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits __________________________________________________________ 197 C. Hoffmann Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal ICs _______________________ 205 Y. Lechuga, R. Mozuelos, M. Martínez, and S. Bracho

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2E: Collaborative Design Web-Services, Infrastructure, Applications Moderators: A. Sauer, FhG EAS/IIS, DE; A. Pawlak, ITE Warsaw, PL E-Design Based on the Reuse Paradigm________________________________________________________ 214 L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, and G. Saucier Internet-Based Collaborative Test Generation with MOSCITO______________________________________ 221 A. Schneider, K. Diener, E. Ivask, J. Raik, R. Ubar, P. Miklos, T. Cibáková, and E. Gramatová A Two-Tier Distributed Electronic Design Framework ____________________________________________ 227 T. Kazmierski and N. Clayton Embedded System Design Based On Webservices _______________________________________________ 232 A. Rettberg and W. Thronicke 2F: Panel Who Owns the Platform? Organizer/Moderator: W. Wolf, Princeton U, US Panellists: M. Pinto, Agere, US; P. Paulin, STMicroelectronics, CA; C. Rowen, Tensilica, US; O. Levia, Improv Systems, US; G. Saucier, Design-Reuse, FR; V. Gerousis, Infineon, DE Who Owns the Platform? ___________________________________________________________________ 238 3A: Embedded Tutorial The Need for Infrastructure IP in SoCs Organizer: D. Gizopoulos, Piraeus U, GR Moderator: G. Smith, Gartner Dataquest, US Speakers: M. Milligan, HPL Technologies, US; Y. Zorian, Virage Logic, US; S. Pateras, LogicVision, US; M. Nicolaidis, iRoC Technologies, FR IP for Embedded Robustness ________________________________________________________________ 240 M. Nicolaidis Embedded Diagnosis IP ____________________________________________________________________ 242 S. Pateras Embedded Robustness IPs __________________________________________________________________ 244 E. Dupont, M. Nicolaidis, and P. Rohr 3B: Advances in Logic Synthesis Moderators: M. Berkelaar, Magma Design Automation, NL; W. Kunz, Kaiserslautern U, DE CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines _____________ 248 S. Gören and F. Ferguson Generalized Early Evaluation in Self-Timed Circuits _____________________________________________ 255 M. Thornton, K. Fazel, R. Reese, and C. Traver Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint ___ 260 S. Jung, K. Kim, and S. Kang

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3C: Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design Moderators: F. Férnandez, IMSE-CNM, ES; A. Konczykowska, Alcatel R&I, FR A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics _________________________________________________________________ 268 W. Daems, G. Gielen, and W. Sansen Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits ______________________ 274 R. Popp, J. Oehmen, L. Hedrich, and E. Barke Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices ___________________________________________________________ 279 P. Vanassche, G. Gielen, and W. Sansen Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification______________________________________________________________________ 285 M. Ciesielski, P. Kalla, Z. Zeng, and B. Rouzeyre 3D: Hot Topic EDA Tools for RF: Myth or Reality? Organizers: L. Guarnirei, Barcelona Design, US; E. Chen, Celestry Design Technologies, US Moderator: C. Ajluni, Wireless Systems Design, US

Presenters: S. Savage, Cypress Semiconductors, US; M. Hershenson, Barcelona Design, US; X. Zhang, Celestry Design Technologies, US

EDA Tools for RF: Myth or Reality? __________________________________________________________ 292 3E: Platform-Based Design and Virtual-Component Reuse Moderators: W. Wolf, Princeton U, US; N. Mártinez Madrid, FZI Karlsruhe, DE Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs ____________________________________________________________________ 296 T. Lee, W. Wolf, and J. Henkel Techniques to Evolve a C++ Based System Design Language ______________________________________ 302 R. Paško, S. Vernalde, and P. Schaumont A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects _________________________________________________________________________ 310 A. Ginés, E. Peralías, A. Rueda, N. Madrid, and R. Seepold 3F2: Analogue Circuit Characterisation and Simulation Moderators: A. Ródriguez-Vázquez, IMSE-CNM, ES; D. Leenaerts, Philips, NL Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications_______________________ 316 W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, and V. Chowdhury Global Optimization Applied to the Oscillator Problem ___________________________________________ 322 S. Lampe and S. Laur

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4A: Panel MEDEA+ and ITRS Roadmaps Organizer: W. Rosenstiel, FZI/Tuebingen U, DE Moderator: G. Mathéron, Director of MEDEA+ Office, FR Panellists: J. Borel, STMicroelctronics, US; G. Matheron, MEDEA+ Office; A. Jerraya, TIMA, Grenoble, FR; S. Resve, UC Berkeley, US; M. Rogers, Intel, US; W. Rosenstiel, FZI/Tuebingen U, DE; I. Rugen-Herzig, Infineon Technologies, DE; F. Theeuwen, Philips Research, NL MEDEA+ and ITRS Roadmaps ______________________________________________________________ 328 4B: Asynchronous Circuits and Clock Scheduling Moderators: M. Renaudin, TIMA, Grenoble, FR; L. Lavagno, Politecnico di Torino, IT A Burst-Mode Oriented Back-End for the Balsa Synthesis System___________________________________ 330 T. Chelcea, S. Nowick, A. Bardsley, and D. Edwards Detecting State Coding Conflicts in STGs Using Integer Programming _______________________________ 338 V. Khomenko, M. Koutny, and A. Yakovlev Verifying Clock Schedules in the Presence of Cross Talk __________________________________________ 346 S. Hassoun, E. Calvillo-Gámez, and C. Cromer 4C: Analogue and Mixed-Signal Systems Moderators: A. Kaiser, ISEN, FR; P. Wambacq, IMEC, BE Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach ______ 352 M. Goffioul, P. Wambacq, G. Vandersteen, and S. Donnay Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter _________________________________ 357 J. Vandenbussche, E. Lauwers, K. Uyttenhove, M. Steyaert, and G. Gielen Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip _________________________________________________________________ 362 R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo, and A. Rodríguez-Vázquez 4D: BIST Diagnosis and DFT Moderators: M. Flottes, LIRMM, FR; A. Benso, Politecnico di Torino, IT An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs _______________ 368 A. Pandey and J. Patel Gate Level Fault Diagnosis in Scan-Based BIST _________________________________________________ 376 I. Bayraktaroglu and A. Orailoglu An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment _________ 382 C. Liu, K. Chakrabarty, and M. Goessel Reducing Test Application Time Through Test Data Mutation Encoding ______________________________ 387 S. Reda and A. Orailoglu 4E: Code and Memory Optimization in Co-Design Moderators: R. Leupers, TU Aachen, DE; R. Ernst, TU Braunschweig, DE Hardware/Software Trade-Offs for Advanced 3G Channel Coding___________________________________ 396 H. Michel, A. Worm, N. Wehn, and M. Münch

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An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs _______________ 402 A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau Assigning Program and Data Objects to Scratchpad for Energy Reduction_____________________________ 409 S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel 5A: Hot Topic Network on a Chip Moderator/Organizer: G. De Micheli, Stanford U, US Networks on Chip: A New Paradigm for Systems on Chip Design ___________________________________ 418 G. De Micheli and L. Benini Communication Mechanisms for Parallel DSP Systems on a Chip ___________________________________ 420 J. Williams, N. Heintze, and B. Ackland Networks on Silicon: Combining Best-Effort and Guaranteed Services _______________________________ 423 K. Goossens, P. Wielage, A. Peeters, and J. van Meerbergen 5B: Low Power Architectures and Software Moderators: W. Nebel, OFFIS, DE; M. Miranda, IMEC, BE Data Reuse Exploration Techniques for Loop-Dominated Applications _______________________________ 428 T. Van Achteren, G. Deconinck, F. Catthoor, and R. Lauwereins EAC: A Compiler Framework for High-Level Energy Estimation and Optimization _____________________ 436 I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. Irwin, and A. Sivasubramaniam Power Savings in Embedded Processors through Decode Filer Cache ________________________________ 443 W. Tang, R. Gupta, and A. Nicolau Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors _____ 449 L. Benini, D. Bruni, A. Macii, and E. Macii 5C: Nitty Gritty Details of Layout Design Moderators: E. Barke, Hannover U, DE; P. Groeneveld, Magma Design Automation, NL Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model___ 456 M. Becer, V. Zolotov, D. Blaauw, R. Panda, and I. Hajj Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits ______________________________________________________ 464 G. Jerke and J. Lienig A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem _____________ 470 L. Huang, X. Tang, H. Xiang, D. Wong, and I. Liu 5D: SoC and System Test Moderators: Y. Zorian, LogicVision, US; D. Gizopoulos, Piraeus U, GR Test Planning and Design Space Exploration in a Core-Based Environment____________________________ 478 E. Cota, L. Carro, M. Lubaszewski, and A. Orailoglu A Hierarchical Test Scheme for System-On-Chip Designs _________________________________________ 486 J. Li, H. Huang, J. Chen, C. Su, C. Wu, C. Cheng, S. Chen, C. Hwang, and H. Lin

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Efficient Wrapper/TAM Co-Optimization for Large SOCs _________________________________________ 491 V. Iyengar, K. Chakrabarty, E. Marinissen Beyond UML to an End-of-Line Functional Test Engine __________________________________________ 499 A. Baldini, A. Benso, P. Prinetto, S. Mo, and A. Taddei 5E: Modelling and Synthesis of Embedded Systems Moderators: J. López, Castilla-La Mancha U, ES; F. Rousseau, TIMA, Grenoble, FR Event Model Interfaces for Heterogeneous System Analysis________________________________________ 506 K. Richter and R. Ernst Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems______________ 514 M. Schmitz, B. Al-Hashimi, and P. Eles A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems_______________________ 522 J. Paul and D. Thomas Automatic Evaluation of the Accuracy of Fixed-Point Algorithms ___________________________________ 529 D. Menard and O. Sentieys 6A: Panel Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs Organizer: K. Brock, Virtual Silicon Technology, US Moderator: C. Edwards, Electronic Times, UK Panellists: R. Lannoo, Alcatel, BE; U. Schlichtmann, Infineon Technologies, DE; A. Domic, Synopsys, US; J. Benkoski, Monterey, US; D. Overhauser, Simplex, US; M. Kliment, Virtual Silicon, US Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs ______ 538 6B: Reconfigurable Architectures Moderators: R.. Hartenstein, Kaiserslautern U, DE; U. Kebschull, Leipzig U, DE A Video Compression Case Study on a Reconfigurable VLIW Architecture ___________________________ 540 D. Rizzo and O. Colavin A Complete Data Scheduler for Multi-Context Reconfigurable Architectures __________________________ 547 M. Sánchez-Élez, M. Férnandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. Kurdahi Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications____________ 553 G. Sassatelli, L. Torres, P. Benoit, T. Gil, C. Diou, G. Cambon, and J. Galy (Self-)reconfigurable Finite State Machines: Theory and Implementation _____________________________ 559 J. Teich and M. Köster 6C: Analogue Modelling, Layout and Sizing Moderators: H. Graeb, TU Munich, DE; G. Gielen, KU Leuven, BE A Linear-Centric Simulation Framework for Parametric Fluctuations_________________________________ 568 E. Acar, S. Nassif, and L. Pileggi Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio _____________ 576 M. Dessouky and D. Sayed

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Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets___________________________________ 581 R. Schwencker, F. Schenkel, M. Pronath, and H. Graeb High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions______________________________________________________________ 586 G. Vandersteen, P. Wambacq, S. Donnay, and F. Verbeyst 6D: Test Resource Partitioning for Embedded Cores Moderators: Z. Peng, Linköping U, SE; B. Rouzeyre, LIRMM, FR Effective Software Self-Test Methodology for Processor Cores _____________________________________ 592 N. Kranitis, A. Paschalis, D. Gizopoulos, and Y. Zorian Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression _____________ 598 A. Chandra and K. Chakrabarty Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression________________________________________________________ 604 P. Gonciari, B. Al-Hashimi, and N. Nicolici Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths______________________ 612 M. Favalli and C. Metra 6E: System Level Simulation and Modelling Moderators: B. Al-Hashimi, Southampton U, UK; P. Schwarz, FhG IIS/EAS Dresden, DE Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design ____________ 620 S. Yoo, G. Nicolescu, L. Gauthier, and A. Jerraya Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses ___________________________ 628 Z. Zheng, L. Pileggi, M. Beattie, and B. Krauter A Linear-Centric Modeling Approach to Harmonic Balance Analysis ________________________________ 634 P. Li and L. Pileggi An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor _______________________________________________________________ 640 P. Pénzes and A. Martin 6F: Hot Topic Deep Submicron Design and Timing Closure Moderator/Organizer: R. Otten, TU Eindhoven, NL Speakers: R. Camposano, Synopsys, US; P. Groeneveld, Magma Design Automation, US; R. Otten, TU Eindhoven, NL Design Automation for Deepsubmicron: Present and Future ________________________________________ 650 7A: Panel Reconfigurable SoC What Will it Look Like? Organizer: D. Davis, Actel, US Moderator: B. Lewis, Gartner/Dataquest, US Panellists: I. Bolsens, Xilinx, US; B. Gupta, STMicroelectronics, US; R. Lauwereins, IMEC, BE; Y. Tanurhan, Actel Corporation, US; C. Wheddon, Quicksilver Technology, US Reconfigurable SoC What Will it Look Like? ________________________________________________ 660

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7B: Layout Aware Logic Synthesis Moderators: A. Oliveira, INESC, PT; R. Murgai, Fujitsu Labs., US Congestion-Aware Logic Synthesis ___________________________________________________________ 664 D. Pandini, L. Pileggi, and A. Strojwas Layout Driven Decomposition with Congestion Consideration ______________________________________ 672 T. Kutzschebauch and L. Stok Improving Placement under the Constant Delay Model____________________________________________ 677 K. Sulimma, W. Kunz, I. Neumann, and L. van Ginneken Crosstalk Alleviation for Dynamic PLAs_______________________________________________________ 683 T. Tien, T. Tsai, and S. Chang 7C: Buffering and Tapering Moderators: J. Lienig, Bosch, DE; F. Johannes, TU Munich, DE Flip-Flop and Repeater Insertion for Early Interconnect Planning____________________________________ 690 R. Lu, G. Zhong, C. Koh, and K. Chao Congestion Estimation with Buffer Planning in Floorplan Design ___________________________________ 696 W. Wong, C. Sham, and F. Young Maze Routing with Buffer Insertion under Transition Time Constraints _______________________________ 702 L. Huang, M. Lai, D. Wong, and Y. Gao Optimal Transistor Tapering for High-Speed CMOS Circuits _______________________________________ 708 L. Ding and P. Mazumder 7D: Automatic Design Debug and TPG Moderators: P. Teixeira, INESC-IST, PT; B. Straube, FhG IIS/EAS Dresden, DE Incremental Diagnosis and Correction of Multiple Faults and Errors _________________________________ 716 A. Veneris, J. Liu, M. Amiri, and M. Abadir Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults ___________________________ 722 I. Pomeranz and S. Reddy FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis___________ 730 V. Vedula and J. Abraham 7E: Object Oriented System Specification and Design Moderators: W. Grass, Passau U, DE; E. Villar, Cantabria U, ES An Environment for Dynamic Component Composition for Efficient Co-Design________________________ 736 F. Doucet, S. Shukla, R. Gupta, and M. Otsuka Functional Verification for SystemC Descriptions Using Constraint Solving ___________________________ 744 F. Ferrandi, M. Rendine, and D. Sciuto The Modelling of Embedded Systems Using HASoC _____________________________________________ 752 M. Edwards and P. Green

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A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems ___________________ 760 A. Dobol and R. Vemuri 8A: Hot Topic UML: Using the Unified Modeling Language for Embedded System Specification Moderator/Organizer: L. Lavagno, Politecnico di Torino, IT The Real-Time UML Standard: Definition and Application ________________________________________ 770 B. Selic UML for Embedded Systems Specification and Design: Motivation and Overview ______________________ 773 G. Martin A UML-Based Design Methodology for Real-Time and Embedded Sytems____________________________ 776 G. de Jong 8B: Real-Time Embedded Systems Moderators: Z. Peng, Linkoping U, SE; J. Sifakis, VERIMAG, FR Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor ___________________________ 782 G. Quan and X. Hu A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis _________________________________________________________________ 788 W. Kim, J. Kim, and S. Min Extending Synchronous Languages for Generating Abstract Real-Time Models ________________________ 795 G. Logothetis and K. Schneider 8C: Interconnect Modelling Moderators: J. Phillips, Cadence Berkeley Labs, US; L. Silveira, IST/INESC, PT An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach _______________________________ 804 D. Goren, M. Zelikson, T. Galambos, R. Gordin, B. Livshitz, A. Amir, A. Sherman, and I. Wagner Closed-Form Crosstalk Noise Metrics for Physical Design Applications ______________________________ 812 L. Chen and M. Marek-Sadowska Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects ____________________________ 820 Q. Xu and P. Mazumder Library Compatible Ceff for Gate-Level Timing__________________________________________________ 826 B. Sheehan 8D: On-Line Testing and Fault Tolerance Moderators: L. Bouzaida, STMicroelectronics, FR; A. Singh, Auburn U, US Self-Checking Scheme for the On-Line Testing of Power Supply Noise_______________________________ 832 C. Metra, L. Schiano, B. Riccò, and M. Favalli Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance _____________ 837 R. Leveugle

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Exploiting Idle Cycles for Algorithm Level Re-Computing ________________________________________ 842 K. Wu and R. Karri New Techniques for Speeding-Up Fault-Injection Campaigns ______________________________________ 847 L. Berrojo, I. Gónzález, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, and C. López 8E: Design Space Evaluation Moderators: J. Teich, Paderborn U, DE; W. Kruijtzer, Philips Research, NL System Design for Flexibility________________________________________________________________ 854 C. Haubelt, J. Teich, K. Richter, and R. Ernst Accurate Area and Delay Estimators for FPGAs _________________________________________________ 862 A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering _______ 870 K. Buchenrieder, A. Pyttel, and A. Sedlmeier Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation____________________________________________________________ 875 N. Savoiu, S. Shukla, and R. Gupta 9A: Hot Topic From System Specification to Layout: Seamless Top-Down Design Methods for Analogue and Mixed Signal Applications Moderators/Organizers: I. Rugen-Herzig, Infineon Technolgies, DE; R. Sommer, Infineon Technologies, DE From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications__________________________________________________________________ 884 R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Maloberti, K. Einwich, C. Clauss, P. Schwarz, and G. Noessing 9B: Architectural Level Synthesis Moderators: P. Eles, Linkoping U, SE; B. Mesman, Philips/TU Eindhoven, NL Memory System Connectivity Exploration _____________________________________________________ 894 P. Grun, N. Dutt, and A. Nicolau Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory ____________ 902 S. Hettiaratchi, P. Cheung, and T. Clarke Multiple-Precision Circuits Allocation Independent of Data-Objects Length ___________________________ 909 M. Molina, J. Mendias, and R. Hermida 9C: Advanced Linear Modelling Techniques Moderators: P. Feldmann, Celight Inc, US; G. Vandersteen, IMEC, BE Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function ____ 916 E. Gad and M. Nakhla Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation _____________ 923 C. Coelho, L. Silveira, and J. Phillips Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods ________________ 931 Y. Chen, V. Balakrishnan, C. Koh, and K. Roy

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9D: Memory Testing and ATPG Issues Moderators: H. Obermeir, Infineon Technologies, DE; M. Sonza Reorda, Politecnico di Torino, IT An Optimal Algorithm for the Automatic Generation of March Tests_________________________________ 938 A. Benso, S. Di Carlo, G. Di Natale, and P. Prinetto Minimal Test for Coupling Faults in Word-Oriented Memories _____________________________________ 944 A. van de Goor, M. Abadir, and A. Carlin Maximizing Impossibilities for Untestable Fault Identification ______________________________________ 949 M. Hsiao Automated Modeling of Custom Digital Circuits for Test __________________________________________ 954 S. Bose 9E: Embedded Software Performance Analysis and Optimization Moderators: H. Hsieh, UC Riverside, US; R. Lauwereins, IMEC, BE False Path Elimination in Quasi-Static Scheduling _______________________________________________ 964 G. Arrigoni, L. Duchini, C. Passerone, L. Lavagno, and Y. Watanabe A Data Analysis Method for Software Performance Prediction______________________________________ 971 G. Bontempi and W. Kruijtzer A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications______ 977 N. Liveris, N. Zervas, D. Soudris, and C. Goutis A Compiler-Based Approach for Improving Intra-Iteration Data Reuse _______________________________ 984 M. Kandemir 9G: Technical Plenary 40 Years of EDA Moderator: A. Jerraya, TIMA, Grenoble, FR European CAD from the 60’s to the New Millenium______________________________________________ 992 Joseph Borel, J.B.-R&D Consulting, FR 10A: Hot Topic Design Technology for Networked Reconfigurable FPGA Platforms Organizer/Moderator: I. Bolsens, Xilinx, US Speakers: D. Verkest, IMEC, BE; S. Guccione, Xilinx, US; S. Singh, Xilinx, US Design Technology for Networked Reconfigurable FPGA Platforms _________________________________ 994 S. Guccione, D. Verkest, and I. Bolsens 10B: High-Level Synthesis and Asynchronous Pipelines Moderators: N. Dutt, UC Irvine, US; M. Renaudin, TIMA, Grenoble, FR High-Speed Non-Linear Asynchronous Pipelines _______________________________________________ 1000 R. Ozdag, P. Beerel, M. Singh, and S. Nowick Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding _____________________________ 1008 M. Ferretti and P. Beerel Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis ________________ 1016 C. Chen and M. Sarrafzadeh

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Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models _____________ 1021 Q. Zhao, B. Mesman, and T. Basten 10C: Coupling and Switching Noise Modelling within Integrated Circuits Moderators: E. Sicard, INSA, FR; G. Vandenbosch, KU Leuven, BE Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network____________________________________________________________________ 1028 T. Brandtner and R. Weigel Fast Method to Include Parasitic Coupling in Circuit Simulations___________________________________ 1033 B. Van Thielen and G. Vandenbosch Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling _____ 1038 L. Ding and P. Mazumder Macromodeling of Digital I/O Ports for System EMC Assessment __________________________________ 1044 I. Stievano, F. Canavero, I. Maio, Z. Chen, D. Becker, and G. Katopis 10D: Panel Formal Verification Techniques: Industrial Status and Perspectives Organizer: I. Moussa, TNI-Valiosys, FR Moderator: R. Pacalet, ENST Paris, FR Panellists: J. Blasquez, Texas Instruments, Villeneuve-Loubet, FR; M. van Hulst, Philips, Eindhoven, NL; A. Fedeli, STMicroelectronics, Agrate, IT; J. Lambert, TNI-Valiosys, FR; D. Borrione, TIMA-UJF, FR; C. Hanoch, Verisity, FR; P. Bricaud, Mentor Graphics, FR Formal Verification Techniques: Industrial Status and Perspectives _________________________________ 1050 10E: Power Optimization for Embedded Processors Moderators: W. Fornaciari, Politecnico di Milano, IT; L. Lavagno, Politecnico di Torino, IT Low Power Embedded Software Optimization Using Symbolic Algebra _____________________________ 1052 A. Peymandoust, T. Simunic, and G. De Micheli An Adaptive Dictionary Encoding Scheme for SOC Data Buses____________________________________ 1059 T. Lv, W. Wolf, J. Henkel, and H. Lekatsas Power Efficient Embedded Processor Ip’s through Application-Specific Tag Compression in Data Caches __ 1065 P. Petrov and A. Orailoglu Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities__________________________________________ 1072 M. Palkovic, M. Miranda, and F. Catthoor

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Poster Sessions An Approach to Model Checking for Nonlinear Analog Systems ___________________________________ 1080 W. Hartong, L. Hedrich, and E. Barke Speeding up SAT for EDA_________________________________________________________________ 1081 S. Pilarski and G. Hu Search-Based SAT Using Zero-Suppressed BDDs ______________________________________________ 1082 F. Aloul, M. Mneimneh, and K. Sakallah An Encoding Technique for Low Power CMOS Implementations of Controllers _______________________ 1083 M. Martínez, M. Avedillo, J. Quintana, M. Koegst, S. Rülke, and H. Süße Composition Trees in Finding Best Variable Orderings for ROBDDs________________________________ 1084 E. Dubrova A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs________ 1085 J. Abke and E. Barke Concurrent and Selective Logic Extraction with Timing Consideration ______________________________ 1086 P. Rezvani and M. Pedram Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions ____________________________________________________________ 1087 D. Kania Efficient and Effective Redundancy Removal for Million-Gate Circuits______________________________ 1088 M. Berkelaar and K. van Eijk Visualization of Partial Order Models in VLSI Design Flow_______________________________________ 1089 A. Bystrov, M. Koutny, and A. Yakovlev High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems________ 1090 J. Rigaud, L. Fesquet, M. Renaudin, and J. Quartana Power-Efficient Trace Caches ______________________________________________________________ 1091 J. Hu, N. Vijaykrishnan, M. Kandemir, and M. Irwin Reducing Cache Access Energy in Array-Intensive Applications ___________________________________ 1092 M. Kandemir and I. Kolcu The Use of Runtime Configuration Capabilities for Networked Embedded Systems ____________________ 1093 C. Nitsch and U. Kebschull A SAT Solver Using Software and Reconfigurable Hardware______________________________________ 1094 I. Skliarova and A. Ferrari A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems______________________________________________________________ 1095 R. Münzenberger, M. Dörfel, F. Slomka, and R. Hofmann Improved Constraints for Multiprocessor System Scheduling ______________________________________ 1096 M. Grajcar and W. Grass

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Maximizing Conditonal Reuse by Pre-Synthesis Transformations __________________________________ 1097 O. Peñalba, J. Mendias, and R. Hermida Control Circuit Templates for Asynchronous Bundled-Data Pipelines _______________________________ 1098 S. Tugsinavisut and P. Beerel Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures ____________________ 1099 O. Peyran and W. Zhuang A New Formulation for SOC Floorplan Area Minimization Problem ________________________________ 1100 C. Lee, Y. Lin, W. Fu, C. Chang, and T. Hsieh Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design ___________________________ 1101 C. Chu and F. Young EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses ________________________________________________________________ 1102 Y. Aghaghiri, M. Pedram, and F. Fallah Estimation of Power Consumption in Encoded Data Buses ________________________________________ 1103 A. García, L. Kabulepa, and M. Glesner Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis _______________________________________________________________________ 1104 T. Hieu Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques _____ 1105 A. Luchetta, S. Manetti, and M. Piccirilli The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits ___________________________ 1106 M. Stan and A. Panigrahi Substrate Parasitic Extraction for RF Integrated Circuits__________________________________________ 1107 A. Cathelin, D. Saias, D. Belot, Y. Leclercq, and F. Clément A Complete Phase-Locked Loop Power Consumption Model______________________________________ 1108 D. Duarte, N. Vijaykrishnan, and M. Irwin Statistical Timing Driven Partitioning for VLSI Circuits__________________________________________ 1109 C. Ababei and K. Bazargan DAISY-CT: A High-Level Simulation Tool for Continuous-Time ∆Σ Modulators ______________________ 1110 K. Francken, M. Vogels, E. Martens, and G. Gielen Automated Optimal Design of Switched-Capacitor Filters ________________________________________ 1111 A. Hassibi and M. Hershenson On-Chip Inductance Models: 3D or Not 3D?___________________________________________________ 1112 T. Lin, M. Beattie, and L. Pileggi Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate ____________________________________________________ 1113 H. Ymeri, B. Nauwelaers, K. Maex, D. De Roest, M. Stucchi, and S. Vandenberghe

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Compact Macromodel for Lossy Coupled Transmission Lines _____________________________________ 1114 R. Khazaka and M. Nakhla An EMC-Compliant Design Method of High-Density Integrated Circuits ____________________________ 1115 J. Levant and M. Ramdani Finding a Common Fault Response for Diagnosis during Silicon Debug _____________________________ 1116 I. Pomeranz, J. Rajski, and S. Reddy IDDT Testing of Embedded CMOS SRAMs ____________________________________________________ 1117 S. Kumar, R. Makki, and D. Binkley Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis ______________________ 1118 S. Bhunia and K. Roy An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits ___________________________________________________________________ 1119 J. Lin, C. Lee, and J. Chen On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems _____ 1120 V. Beroulle, Y. Bertrand, L. Latorre, and P. Nouet Directed-Binary Search in Logic BIST Diagnostics______________________________________________ 1121 R. Kapur, T. Williams, M. Mercer An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators ____________ 1122 M. Favalli and M. Dalpasso Fault Isolation Using Tests for Non-Isolated Blocks _____________________________________________ 1123 I. Pomeranz and Y. Zorian A Heuristic for Test Scheduling at System Level________________________________________________ 1124 M. Flottes, J. Pouget, and B. Rouzeyre Formulation of SOC Test Scheduling as a Network Transportation Problem __________________________ 1125 S. Koranne and V. Choudhary A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs_____________________________________________________________________ 1126 M. Gericota, G. Alves, M. Silva, and J. Ferreira Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider ________________________ 1127 A. Drozd, M. Lobachev, and J. Drozd An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores_____ 1128 A. Bona, M. Sami, D. Sciuto, V. Zaccaria, C. Silvano, and R. Zafalon The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines _________________ 1129 A. Sauer, G. Elst, L. Krahn, and W. John Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments____________________________________________________________ 1130 L. Indrusiak, M. Glesner, and R. Reis

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FlexBench: Reuse of Verification IP to Increase Productivity ______________________________________ 1131 S. Stöhr, M. Simmons, and J. Geishauser Mappability Estimation of Architecture and Algorithm___________________________________________ 1132 J. Soininen, J. Kreku, and Y. Qu Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS __________________________ 1133 P. Wilson, J. Ross, M. Zwolinski, A. Brown, and Y. Kiliç A Parallel LCC Simulation System __________________________________________________________ 1134 K. Hering Error Simulation Based on the SystemC Design Description Language ______________________________ 1135 F. Bruschi, M. Chiamenti, F. Ferrandi, and D. Sciuto Towards a Kernel Language for Heterogeneous Computing _______________________________________ 1136 D. Björklund and J. Lilius Top-Down System Level Design Methodology Using SpecC, VCC and SystemC ______________________ 1137 L. Cai, D. Gajski, P. Kritzinger, and M. Olivares Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors_________ 1138 L. Pozzi, M. Vuletić, and P. Ienne Steady State Calculation of Oscillators Using Continuation Methods ________________________________ 1139 H. Brachtendorf, S. Lampe, R. Laur, R. Melville, and P. Feldmann A Fast Johnson-Mobius Encoding Scheme for Fault Secure Binary Counters____________________CD-ROM only K.S. Papadomanolakis, A.P. Kakarountas, N. Sklavos and C.E. Goutis Author Index ____________________________________________________________ 1141

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DATE 2002 Executive Committee

GENERAL CHAIR Jose Epifanio da Franca ChipIdea, Lisbon, PT

PROGRAM CHAIR Carlos Delgado-Kloos U Carlos III Madrid, ES

VICE CHAIR, WEB & PUBLICATIONS Diederik Verkest IMEC, Leuven, BE

VICE PROGRAM CHAIR & TUTORIALS Norbert Wehn Kaiserslautern U, DE

PAST CHAIR AND FINANCE CHAIR Ahmed Jerraya TIMA, Grenoble, FR

PAST PROGRAM CHAIR Wolfgang Nebel Oldenburg U and OFFIS, DE

DESIGNERS’ FORUM Donatella Sciuto Politecnico di Milano, IT

SPECIAL SESSIONS Wolfgang Rosenstiel Tuebingen U, DE

HANDS-ON TUTORIALS Eugenio Villar Cantabria U, ES

AUDIO VISUAL Udo Kebschull Leipzig U, DE

POSTERS Adoracion Rueda CNM, Seville, ES

ELECTRONIC REVIEW Wolfgang Müller Paderborn U, DE

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UNIVERSITY BOOTH Marie-Minerve Louerat UPMC, Paris, FR

FRINGE MEETINGS Eric Martin LESTER-UBS, FR

UNIVERSITY BOOTH Manuel Bouyer UPMC, Paris, FR

DESIGN CONTEST Patrice Senn France Telecom, FR

AWARDS Patrice Quinton IRISA, FR

PCB SYMPOSIUM Carsten Elgert Mentor Graphics, DE

TRAVEL GRANTS Marta Rencz TU Budapest, HU

PUBLICITY Bernard Courtois TIMA, Grenoble, FR

LOCAL ARRANGEMENTS Agnieszka Konczykowska Alcatel R&I, Marcoussis, FR

PRESS LIAISON Fred Santamaria Paris, FR

EDAA REPRESENTATIVE & ASPDAC Peter Marwedel Dortmund U, DE

IEEE REPRESENTATIVE Yervant Zorian LogicVision, US

DAC REPRESENTATIVE Bryan Ackland Agere Systems, Holmdel, US

USA REPRESENTATIVE Giovanni De Micheli Stanford U, US

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ASIA REPRESENTATIVE Tokinori Kozawa Starc, JP

ICCAD REPRESENTATIVE Rolf Ernst TU Braunschweig, DE

EDA CONSORTIUM REPRESENTATIVE Larry Eberle Synopsys, US

EDA CONSORTIUM REPRESENTATIVE Pamela Parrish EDA Consortium, US

VENDORS COMMITTEE CHAIR Wes Ryder Mentor Graphics, Newbury, UK

EXHIBITION MANAGER Andrew Porter EDA, London, UK

EVENT MANAGER Gordon Adshead MDT, UK

EXHIBITION SECRETARIAT Jeremy Kenyon EDA, London, UK

CONFERENCE SECRETARIAT Sue Menzies European Conferences Edinburgh, UK

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Technical Program Chairs

SYSTEM DESIGN METHODS Rajesh Gupta UC Irvine, US

SYSTEM DESIGN METHODS Luciano Lavagno Politecnico di Torino, IT

ANALOGUE & MIXED A/D SYSTEMS Andreas Kaiser ISEN, FR

ANALOGUE & MIXED A/D SYSTEMS Piet Wambacq IMEC, BE

DESIGN OF LOW POWER SYTEMS Wolfgang Nebel Oldenburg U & OFFIS, DE

DESIGN OF LOW POWER SYSTEMS Enrico Macii Politecnico di Torino, IT

PLATFORM DESIGN Wayne Wolf Princeton U, US

PLATFORM DESIGN Natividad Martinez Madrid FZI, DE

RECONFIGURABLE COMPUTING Rudy Lawwereins IMEC, Leuven, BE

RECONFIGURABLE COMPUTING Udo Kebschull Leipzig U, DE

SYNCHRONIZATION METHODS Jordi Cortadella UP Catalunya, ES

SYNCHRONIZATION METHODS Mike Kishinevsky Intel, US

SYSTEM LEVEL SPECIFICATION Werner Grass Passau U, DE

SYSTEM LEVEL SPECIFICATION Vassilios Gerousis Infineon, DE

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REAL-TIME EMBEDDED SYSTEMS Joseph Sifakis VERIMAG, Grenoble, FR

REAL-TIME EMBEDDED SYSTEMS Edward Lee UC Berkeley, US

SIMULATION AND EMULATION Peter Schwarz FhG, Dresden DE

SIMULATION AND EMULATION Bashir Al-Hashimi Southhampton U, UK

HW/SW CODESIGN Ahmed Jerraya TIMA, Grenoble, FR

HW/SW CODESIGN Juan Carlos López Castilla La Mancha U, ES

ARCHITECTURAL SYNTHESIS Roman Hermida Madrid Complutense U, ES

ARCHITECTURAL SYNTHESIS Nikil Dutt UC Irvine, US

LOGIC & FSM SYNTHESIS Arlindo M. Oliviera IST-INESC, PT

LOGIC & FSM SYNTHESIS Wolfgang Kunz Kaiserslautern U, DE

PHYSICAL DESIGN & VERIFICATION Erich Barke Hannover U, DE

PHYSICAL DESIGN & VERIFICATION Ralph Otten TU Eindhoven, NL

INTERCONNECT & MIXED SIGNAL Helmut Graeb TU Munich, DE

INTERCONNECT & MIXED SIGNAL Luis Miguel Silveira IST/INESC ID, Lisbon, PT

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Etienne Sicard INSA/DGEI, Toulouse, FR

EMC Guy Vandenbosch KU Leuven, BE

FORMAL VERIFICATION Thomas Kropf Bosch, Reutlingen, DE

FORMAL VERIFICATION Carl Pixley Synopsys, Portland, US

SYMBOLIC TECHNIQUES Agnieszka Konczykowska Alcatel R&I, Marcoussis, FR

SYMBOLIC TECHNIQUES Francisco Fernandez CNM, Seville, ES

COLLABORATIVE DESIGN Franz Rammig Paderborn U, DE

COLLABORATIVE DESIGN Adam Pawlak ITE, Warsaw, PL

DEFECT ORIENTED TEST Michel Renovell LIRMM, Montpellier, FR

DEFECT ORIENTED TEST Jose Pineda de Gyvez Phillips, NL

ANALOGUE & MIXED SIGNAL TEST Jose Luis Huertas CNM-IMSE, Seville, ES

ANALOGUE & MIXED SIGNAL TEST Bozena Kaminska Fluence Technology, US

TEST GENERATION Joao Paolo Teixeira Lisboa U, PT

TEST GENERATION Christian Landrault LIRMM, FR

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BIST & DFT Paolo Prinetto Politecnico di Torino, IT

BIST& DFT Alex Orailoglu UC San Diego, USA

TEST PARTITIONING & SoC TEST Yervant Zorian Logic Vision, US

TEST PARTITIONING & SoC TEST Dimitris Gizopoulos Pireaeus U, GR

FIELD & ON-LINE TESTING Michael Nicolaidis IRoC Technologies, FR

FIELD & ON-LINE TESTING Dhiraj Pradhan Bristol U, UK

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Vendors Committee Wes Ryder Mentor Graphics, Newbury, UK (Chair)

Herman Beke Adelante Tech, Leuven, BE Peter Denyer Sun Microsystems, PaloAlto, US

Linda Lavin Aptix, San Jose, US Andrew Lock Synopsys, Reading, UK

Mark Gallagher Cadence, Bracknell, UK Pamela Parrish EDA Consortium, US

Jeremy Kenyon EDA, UK Andrew Porter EDA, UK

DATE Sponsors Committee

CHAIR AND EDAA CHAIR Peter Marwedel Dortmund U, DE

EDAA FINANCE CHAIR Herman Beke Adelante Technology, BE

IEEE COMPUTER SOCIETY TW Williams Synopsys, US

IEEE COMPUTER SOCIETY Yervant Zorian Logic Vision, US

RAS Alex Stempkovsky Russian Academy of Science, RUS

ECSI Jean Mermet ECSI, FR

ACM-SIGDA Jim Cohoon U Virginia, US

AUDIT CHAIR Volker Dueppe Munich, DE

EDA CONSORTIUM Larry Eberle, Synopsys, US & Pamela Parrish, EDA Consortium, US

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Technical Program Committee Bashir Al-Hashimi, Southampton U, UK

Daniel Auvergne, LIRMM, FR Florence Azais, LIRMM, FR

Carlos Azeredo Leme, ChipIdea, PT Erich Barke, Hannover U, DE

Alfredo Benso, Politecnico di Torino, IT Reinaldo A. Bergamaschi, IBM, US

Michel Berkelaar, Magma Design Automation, NL Gerard, Berry, Esterel Technologies, FR

Christian Berthet, STMicroelectronics, FR Shuvra S. Bhattacharya, Maryland U, US

David Blaauw, Motorola, US Massimo Bombana, Siemens ICN, IT

Frank Brglez, NC State U, US Randal E. Bryant, Carnegie Mellon U, US

Klaus Buchenrieder, Infineon Technologies, DE Jean-Paul Calvez, IRESTE-Nantes U, FR Paolo Camurati, Politecnico di Torino, IT Flavio Canavero, Politecnico di Torino, IT

Marco Carilli, STMicroelectronics, FR Gunnar Carlsson, Ericsson Radio Systems, SE

Johan Catrysse, KHBO, BE Sreejit Chakravarty, Intel, US Victor Champac, INAOE, MX

Abijit Chatterjee, GATECH, US Kuang-Chien Cheng, Verplex Systems, US Peter Y.K. Cheung, Imperial College, UK

Vivek Chickermane, IBM, US Juan Chico, CNM Seville, ES

Kiyoung Choi, Seoul National U, KR Marcello Coppola, STMircoelectronics, FR

Jordi Cortadella, UP Catalunya, ES Bernard Courtois, TIMA, FR

Jan Craninckx, Alcatel Microelectronics, BE Walter Daems, KU Leuven, BE

Carl Das, IMEC, BE Ali Dasdan, Synopsys, US

Giovanni De Micheli, Stanford U, US Carlos Delgado Kloos, Carlos III de Madrid U, ES

Serge Demidenko, Massey U, NZ Carsten Demuth, Infineon Technologies, DE

Alex Doboli, New York State U, US Rolf Drechsler, Bremen U, DE

Nikil Dutt, UC Irvine, US George E. Economakos, Athens NTU, GR

Martyn Edwards, UMIST, UK Stephen A. Edwards, Columbia U, US

Petru Eles, Linköping U, SE Ibrahim Elfadel, IBM, US Marc Engels, IMEC, BE

Luis Entrena, Carlos III de Madrid U, ES

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Rolf Ernst, TU Braunschweig, DE Hans Eveking, TU Darmstadt, DE

Peter Feldmann, CeLight, US Uwe Feldmann, Infineon Technologies, DE

Francisco Fernandez, IMSE-CNM, U Seville, ES Joan Figueras, UP Catalunya, ES

Franco Fiori, Politecnico di Torino, IT Limor Fix, Intel, ISR

Marie-Lise Flottes, LIRMM, FR William Fornaciari, Politecnico di Milano, IT

Norbert Fristacky, Slovak TU, SK Hideo Fujiwara, Nara IT, JP Daniel Gajski, UC Irvine, US

Jim Garside, Manchester U, UK Catherine Gebotys, Waterloo U, CA

Daniel Geist, IBM Haifa Research Lab, ISR Eberhard Gerbracht, TU Braunschweig, DE

Vassilios Gerousis, Infineon Technologies, DE Georges Gielen, KU Leuven, BE

Dimitris Gizopoulos, Pireaus U, GR Manfred Glesner, TU Darmstadt, DE

Michael Goessel, Potsdam U, DE Helmut Graeb, TU Munich, DE

Miltos Grammatikakis, ISD SA, GR Werner Grass, Passau U, DE

Thorsten Groetker, Synopsys, DE Guido Gronthoud, Philips, NL

Herbert Gruenbacher, Carinthia Tech. Inst., AT Herve Guegan, Mentor Graphics Anacad, FR

Rajesh Gupta, UC Irvine, US David Harris, Harved Mudd College, US

Ian G. Harris, Massachusetts U, US Peter Harrod, ARM, UK

Reiner Hartenstein, Kaiserslautern U, DE Takashi Hasegawa, Fujitsu, JP

Sybille Hellebrand, Innsbruck U, AT Joerg Henkel, NEC, US

Roman Hermida, Madrid Complutense U, ES Hiromi Hiraishi, Kyoto Sangyo U, JP

Mokhtar Hirech, Synopsys, US H. Peter Hofstee, IBM, US

Nuno Horta, IST, PT Harry Hsieh, UC Berkeley, US

Jose Luis Huertas, CNM Seville, ES Ed Huijbregts Magma Design Automation, NL

Sorin Huss, TU Darmstadt, DE Thomas Ifström, Robert Bosch GmbH, DE

Margarida F. Jacome, U Texas at Austin, US Jörn W. Janneck, UC Berkeley, US

Axel Jantsch, Royal Inst. of Technology, SE Ahmed Jerraya, TIMA Grenoble, FR Frank M. Johannes, TU Munich, DE

Werner John, FhG-IZM, DE Andreas Kaiser, IEMN-ISEN, FR

Bozena Kaminska, Fluence Technology, US Ramesh Karri, Polytech U Brooklyn, US

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Tom Kazmierski, Southampton U, UK Udo Kebschull, Leipzig U, DE Hans Kerkhoff, Twente U, NL

David Kinniment, Newcastle U, UK Kozo Kinoshita, Osaka Gaukin U, JP

Michael Kishinevsky, Intel, US Bernd Kleinjohann, Paderborn U/C-LAB, DE

Gernot Koch, Bridges2Silicon Inc, US Michael Koch, Stralsund FH, DE

Juergen Koehl, IBM Deutschland GmbH, DE Cheng-Kok Koh, Purdue U, US

Agnieszka Konczykowska, Alatel R&I, FR Reiner Kress, Infineon Technologies, DE Thomas Kropf, Robert Bosch GmbH, DE

Wido Kruijtzer, Philips, NL Bram Kruseman, Philips, NL

Ernest S. Kuh, UC Berkeley, US Sandip Kundu, Intel, US

Wolfgang Kunz, Kaiserslautern U, DE Fadi Kurdahi, Morpho Technologies, US

Christian Landrault, LIRMM, FR Rudy Lauwereins, IMEC, BE

Luciano Lavagno, P Torino, IT Edward Lee, UC Berkeley, US Domine Leenaerts, Philips, NL

Rainer Leupers, Dortmund U, DE Regis Leveugle, TIMA Grenoble, FR

Stan Liao, Synopsys, US Jens Lienig, Robert Bosch GmbH, DE

Vanco Litovski, Elektronski Fakultet, YU Monica Lobetti Bodoni, Siemens ICN SpA, IT Juan Carlos Lopez, Castilla-La Mancha U, ES

Weikko Loukussa, Nokia, FIN Patrick Lysaght, Xilinx, UK

Fadi Maamari, LogicVision Inc, US Enrico Macii, P Torino, IT

Jan Madsen, TU Denmark, DK Kenneth Mandl, Teradyne Inc, US

Stefano Manetti, Florence U, IT Hans Manhaeve, Q-Star Test, BE

Diana Marculescu, Carnegie Mellon U, US Erik Jan Marinissen, Philips, NL

Grant Martin, Cadence Design Systems, US Natividad Martinez Madrid, FZI Karlsruhe, DE

Peter Maxwell, Agilent, US Ken McMillan, Cadence Berkeley Labs, US

Fernando Medeiro, Seville U, ES Renu Mehra, Clearwater Networks, US Thomas F. Melham, Glasgow U, UK

Bart Mesman, Philips, NL Cecilia Metra, Bologna U, IT

Volker Meyer zu Bexten, TEMIC Semiconductors GmbH, DE Shin-ichi Minato, NTT, JP

Miguel Miranda, IMEC, BE Yukiya Miura, Tokyo U, JP

Klaus Mueller-Glaser, Karlsruhe U, DE

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Peter Muhmentahler, Infineon Technologies, DE Tamal Mukherjee, Carnegie Mellon U, US

Michael Münch, Alcatel, BE Rajeev Murgai, Fujitsu, US

Michel Nakhla, Carleton U, CA Sanjiv Narayan, Cadence Design Systems, IND

Zainaladedin Navabi, Northeastern U, US Wolfgang Nebel, OFFIS/Oldenburg U, DE Michael Nicolaidis, iRoC Technologies, FR

Dimitris Nikolos, Patras U, GR Pascal Nouet, LIRMM, FR

Franc Novak, Jozef Stefan Institute, SL Enrico Novarini, STMicroelectronics, IT

Kasia Nowak, Philips, NL Steven Nowick, Columbia U, US

Hermann Obermeir, Infineon Technologies, DE Arlindo Oliveira, IST / INESC ID, PT

Hidetoshi Onodera, Kyoto U, JP Alex Orailoglu, UC San Diego, US

Ralph Otten, TU Eindhoven, NL Ian Page, Imperial College, UK

Sri Parameswaran, Queensland U, AU Abelardo Pardo, Carlos III de Madrid U, ES

Antonis Paschalis, Athens U, GR Robert Pasko, IMEC, BE Adam Pawlak, ITE, PL

Massoud Pedram, Southern California U, US Zebo Peng, Linköping U, SE Ian Phillips, ARM Ltd, UK

Joel Phillips, Cadence Design Systems, US Stanislaw Piestrak, TU Wroclaw, PL

Jose Pineda, Philips, NL Carl Pixley, Motorola, US

Jonas Plantin, Ericsson Radio Systems AB, SE Dhiraj Pradhan, Bristol U, UK

Paolo Prinetto, Politecnico di Torino, IT Elke Radeke, Incony AG, DE

Martin Radetzki, Sci-Worx GmbH, DE Franz Rammig, Paderborn U/C-LAB, DE

Marc Renaudin, TIMA Grenoble, FR Marta Rencz, Budapest TU, HU Michel Renovell, LIRMM, FR

Jochen Rivoir, Agilent, DE Angel Rodriguez-Vazquez, CNM Seville, ES

Jerzy Rosenblit, Arizona U, US Wolfgang Rosenstiel, FZI Kalrsruhe/Tübingen U, DE

Franz Rossler, Thesys GmbH, DE Frederic Rousseau, TIMA Grenoble, FR

Bruno Rouzeyre, LIRMM, FR Kaushik Roy, Purdue U, US

Adoracion Rueda, CNM Seville, ES Irmtraud Rugen-Herzig, Infineon Technologies, DE

Jerzy Rutkowski, Silesian TU, PL Frank Sabath, Wehrwissenschaftliches Inst., DE

Sachin Sapatnekar, Minnesota U, US Michel Sarlotte, Thales Communications, FR

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Gabriele Saucier, Design and Reuse, FR Patrick Schaumont, UC Los Angeles, US

Reimar Scherer, TU Dresden, DE Guido Schumacher, Oldenburg U, DE

Peter Schwarz, FhG IIS/EAS Dresden, DE Donatella Sciuto, P Milano, IT

Carl Sechen, Washington U, US Ralf Seepold, FZI Karlsruhe, DE Jaume Segura, Illes Balears U, ES

Bran Selic, Rational, US Tom Shiple, Synopsys, FR

Samvel Shoukourian, Virage Logic, US Etienne Sicard, INSA, FR

Joseph Sifakis, Verimag, FR Luis Miguel Silveira, IST / INESC, PT Jerry Soden, Sandia National Labs, US

Ralf Sommer, Infineon Technologies, DE Matteo Sonza Reorda, Politecnico di Torino, IT

Mircea Stan, Virginia U, US Janusz Starzyk, Ohio U, US

Thomas Steinecke, Infineon Technologies, DE Franz-Josef Stewing, Materna GmbH, DE

Michiel Steyaert, KU Leuven, BE Leon Stok, IBM, US

Bernd Straube, FhG IIS/EAS Dresden, DE Steve Sunter, LogicVision Inc, CA Atsushi Takahashi, Tokyo IT, JP

Steffen Tarnick, Satcon, DE Jürgen Teich, Paderborn U, DE

Joao Paulo Teixeira, IST, PT Lothar Thiele, ETH Zurich, CH Claudio Turchetti, Ancona U, IT Raimund Ubar, Tallinn TU, EE

Dirk Van Troyen, De Nayer Inst, BE Guy Vandenbosch, KU Leuven, BE

Gerd Vandersteen, IMEC, BE Moshe Vardi, Rice U, US

Ingrid Verbauwhede, UCLA, US Tiziano Villa, PARADES, IT

Eugenio Villar, Cantabria U, ES Flavio Wagner, UFRGS BRZ, MX

Duncan M. Walker, Texas A&M U, US Piet Wambacq, IMEC, BE

Norbert Wehn, Kaiserslautern U, DE Wayne Wolf, Princeton U, US

Martin D.F. Wong, U Texas at Austin, US Cheng-Wen Wu, National Tsing Hua U, ROC

SungJoo Yoo, IMAG, FR Roberto Zafalon, ST Microelectronics, IT

Gerhard Zimmermann, Kaiserslautern U, DE Yervant Zorian, LogicVision Inc, US Mark Zwolinski, Southampton U, UK

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Reviewers The DATE Executive Committee gratefully acknowledges the assistance of the following persons in the review process.

Antonio Acosta Andrea Acquaviva Amit Agarwal Yazdan Aghaghiri Chuck Alpert Sameh Asaad Sigal Asaf Veronique Aubert Nadine Azemard Paolo Bacchetta Werner W. Bachmann John Bainbridge Edna Barros Iwan Basten Marcus Bednara S.P. Beeby Djilali Belkadi Tarek Ben Ismail Shoham Ben-David Luca Benini Nico Benschop Davide Bertozzi Soumendu Bhattacharya Subhrajit Bhattacharya Swarup Bhunia Alessandro Bogliolo Pascal Bolcato Andrea Bona Gianluca Bontempi C. Brandolese Forrest Brewer Erik Brockmeyer Davide Bruni Klaus Buchenrieder Gianpiero Cabodi Lukai Cai Aiqun Cao Josep Carmona Ricardo Carmona Luigi Carro Giorgio Casinovi Paul Caspi Francky Catthoor Wander Cesario K.C. Chen Wei-Chung Chen Yiran Chen Eli Chiprout

Lih-yih Chou Radim Cmar Cristiano Coelho de Arauo John Compiet Massimo Conti Paolo Crippa Miroslav Cupak David Cyriuk Karthik Dantu Erwin de Kock Jose M. de la Rosa Rocio del Rio Mario Diaz Nava Carl Dickey Charles Dike Petr Dobrovolny Rainer Doemer Rafael Dominguez-Castro Anouar Dziri Wolfgang Eberle Gerard Eichenmueller Roy Emek Tony Ewing Sune Fallgard Nielsen Michele Favalli Jorge R. Fernandes Milagros Fernandez Viktor Fernandez Fabrizio Ferrandi Eva Fordran Ana Teresa Freitas Martin Frerichs Tomohiro Fujita Kunihiro Fujiyoshi Marco Garatti Marco Gavazzi Daniel Geist Andreas Gerstlauer Cedric Ghez Susanne Graf Miltos Grammatikakis Vincent Gravot Peter Grun Oscar Guerra Matthias Gulbins Sumit Gupta Yajun Ha Achintya Halder

Frank Hannig Masanori Hashimoto Masaki Hashizume Christian Haubelt Chen He Domenik Helms Eckhard Hennig Andreas Hermann Stephan Hermanns Payam Heydari J. Ignacio Hidalgo Yoshinobu Higami Alireza Hodjat Stefan Hoereth Leszek Holenderski Hans Holten-Lund Jiang Hu Hideyuki Ichihara Yonghee Im Ali Iranli Anoop Iyer Etienne Jacobs Marek Jersak Jie-Hong Jiang Jorge Juan-Chico Martin Kahlert Krishnan Kalias Timothy Kam Chang Woo Kang M. Karels Juergen Karmann Ramesh Karri Meenakshi Kaul X. Kavousianos Idris Kaya Sharon Keidar Hyung-il Kim Jae-Joon Kim Desmond A. Kirkpatrick Gernot Koch Alex Kondratyev Ronald Konemund Nektarinos Kranitis Viktor Kravets Lars Kruse James Kukula Thomas Kutzschenbauch W. Stephen Lacy

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Marcello Lajolo Waiching Lam Juan Lanchares Holger Lange Viktor Lapinskii Katarzyna Leijten-Nowak Haris Lekatsas Chen Li Jin-Fu Li Jianlin Liang Marisa Lopez-Vallejo Ruibing Lu Marcelo Lubaszewski Gabriele Luculli Tony Ma Youngran Ma Alberto Macii Jean Christophe Madre Carsten Malonnek Leonardo Mangeruca Theodore Marescaux Igor Markov Bingfeng Mei M. Melham Jose Mendias Michael Mirbeth Hiroshi Miyashita Fan Mo M. Carmen Molina Mark Moulin Francisco Moya Jose M. Moya Enric Musoll Ulrich Nageldinger Alberto Nannarelli Jagan Narasimhan Rolf Neubert Gabriela Nicolescu Carsten Nitsch Bernd Obermeier Joerg Oehmen Kenichi Okada Markus Olbrich Mauro Olivieri Simone Orcioni Moez Ouni Martin Palkovic David Pan Francesco Papariello Robert Pasko Enric Pastor Srinivas Patil

Bipul C. Paul Yanick Paviot M. Pavlovic Steen Pedersen Junyu Peng Eduardo Peralias Belen Perez-Verdu Carl R. Pertry Satish Pillai Luigi Pomante Massimo Poncino Stefano Quer Anand Ramachandran Sanjay Ramnath Juan Ramos-Martos Philippe Raynaud Lakshmi Reddy Marc Renaudin Iris Reuveni Peyman Rezvani Kai Richter Luc Rijnders Fernando Rincon Elisenda Roca Erven Rohou Oriol Roig Roberto Rossi Jerzy Rozenblit A.E. Ruehli Julien Ryckaert Biranchinath Sahu Keishi Sakanushi Lorenzo Salvemini Pablo Sanchez Marcos Sanchez-Elez Sergei Sawitzki Prashant Saxena Eike Schmidt Jens Schoenherr Andrew Seawright Alexander Sedlmeier Eric Seelen Luc Semeria Matthias Senn Narendra Shenoy Dongwan Shin Ofer Shtrichman Antoine Sirianni Naran Sirisantana Frank, Slomka Leonel Sousa Jens Sparso

Richard Stahl Richard Stahl Christian Stangier Ted Stanion Phillip Stanley-Marbell Ken Stevens Richard Stolzman Erik Stoy Paul Stravers Chih-Ping Su Haihua Su Qing Su Andrew Sullivan Madhavan Swaminathan Armando Tacchella Hiroshi Takahashi Emil Talpes Shantanu Tarafdar Alexander Taubin Lionel Torres Stavros Tripakis Norbert Unger Jos van Eijndhoven Chris Van Hoof Tycho Van Meeuwen Arnout Vandecappelle Mauricio Varea Fabrice Veerse Haridimos T. Vergos Diederik Verkest Tiziano Villa Stefan Voegele Shin’ichi Wakabayashi Chih-Wea Wang Rui Wang Ralph Weper Kaije Wu Zhu Xiaoke Qiang Xie Peng Yang Nina Yevtushenko Chantal Ykman Hiroyuki Yotsuyanagi Sergio Yovine Haobo Yu Emmanuel Zarpas Pei Zhang Guoan Zhong Chengwen Zhuang Dirk Ziegenbein Stefan Zimmermann

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Welcome to Date 2002 On behalf of the Executive and Technical Program Committees, we take great pleasure in welcoming you

to Paris and to DATE 02, the single, most comprehensive European Conference and Exhibition event bringing together academic researchers, industry specialists, users and vendors in the fields of Design, Automation and Test of electronic circuits and systems.

The endless quest for faster, cheaper, smaller electronic products, particularly for the growing consumer and communications markets, dictate that increasingly complex designs be generated in continuously shrinking time scales. But while design time has been reduced by possibly as much as 70 percent over the past few years, the cost of design has significantly increased and continues to grow. This makes design automation a strategic technology for modern electronic systems, from simple ASICs via embedded IP cores to large systems on chip made of heterogeneous processors communicating via on-chip networks.

DATE has become the pre-eminent European conference tapping into a large reservoir of research and development activities in the field of design technology. World leading companies in wireless communications and automotive industries have led to the emergence of recognised European specialities in Embedded Systems as well as IP and SoC Technologies, particularly with a strong mixed-signal content. These are three of the most important driving forces behind IT’s explosive growth and the main contributors to accelerate the pace of electronic integration allowing complex systems to be built into a single chip. DATE is a unique event where the latest scientific and technological developments are brought to public from the leading players in the field. DATE, therefore, offers a once-in-a-year occasion to find out more about the technical and architectural trends of circuits and systems, small and large, and the design automation and test challenges they bring to tool vendors and PCB companies as well as semiconductor and IP providers alike.

DATE 02 has received a total of 476 papers submitted to the regular scientific tracks of the Conference, a very significant 60 percent increase in the number of submissions in comparison to the previous edition. The Program Committee has had the hard and always difficult task of selecting 88 papers for long presentations, 54 papers for short presentations and 68 papers for presentation as posters. An additional 46 papers will be presented in the Designers’ Forum which were selected from a record breaking 70 submissions. Last but not least, 14 Special Sessions have been chosen to bring stimulating insights and vibrant discussions in state-of-the-art topics. Due to such a large number of excellent contributions selected by the Technical Program Committee, the Conference Program has been extended from 5 to 6 parallel tracks.

In complement to the main technical and scientific Program, we have designed a number of valuable education activities in the days before and after the conference. These are the Pre-Conference Tutorials on Monday, already a tradition at DATE, and two new full day Master Courses that will take place just after the conference on Friday and which will address practical design-oriented issues of system-on-chip applications. The organization of many Hands-on-Tutorials, a PCB Symposium, a University Booth, vendor presentations, fringe meetings, and social events offer a wide variety of extra opportunities to meet and exchange information on relevant issues for the design, automation and test communities.

Many volunteers have given their best efforts to make this Conference and Exhibition an outstanding event. We would like to thank all the members of the Sponsors Committee, the Executive Committee, the Program Committee, the Vendors Committee and the Exhibitors, as well as all the Authors, Speakers, Session Organizers, Session Chairs, and Reviewers for their continued interest, energy and support to DATE. We hope that you will enjoy the DATE 02 Conference and Exhibition as much as all of us have enjoyed organising it for you.

Jose da Franca, General Chairman Carlos Delgado Kloos, Program Chairman

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Best Paper Awards Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the most outstanding papers of the previous year’s conference. The selection is based on the results of the reviewing process and the voting by the conference participants. The paper selected as the most outstanding in the field of CAD (track A) is:

Trace-Driven Application Modeling for System-Level Performance Analysis

by Radu Marculescu and Amit Nandiof Carnegie Mellon University,, USA The authors address the problem of selecting a platform for a set of target multimedia applications, and use Stochastic Automata Networks to carry out a system-level analysis. This method is illustrated on an MPEG-2 video decoder application. The paper selected as the most outstanding in the field of Tools (track B) is:

An Extension of SystemC for Mixed Multi-Level Communication Modeling and Interface-Based System Design

by Robert Siegmund and Dietmar Mueller of Chemnitz University of Technology, Germany

The authors extend SystemC with a new design unit called the interface and illustrate this extension with the modeling of the digital part of a wireless SmartCard transponder-reader/writer system. The paper selected as the most outstanding in the field of Test (track C) is: Efficient Test Data Compression and Decompression for System-on-a-Chip Using Integral Scan Chains and

Golomb Coding

by Anshuman Chandra and Krishnendu Chakrabarty of Duke University, USA

The authors consider a new compression decompression architecture for testing embedded cores in a SoC. They demonstrate the effectiveness of this approach by applying it to the ISCAS 89 benchmark circuits.

Congratulations to the winners!

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Tutorials A1 System Level Specification Beyond RTL

Organizer: Daniel D Gajski, UC Irvine, US Speakers: Jianwen Zhu, Toronto U, CAN Ahmed Jerraya, TIMA, Grenoble, FR Andreas Gerstlauer, UC Irvine, US Daniel D Gajski, UC Irvine, US

Complexities of present systems or SoC designs are forcing the movement to a higher level of abstraction than RTL. With most of the system containing a large portion of software, the present languages, methodologies and tools are not adequate to tackle system-level design. The movement to programming languages or extensions of programming languages seems to be in the right direction. In this tutorial we will discuss the basic models of computation and requirements for specifying software, hardware and complete systems. Furthermore we will give an overview of available languages, methods and models. Then, we will discuss some experiments in describing systems with presently leading system level languages such as SystemC and SpecC. Finally, we will give an overview of other specification efforts, discuss the essential issues surrounding system-level design specification, synthesis and verification, and forecast future trends in system-level design flows. B1 Low Power/Low Energy Embedded Software

Organizer: Peter Marwedel, Dortmund U, DE Speakers: Peter Marwedel, Dortmund U, DE Luca Benini, Bologna U, IT

With a focus on programmable embedded systems, this tutorial will: - survey the interaction of architecture, operating systems, compilers and memories from a power/energy focus - present specific contributions of each part to power and energy, and - outline software techniques for minimisation of power/energy. In the first section, an introduction to the topic will be provided. Due to the large influence of the memory architecture on the total energy consumption, different memory architectures will be presented next. We will show how partitioned memories can help reducing the energy consumption. In the next section, we will describe how partitioned memory architectures and other features of embedded systems can be exploited in compilers. This includes the exploitation of caches. In addition, this includes an analysis of the size of register files. Furthermore, we will explain techniques for reducing the memory traffic by global optimisations designed for multimedia applications. This section also comprises a description of applicable standard compiler optimisations and their potential for energy reductions as well as a brief introduction to compression techniques. The final section describes system software and real-time operating system (RTOS) issues. This will include hardware for RTOS-based power management, software support for power management, power-aware process scheduling and power-aware device management. Exploitation of application-specific information and power management of distributed systems will also be covered.

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C1 Test Resource Partitioning Strategies for SoC Organizer: Yervant Zorian, LogicVision, US Speakers: Yervant Zorian, LogicVision, US Michael Rodgers, Intel, US

The 2001 ITRS Roadmaps have been expanded to address more of the test cost challenges that impact SoC design and manufacturing test processes. In the area of test challenges, System-on-Chip (SoC) designs are included in the test chapter for the first time. In addition, new trends in manufacturing test resources are covered for the first time. This tutorial sheds light on the SoC test requirements in terms of embedded and external test resources. It analyses several challenges described in ITRS 2001 roadmaps, and presents strategies to adopt in order to address these challenges. The tutorial concentrates on the on-chip trade-offs, centralised and distributed test resources, and their scheduling solutions. It also discusses the off-chip test resources and their partitioning between hardware and software. The tutorial concludes by looking into future SoC trends and the corresponding test resource partitioning (TRP) needs. This tutorial is part of the IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2002 E1 Design Methodologies and CAD Tools for Mixed-Signal and RF ICs

Organizer: Georges Gielen, KU Leuven, BE Speakers: Georges Gielen, KU Leuven, BE Geert Van der Plas, KU Leuven, BE

The growth of wireless services and other telecom applications increases the need for low-cost highly integrated solutions with very demanding performance specifications. This requires the development of intelligent front-end architectures that circumvent the physical limitations posed by the technology. In addition, with the evolution towards ultra deep submicron CMOS technologies, the design of SoC will emerge which are increasingly mixed-signal designs. The desire to do hand-crafted, one-transistor-at-a-time analogue design is increasingly at odds with the current time-to-market constraints and hence the need for more analogue design productivity, practical circuit and layout synthesis, and reliable verification at all levels of the mixed-signal hierarchy. This tutorial will present the recent progress and current state-of-the-art in design tools and methodologies for complex mixed-signal designs as well as for RF IC design. Different aspects will be covered ranging from design methodologies and behavioural modelling to techniques for analogue circuit and layout synthesis. The techniques will be addressed from a designer point of view, so that attendees can assess how the techniques could be integrated to improve their current design practice. The tutorial will also include on-line demonstrations of advanced research tools in this area so that attendees can get an even better idea of the capabilities and power of the presented material. A2 Platform Based Design

Organizer: Rolf Ernst, TU Braunschweig, DE Speakers: Rolf Ernst, TU Braunschweig, DE Michael Münch, Alcatel, BE

Platform based design uses architecture templates and libraries of complex configurable hardware and software components to reach the productivity required for complex System-on-Chips (SoC) design. Platform design methodologies must go hand-in-hand with architecture and library development to enable efficient mapping of applications to platforms. The tutorial will give insight to the architectures and methodologies of platform based SoC design and highlight some of the open issues and caveats. In the introduction, we will define platform-based design from both an application as well as an architectural perspective. We will identify system components and investigate various design decisions that have to be made when designing platform architectures and components that can serve as generic building blocks in platform-based design. We will then discuss the necessary support in design methodology required to enable an efficient design

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process around such platforms. The second part of the tutorial will illustrate some of these issues through the design of a generic embedded processor-based platform designed and in use across various business divisions in Alcatel. Emphasis will be put on architectural trade-offs, as well as modelling and validation of designs based on the platform. In the third part of the tutorial, we will highlight some of the tough design problems which arise from integration of heterogeneous hardware and software IP components on a platform. We will focus on performance and load analysis and optimisation in the context of multiprocessor platforms running real-time operating systems. B2 Low Power Hardware Design

Organizer: Wolfgang Nebel, OFFIS, DE Speakers: Wolfgang Nebel, OFFIS, DE Eike Schmidt, OFFIS, DE

This tutorial addresses system-level, algorithm, and RTL designers who are facing power problems in their designs. Power consumption is not a second-class citizen any more. More and more ASIC design projects have constraints on the power consumption. The constraints might be due to the chip package, reliability issues, or the battery lifetime of mobile applications. This tutorial presents techniques to estimate and minimise power consumption of ASIC hardware implementations. Different levels of abstraction are addressed. The first part gives a brief overview of available power estimation tools and the underlying methodologies. Transistor, gate, RT, algorithm, and system-level tools and techniques are presented. The second part discusses design techniques to minimise power and energy consumption. The tutorial focuses on the higher levels of abstraction, from system down to RT level, where most power savings can be gained. For system level optimisation, techniques like power management, bus encoding, data compression, memory hierarchy optimisation as well as voltage and frequency scaling are presented. Also addressed are approaches like algorithm selection, algorithm transformations, and common case computation. Examples of RT-level optimisation techniques which will be discussed are memory access optimisations, resource sharing and parallelisation, operand isolation, as well as clock gating. C2 Design and Testing Challenges for Low-Voltage Scaled CMOS Circuits

Organizer: Kaushik Roy, Purdue U, US Speakers: Kaushik Roy, Purdue U, US Ali Keshavarzi, Intel, US

This tutorial focuses on challenges of low-voltage CMOS design and test. As technology scales, leakage and leakage control becomes critical for design and test of integrated circuits. We explain test techniques for intrinsically leaky ICs and present measured data from industry. The following topics will be covered in detail: Scaling of MOS devices; Low voltage CMOS design styles; Cross-talk and predictable design; Transistor threshold scaling for high-performance designs; Leakage currents in CMOS circuits; Leakage control such as multiple Vt CMOS, dynamic Vt CMOS, transistor stacking and their implication to testing; Testing of low-voltage, low-threshold CMOS circuit and memories under elevated background leakage; Dynamic current testing; BIST for low-power circuits. This tutorial is part of the IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2002

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E2 Test-Based Methods for Design Verification and Diagnosis Organizer: Dhiraj K. Pradhan, Bristol U, UK Speaker: Dhiraj K. Pradhan, Bristol U, UK Adit Singh, Auburn U, US

The interplay between test and design is becoming ever-more crucial. Often, manufacturing problems are, in fact, rooted in design problems. Consequently, understanding design verification helps test engineers in communicating with design engineers. Completion of this tutorial will help facilitate communication between test and design groups. This tutorial is aimed at giving test engineers an introduction to the use of test techniques for design verification and diagnosis. The following topics will be covered: • Basic concepts of design flow • Basic concepts of logic verification • Application of test concepts and techniques to design verification • Application of test concepts and techniques to design diagnosis Both combinational and sequential circuit design verification and diagnosis will be discussed. This tutorial is part of the IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2002

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Master Courses M1 Design of Digital VLSI Signal Processing Chips

Organizer: Tobias Noll, RWTH Aachen, DE Speakers: Tobias Noll, RWTH Aachen, DE Lajos Gaszi, Infineon, DE Matthias Schöbinger, Infineon, DE Jos Huisken, Philips Research Lab, NL

The enabling key technologies and driving forces for today’s and future Mobile, Internet and Broadband Multimedia systems are Digital Signal Processing and Optoelectronics. At the boundary between the higher layers and the physical transmission medium (wireless, optical, cable, storage, etc.) more and more sophisticated DSP technologies are required. Although the performance of embedded DSP kernels continuously increases, the performance required for the implementation of those advanced DSP systems increases even faster. Adding high performance co-processor blocks dedicated to standard functionalities (like filtering, convolution and error decoding) and applying an optimised HW/SW split significantly reduces DSP load, releasing flexible DSP resources for added value applications. Even more important in many applications is the resulting dramatic reduction of power dissipation and silicon area. An additional implementation alternative becoming more and more attractive is the use of re-configurable FPGA-like blocks. This leads to heterogeneous System-on-Chip architectures, where the most important challenges are to find the ideal HW/SW and analogue/digital partitioning for minimising system costs as silicon area, power dissipation, design effort, testability, etc. Keys to the success of this approach are 1) an early interaction between system level requirements and implementation issues, and 2) short development times. Parameterised, fairly accurate cost models here enable the evaluation of the high-dimensional design space with fast iteration cycles on algorithmic system level and are the basis for tradeoffs between system requirements and implementation cost already in an early phase of the system development. Techniques like minimisation of application-specific weighted complexity measures or Pareto techniques can be applied to support this evaluation process. In designing the dedicated high-performance/low-power hardware blocks to be used in those heterogeneous architectures a careful optimisation on all levels of deep-sub-micron CMOS design is mandatory. On the algorithmic system and architectural level, equivalence transformations, pipelining, re-timing, look-ahead, as well as pre-compute-and-select techniques together with the use of redundant number representations are applied in order to find attractive solutions coping with the performance requirements as well as the I/O and memory bandwidth problem. Parallelisation and timesharing techniques are applied to match the intrinsic throughput of the optimised building blocks to the specified one. On logic and circuit level, proper clocking schemes and logic building blocks have to be selected, suiting well to the technology and supply voltage to be used, the noise margin requirements and fitting to the switching activity at the according instance. Finally, on the layout level only a careful dimensioning, placement, and routing strategy allows competitive solutions by avoiding instead of coping with the dramatically increasing interconnect delay issues. Preserving the high degree of locality inherent in most DSP algorithms at arithmetic level during the whole mapping process ensures highest throughput, small silicon area and even more important, lowest possible power dissipation. The proper use of these strategies and techniques will be explained on exemplary challenging, actually industrial relevant systems and architectures. Benchmark comparisons demonstrate the benefit of this approach.

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M2 Systems and Networks on Chip Organizer: Ahmed Jerraya, TIMA, Grenoble, FR Speakers: Giovanni De Micheli, Stanford U, US Luciano Lavagno, Politecnico di Torino, IT Sungjoo Yoo, Inter-University Semiconductor Research Centre, Seoul, KR Ahmed Jerraya, TIMA, Grenoble, FR

The ITRS roadmap predicts that in 2005, 70 percent of ASICs will include at least one embedded instruction set processor. In this case, most ASICs will be SoCs (Systems-on-Chip). This prediction is not only confirmed but strengthened: SoCs will include several instruction-set processors in the case of applications such as mobile terminals (e.g. GSM), set-top boxes (e.g. pnx 8500 from Philips), game processors (e.g. PlayStation 2 from Sony) and network processors. All the above designs correspond to mass market products and are (or will be) integrated on a single chip for production cost reasons. It is even expected that these applications act as the main drivers for the semiconductor industry. Most system and semiconductor houses are working on platforms allowing the integration of several cores (CPU, DSP, MCU, co-processors) and sophisticated communication networks (hierarchical bus, TDMA-based bus, point-to-point connection and packet routing switch) on a single chip. The trend is then to build large designs as a networked System-on-Chip. The game is now to interconnect standard components as we used to do for boards a few years ago. This evolution is creating several breaking points in the design process. This course will address the four main challenges for the design community:

■ We consider systems on chips (SoCs) that will be designed and produced in five to ten years from today, with gate lengths in the range 50-100nm. We address the distinguishing features of a design methodology that aims at achieving reliable designs under the limitations of the interconnect technology. Specifically, we consider energy consumption reduction, under guaranteed quality of service (QoS), as a main objective in system design. We show that the unreliability of the physical layer is a potential show-stopper for SoC design. We argue that network technology can be used to provide a framework for designing on-chip interconnect. We visit different layers of a micro-network stack abstraction and show new directions toward designing on-chip communication.

■ We will overview the main on-chip communication architecture schemes. The on-chip communication architecture implements the communication part (e.g. client-server relation, fifo’s, etc..) of the designer’s specification. The architecture consists of software and hardware parts. Software parts include middleware, operating system, device driver and hardware part DMA, bus/network adapter, communication network consisting of dynamic/static routers, and memory. We will focus on networks.

■ We will introduce a design methodology for architectural exploration of networks on chip based on decoupling functionality from architecture, and computation from communication. A simple example of various mapping and refinement options for a single function-to-function token-based communication will be used to practically illustrate the basic concepts. A larger realistic on-chip network will then be used to describe what sort of information can be obtained by various mapping and performance analysis experiments. Although some specific tools will be used to make the explanation more concrete, the methodology is fully tool-independent, and can be implemented on top of several publicly available design frameworks.

■ We will explain the different approaches used to build hardware/software interfaces for networked Systems-on-Chip. This includes building hardware wrappers to interface components with communication networks and software wrappers including OS to isolate software application from architecture.

xlvi

Conference and Exhibition: March 3-7, 2003

Munich, Germany Call for Participation

Scope of the Event

The sixth DATE conference and exhibition is the main European event bringing together design automation researchers, users and vendors, as well as specialists in the design, test and manufacturing of electronic systems and circuits.

Structure of the Event The five day event consists of a conference with plenary invited papers, regular papers, posters, panels, tutorials, and master courses as well as a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services. The organization of a designer forum, user group meetings, fringe meetings, a university booth, hands-on tutorials, vendor presentations and social events offer a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community.

Areas of Interest Within the scope of the conference, the main areas of interest are: Design methodologies, CAD languages, algorithms and tools, Testing of electronic systems, and Designer experiences. Topics of interest include, but are not restricted to:

• System Design Methods • Modelling and Design Languages • Formal Verification • Platform Based design, IP Reuse • HW/SW Co-Design • Embedded System Design • Reconfigurable Computing • Design of Low Power Systems

• Analog and Mixed-Signal Design • Simulation and Emulation • Architectural Level Synthesis • Logic Synthesis • Physical Design and Verification • Interconnect Modelling, EMC • Test and Design for Testability • Testing Cores and Systems

Designers’ Forum

As in previous years, a special track for papers presenting design experiences will be organised. Please watch the conference web site at http://www.date-conference.com/ for special instructions.

Submission of Papers Papers have to be submitted electronically before September 8th, 2002 via the conference web page

http://www.date-conference.com

Conference Secretariat European Conferences

3 Coates Place, Edinburgh, EH3 7AA, UK Tel: +44-131-225-2892 Fax: +44-131-225-2925

Email: sue.menzies@ec.u-net.com

Exhibition Secretariat EDA Exhibitions Ltd.

63/66 Hatton Garden, London, EC1N 8SR, UK Tel: +44-20-7681-1000 Fax: +44-20-7242-5124

Email: exhibitions@edaltd.co.uk

Chairs General Chair: Diederik Verkest, IMEC, Belgium <verkest@imec.be> Program Chair: Norbert Wehn, University of Kaiserslautern, Germany <wehn@eit.uni-kl.de>

Session Index PLENARY – KEYNOTE SESSION 1A HOT TOPIC – How to Choose Semiconductor IP? 1B Formal Verification of Complex Designs 1C Cooling Layout Arrangements 1D Defect Oriented Test 1E Power Analysis and Management in Networks and Processors 2A PANEL – What is the Right IP Business Model? 2B SAT and BDD Techniques 2C Technology and Interconnect Issues in Low Power Design 2D Advanced Mixed Signal Test 2E Collaborative Design – Web-Services, Infrastructure, Applications 2F PANEL – Who Owns the Platform? 3A EMBEDDED TUTORIAL – The Need for Infrastructure IP in SoCs 3B Advances in Logic Synthesis 3C Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design 3D HOT TOPIC – EDA Tools for RF: Myth or Reality? 3E Platform-Based Design and Virtual-Component Reuse 3F2 Analogue Circuit Characterisation and Simulation 4A PANEL – MEDEA+ and ITRS Roadmaps 4B Asynchronous Circuits and Clock Scheduling 4C Analogue and Mixed-Signal Systems 4D BIST Diagnosis and DFT 4E Code and Memory Optimisation in Co-Design 5A HOT TOPIC – Network on a Chip 5B Low Power Architectures and Software 5C Nitty Gritty Details of Layout Design 5D SoC and System Test 5E Modelling and Synthesis of Embedded Systems 6A PANEL – Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-

Performance SoC Designs 6B Reconfigurable Architectures 6C Analogue Modelling, Layout and Sizing 6D Test Resource Partitioning for Embedded Cores 6E System Level Simulation and Modelling 6F HOT TOPIC – Deep Submicron Design and Timing Closure 7A PANEL – Reconfigurable SoC – What Will it Look Like? 7B Layout Aware Logic Synthesis 7C Buffering and Tapering 7D Automatic Design Debug and TPG 7E Object Oriented System Specification and Design 8A HOT TOPIC - UML: Using the Unified Modeling Language for Embedded System Specification 8B Real-Time Embedded Systems 8C Interconnect Modelling 8D On-Line Testing and Fault Tolerance 8E Design Space Evaluation 9B Architectural Level Synthesis 9C Advanced Linear Modelling Techniques 9D Memory Testing and ATPG Issues 9E Embedded Software Performance Analysis and Optimisation 9G TECHNICAL PLENARY – 40 Years of EDA 10A HOT TOPIC – Design Technology for Networked Reconfigurable FPGA Platforms 10B High-Level Synthesis and Asynchronous Pipelines 10C Coupling and Switching Noise Modelling within Integrated Circuits 10D PANEL – Formal Verification Techniques: Industrial Status and Perspectives 10E Power Optimisation for Embedded Processors POSTER SESSIONS

Author Index Design, Automation, and Test in Europe DATE 2002

Ababei, C.____________________________ 1109 Abadir, M. ____________________________ 716 Abadir, M. ____________________________ 944 Abke, J.______________________________ 1085 Abraham, J.____________________________ 730 Acar, E._______________________________ 568 Ackland, B.____________________________ 420 Aghaghiri, Y. _________________________ 1102 Al-Ars, Z. ______________________________ 89 Al-Hashimi, B. _________________________ 514 Al-Hashimi, B. _________________________ 604 Aloul, F. _____________________________ 1082 Alves, G._____________________________ 1126 Amir, A. ______________________________ 804 Amiri, M. _____________________________ 716 Antreich, K. ____________________________ 78 Arrigoni, G. ___________________________ 964 Auvergne, D. __________________________ 316 Avedillo, M. __________________________ 1083 Azevedo, A. ___________________________ 168 Bagherzadeh, N. ________________________ 547 Balakrishnan, V. ________________________ 931 Baldini, A. ____________________________ 499 Banerjee, P.____________________________ 862 Bardsley, A. ___________________________ 330 Barke, E. _____________________________ 1080 Barke, E. _____________________________ 1085 Barke, E. ______________________________ 274 Basten, T. ____________________________ 1021 Bayraktaroglu, I.________________________ 376 Bazargan, K. __________________________ 1109 Beattie, M. ___________________________ 1112 Beattie, M. ____________________________ 628 Becer, M. _____________________________ 456 Becker, D.____________________________ 1044 Beerel, P. ____________________________ 1000 Beerel, P. ____________________________ 1008 Beerel, P. ____________________________ 1098 Belot, D. _____________________________ 1107 Benini, L. _____________________________ 102

Benini, L. _____________________________ 418 Benini, L. _____________________________ 449 Benoit, P. _____________________________ 553 Benso, A. _____________________________ 499 Benso, A. _____________________________ 938 Berkelaar, M. _________________________ 1088 Beroulle, V. __________________________ 1120 Berrojo, L. ____________________________ 847 Bertozzi, D.____________________________ 102 Bertrand, Y. __________________________ 1120 Bhunia, S. ____________________________ 1118 Binkley, D. ___________________________ 1117 Biswas, P. _____________________________ 402 Björklund, D. _________________________ 1136 Blaauw, D. ____________________________ 456 Bolsens, I. _____________________________ 994 Bona, A. _____________________________ 1128 Bontempi, G. __________________________ 971 Bose, S._______________________________ 954 Boyd, S. ______________________________ 110 Bracho, S. _____________________________ 205 Brachtendorf, H. _______________________ 1139 Brandtner, T.__________________________ 1028 Brayton, R. ____________________________ 134 Bricaud, P. _____________________________ 17 Brown, A. ____________________________ 1133 Bruni, D. ______________________________ 449 Bruschi, F. ___________________________ 1135 Buchenrieder, K.________________________ 870 Bystrov, A. ___________________________ 1089 Cabodi, G._____________________________ 150 Cai, L. _______________________________ 1137 Calvillo-Gámez, E. ______________________ 346 Cambon, G.____________________________ 553 Camurati, P. ___________________________ 150 Canavero, F. __________________________ 1044 Carlin, A. _____________________________ 944 Carmona, R. ___________________________ 362 Carro, L. ______________________________ 478 Cathelin, A.___________________________ 1107

Catthoor, F.___________________________ 1072 Catthoor, F.____________________________ 428 Chakrabarty, K. ________________________ 382 Chakrabarty, K. ________________________ 491 Chakrabarty, K. ________________________ 598 Chandra, A.____________________________ 598 Chang, C. ____________________________ 1100 Chang, S. _____________________________ 683 Chang, Y. ______________________________ 69 Chao, K. ______________________________ 690 Chatterjee, A. __________________________ 186 Chelcea, T. ____________________________ 330 Chen, C. _____________________________ 1016 Chen, H. _______________________________ 69 Chen, J. ______________________________ 1119 Chen, J. _______________________________ 486 Chen, L. ______________________________ 176 Chen, L. ______________________________ 812 Chen, S. ______________________________ 486 Chen, Y. ______________________________ 931 Chen, Z. _____________________________ 1044 Cheng, C. _____________________________ 486 Cherubal, S. ___________________________ 186 Cheung, P. ____________________________ 902 Chiamenti, M._________________________ 1135 Choudhary, A. _________________________ 862 Choudhary, V. ________________________ 1125 Chowdhury, V. _________________________ 316 Chu, C. ______________________________ 1101 Cialdella, B. ___________________________ 316 Cibáková, T. ___________________________ 221 Ciesielski, M. __________________________ 285 Clarke, T. _____________________________ 902 Clauss, C. _____________________________ 884 Clayton, N. ____________________________ 227 Clément, F. ___________________________ 1107 Cobb, B. _______________________________ 94 Coelho, C._____________________________ 923 Colavin, O. ____________________________ 540 Cornea, R._____________________________ 168 Corno, F.______________________________ 847 Cortadella, J.____________________________ 44 Cota, E. _______________________________ 478 Cromer, C. ____________________________ 346 Daems, W. ____________________________ 268 Daldoss, L. ____________________________ 192 Dalpasso, M.__________________________ 1122 de Jong, G. ____________________________ 776 De Micheli, G. _________________________ 102 De Micheli, G. ________________________ 1052

De Micheli, G. _________________________ 418 De Roest, D. __________________________ 1113 De Vicente, J. ___________________________ 54 Deconinck, G.__________________________ 428 Dessouky, M. __________________________ 576 Di Carlo, S.____________________________ 938 Di Natale, G.___________________________ 938 Diener, K. _____________________________ 221 Ding, L.______________________________ 1038 Ding, L._______________________________ 708 Diou, C. ______________________________ 553 Doboli, A. ____________________________ 760 Domínguez-Castro, R. ___________________ 362 Donnay, S. ____________________________ 352 Donnay, S. ____________________________ 586 Dörfel, M. ____________________________ 1095 Doucet, F. _____________________________ 736 Drozd, A. ____________________________ 1127 Drozd, J. _____________________________ 1127 Duarte, D. ____________________________ 1108 Dubrova, E.___________________________ 1084 Duchini, L. ____________________________ 964 Dufaza, C._____________________________ 316 Dupont, E._____________________________ 244 Dutt, N. _______________________________ 168 Dutt, N. ________________________________ 36 Dutt, N. _______________________________ 402 Dutt, N. _______________________________ 894 Dworak, J.______________________________ 94 Edwards, D. ___________________________ 330 Edwards, M. ___________________________ 752 Einwich, K.____________________________ 884 Eles, P. _______________________________ 514 Elst, G. ______________________________ 1129 Entrena, L. ____________________________ 847 Ernst, R. ______________________________ 506 Ernst, R. ______________________________ 854 Espejo, S. _____________________________ 362 Essi, Jr, V._____________________________ 132 Fallah, F._____________________________ 1102 Favalli, M. ___________________________ 1122 Favalli, M. ____________________________ 612 Favalli, M. ____________________________ 832 Fazel, K. ______________________________ 255 Feldmann, P.__________________________ 1139 Ferguson, F. ___________________________ 248 Férnandez, M.__________________________ 547 Ferrandi, F. ___________________________ 1135 Ferrandi, F. ____________________________ 744 Ferrari, A. ____________________________ 1094

Ferreira, J.____________________________ 1126 Ferretti, M. ___________________________ 1008 Fesquet, L. ___________________________ 1090 Flottes, M.____________________________ 1124 Francken, K. __________________________ 1110 Fu, W. _______________________________ 1100 Gad, E. _______________________________ 916 Gajski, D. ____________________________ 1137 Galambos, T. __________________________ 804 Galy, J. _______________________________ 553 Gao, Y. _______________________________ 702 García, A. ____________________________ 1103 Gatti, U. ______________________________ 884 Gauthier, L.____________________________ 620 Geishauser, J. _________________________ 1131 Gericota, M. __________________________ 1126 Ghanmi, L. ____________________________ 214 Ghose, K. _____________________________ 124 Ghrab, A. _____________________________ 214 Gielen, G. ____________________________ 1110 Gielen, G. _____________________________ 268 Gielen, G. _____________________________ 279 Gielen, G. _____________________________ 357 Gil, T. ________________________________ 553 Ginés, A.______________________________ 310 Gizopoulos, D. _________________________ 592 Glesner, M. ___________________________ 1103 Glesner, M. ___________________________ 1130 Goessel, M.____________________________ 382 Goffioul, M. ___________________________ 352 Goldberg, E. ___________________________ 134 Goldberg, E. ___________________________ 142 Gonciari, P.____________________________ 604 Gónzález, I.____________________________ 847 Goossens, K.___________________________ 423 Gordin, R. _____________________________ 804 Goren, D. _____________________________ 804 Gören, S.______________________________ 248 Goutis, C. _____________________________ 977 Graeb, H. _____________________________ 581 Graeb, H. ______________________________ 78 Grajcar, M. ___________________________ 1096 Gramatová, E.__________________________ 221 Grass, W. ____________________________ 1096 Green, P. ______________________________ 752 Grimaila, M. ____________________________ 94 Grun, P._______________________________ 894 Guardiani, C. __________________________ 192 Guccione, S. ___________________________ 994 Gupta, R.______________________________ 117

Gupta, R.______________________________ 168 Gupta, R.______________________________ 443 Gupta, R.______________________________ 736 Gupta, R.______________________________ 875 Hajj, I.________________________________ 456 Halambi, A. ___________________________ 402 Haldar, M._____________________________ 862 Hamdoun, M. __________________________ 214 Hartong, W. __________________________ 1080 Hassibi, A. ___________________________ 1111 Hassoun, S. ____________________________ 346 Haubelt, C. ____________________________ 854 Hedrich, L. ___________________________ 1080 Hedrich, L. ____________________________ 274 Heintze, N. ____________________________ 420 Henkel, J. ____________________________ 1059 Henkel, J. _____________________________ 296 Hennig, E._____________________________ 884 Hering, K. ____________________________ 1134 Hermida, R. __________________________ 1097 Hermida, R. ____________________________ 54 Hermida, R. ___________________________ 547 Hermida, R. ___________________________ 909 Hershenson, M.________________________ 1111 Hettiaratchi, S. _________________________ 902 Hieu, T.______________________________ 1104 Hoffmann, C. __________________________ 197 Hofmann, R. __________________________ 1095 Hsiao, M. _____________________________ 949 Hsieh, T. _____________________________ 1100 Hu, G. _______________________________ 1081 Hu, J.________________________________ 1091 Hu, X. ________________________________ 782 Huang, H. _____________________________ 486 Huang, L. _____________________________ 470 Huang, L. _____________________________ 702 Hwang, C._____________________________ 486 Ienne, P. _____________________________ 1138 Indrusiak, L. __________________________ 1130 Irani, S. _______________________________ 117 Irwin, M._____________________________ 1091 Irwin, M._____________________________ 1108 Irwin, M.______________________________ 436 Issenin, I. _____________________________ 168 Ivask, E. ______________________________ 221 Iyengar, V. ____________________________ 491 Jerke, G. ______________________________ 464 Jerraya, A._____________________________ 620 Jiménez-Garrido, F. _____________________ 362 Jin, L. _________________________________ 61

John, W. _____________________________ 1129 Jung, S. _______________________________ 260 Kabulepa, L. __________________________ 1103 Kadayif, I._____________________________ 436 Kaivola, R. _____________________________ 20 Kajitani, Y. _____________________________ 61 Kalla, P. ______________________________ 285 Kandemir, M. _________________________ 1091 Kandemir, M. _________________________ 1092 Kandemir, M. __________________________ 436 Kandemir, M. __________________________ 984 Kang, S. ______________________________ 260 Kania, D._____________________________ 1087 Kapur, R. ____________________________ 1121 Karri, R. ______________________________ 842 Katopis, G. ___________________________ 1044 Kazmierski, T. _________________________ 227 Kebschull, U. _________________________ 1093 Khazaka, R. __________________________ 1114 Khomenko, V. _________________________ 338 Kiliç, Y. _____________________________ 1133 Kim, C. _______________________________ 163 Kim, J. _______________________________ 788 Kim, K. _______________________________ 260 Kim, W. ______________________________ 788 Koegst, M. ___________________________ 1083 Koh, C. _______________________________ 690 Koh, C. _______________________________ 931 Kolcu, I. _____________________________ 1092 Koranne, S. ___________________________ 1125 Köster, M._____________________________ 559 Koutny, M. ___________________________ 1089 Koutny, M. ____________________________ 338 Krahn, L._____________________________ 1129 Kranitis, N. ____________________________ 592 Krauter, B. ____________________________ 628 Kreku, J. _____________________________ 1132 Kritzinger, P. _________________________ 1137 Kruijtzer, W.___________________________ 971 Kucuk, G. _____________________________ 124 Kumar, S. ____________________________ 1117 Kunz, W.______________________________ 677 Kurdahi, F. ____________________________ 547 Kutzschebauch, T. ______________________ 672 Lai, M. _______________________________ 702 Lampe, S. ____________________________ 1139 Lampe, S. _____________________________ 322 Lanchares, J. ____________________________ 54 Latorre, L.____________________________ 1120 Laur, R.______________________________ 1139

Laur, S. _______________________________ 322 Lauwereins, R. _________________________ 428 Lauwers, E.____________________________ 357 Lavagno, L.____________________________ 964 Lechuga, Y. ___________________________ 205 Leclercq, Y. __________________________ 1107 Lee, B. _______________________________ 409 Lee, C. ______________________________ 1100 Lee, C. ______________________________ 1119 Lee, S._________________________________ 94 Lee, T.________________________________ 296 Lekatsas, H. __________________________ 1059 Levant, J. ____________________________ 1115 Leveugle, R. ___________________________ 837 Li, J. _________________________________ 486 Li, P. _________________________________ 634 Lienig, J. ______________________________ 464 Lilius, J. _____________________________ 1136 Lin, H.________________________________ 486 Lin, J. _______________________________ 1119 Lin, J. _________________________________ 69 Lin, T. _______________________________ 1112 Lin, Y._______________________________ 1100 Liu, C.________________________________ 382 Liu, I. ________________________________ 470 Liu, J. ________________________________ 716 Liu, S. ________________________________ 192 Liveris, N._____________________________ 977 Livshitz, B. ____________________________ 804 Lobachev, M. _________________________ 1127 Logothetis, G. __________________________ 795 López, C. _____________________________ 847 Lu, R. ________________________________ 690 Lubaszewski, M.________________________ 478 Luchetta, A. __________________________ 1105 Lv, T. _______________________________ 1059 Macchiarulo, L. ________________________ 158 Macii, A.______________________________ 449 Macii, E. ______________________________ 158 Macii, E. ______________________________ 449 Madrid, N. ____________________________ 310 Maestre, R. ____________________________ 547 Maex, K. _____________________________ 1113 Maio, I. ______________________________ 1044 Majoux, B. ____________________________ 316 Makki, R. ____________________________ 1117 Malcovati, P.___________________________ 884 Maloberti, F. ___________________________ 884 Manetti, S. ___________________________ 1105 Marek-Sadowska, M. ____________________ 176

Marek-Sadowska, M. ____________________ 812 Marinissen, E.__________________________ 491 Martens, E. ___________________________ 1110 Martin, A. _____________________________ 640 Martin, G. ______________________________ 16 Martin, G. _____________________________ 773 Martínez, M. __________________________ 1083 Martínez, M. ___________________________ 205 Marwedel, P.___________________________ 409 Mazumder, P. _________________________ 1038 Mazumder, P. __________________________ 708 Mazumder, P. __________________________ 820 McNamara, P.__________________________ 192 Melville, R.___________________________ 1139 Menard, D. ____________________________ 529 Mendias, J. ___________________________ 1097 Mendias, J. ____________________________ 909 Mercer, M. ___________________________ 1121 Mercer, M. _____________________________ 94 Mesman, B.___________________________ 1021 Metra, C.______________________________ 612 Metra, C.______________________________ 832 Michel, H._____________________________ 396 Miklos, P. _____________________________ 221 Min, S. _______________________________ 788 Miranda, M. __________________________ 1072 Mishra, P. ______________________________ 36 Missaoui, B. ___________________________ 214 Mneimneh, M. ________________________ 1082 Mo, S. ________________________________ 499 Molina, M. ____________________________ 909 Mozuelos, R.___________________________ 205 Mukherjee, A.__________________________ 176 Münch, M. ____________________________ 396 Münzenberger, R. ______________________ 1095 Nakhla, M. ___________________________ 1114 Nakhla, M. ____________________________ 916 Narasimhan, N.__________________________ 20 Nassif, S.______________________________ 568 Nauwelaers, B. ________________________ 1113 Nayak, A. _____________________________ 862 Neumann, I. ___________________________ 677 Nicolaidis, M. __________________________ 240 Nicolaidis, M. __________________________ 244 Nicolau, A. ____________________________ 168 Nicolau, A. _____________________________ 36 Nicolau, A. ____________________________ 402 Nicolau, A. ____________________________ 443 Nicolau, A. ____________________________ 894 Nicolescu, G. __________________________ 620

Nicolici, N. ____________________________ 604 Nitsch, C. ____________________________ 1093 Noessing, G. ___________________________ 884 Nouet, P. _____________________________ 1120 Novikov, Y. ___________________________ 142 Nowick, S. ___________________________ 1000 Nowick, S. ____________________________ 330 Oehmen, J. ____________________________ 274 Olivares, M. __________________________ 1137 Orailoglu, A.__________________________ 1065 Orailoglu, A.___________________________ 376 Orailoglu, A.___________________________ 387 Orailoglu, A.___________________________ 478 Otsuka, M. ____________________________ 736 Ozdag, R. ____________________________ 1000 Padmanaban, S. _________________________ 84 Palkovic, M. __________________________ 1072 Panda, R.______________________________ 456 Pandey, A. ____________________________ 368 Pandini, D. ____________________________ 664 Panigrahi, A.__________________________ 1106 Paschalis, A. ___________________________ 592 Paško, R.______________________________ 302 Passerone, C. __________________________ 964 Pastor, E._______________________________ 44 Patel, J. _______________________________ 368 Pateras, S. _____________________________ 242 Paul, J. _______________________________ 522 Pedram, M. ___________________________ 1086 Pedram, M. ___________________________ 1102 Peeters, A._____________________________ 423 Peña, M. _______________________________ 44 Peñalba, O. ___________________________ 1097 Pénzes, P. _____________________________ 640 Peralías, E. ____________________________ 310 Petrov, P. ____________________________ 1065 Peymandoust, A._______________________ 1052 Peyran, O. ____________________________ 1099 Phillips, I. ______________________________ 14 Phillips, J. _____________________________ 923 Piccirilli, M. __________________________ 1105 Pilarski, S.____________________________ 1081 Pileggi, L. ____________________________ 1112 Pileggi, L. _____________________________ 568 Pileggi, L. _____________________________ 628 Pileggi, L. _____________________________ 634 Pileggi, L. _____________________________ 664 Pomeranz, I. __________________________ 1116 Pomeranz, I. __________________________ 1123 Pomeranz, I. ___________________________ 722

Poncino, M. ___________________________ 158 Ponomarev, D. _________________________ 124 Popp, R. ______________________________ 274 Pouget, J. ____________________________ 1124 Pozzi, L. _____________________________ 1138 Prasad, M._____________________________ 134 Prinetto, P. ____________________________ 499 Prinetto, P. ____________________________ 938 Pronath, M. ____________________________ 581 Pronath, M. _____________________________ 78 Pyttel, A.______________________________ 870 Qu, Y. _______________________________ 1132 Quan, G. ______________________________ 782 Quartana, J.___________________________ 1090 Quer, S._______________________________ 150 Quintana, J.___________________________ 1083 Rahajandraibe, W. ______________________ 316 Raik, J. _______________________________ 221 Rajski, J. _____________________________ 1116 Ramdani, M. __________________________ 1115 Ratford, V. _____________________________ 15 Reda, S._______________________________ 387 Reddy, S. ____________________________ 1116 Reddy, S. _____________________________ 722 Reese, R.______________________________ 255 Reis, R. ______________________________ 1130 Renaudin, M. _________________________ 1090 Rendine, M. ___________________________ 744 Rettberg, A. ___________________________ 232 Rezvani, P. ___________________________ 1086 Riccò, B. ______________________________ 832 Richter, K. ____________________________ 506 Richter, K. ____________________________ 854 Rigaud, J. ____________________________ 1090 Rizzo, D.______________________________ 540 Rodríguez-Vázquez, A. __________________ 362 Rohr, P._______________________________ 244 Ross, J. ______________________________ 1133 Rouzeyre, B. __________________________ 1124 Rouzeyre, B. ___________________________ 285 Roy, K. ______________________________ 1118 Roy, K. _______________________________ 163 Roy, K. _______________________________ 931 Rueda, A. _____________________________ 310 Rugen-Herzig, I. ________________________ 884 Rülke, S. _____________________________ 1083 Saias, D. _____________________________ 1107 Sakallah, K. __________________________ 1082 Sakanushi, K. ___________________________ 61 Sami, M. _____________________________ 1128

Sánchez-Élez, M. _______________________ 547 Sansen, W. ____________________________ 268 Sansen, W. ____________________________ 279 Sarrafzadeh, M. _______________________ 1016 Sassatelli, G. ___________________________ 553 Saucier, G. ____________________________ 214 Sauer, A. _____________________________ 1129 Savoiu, N. _____________________________ 875 Saxena, S. _____________________________ 192 Sayed, D. _____________________________ 576 Schaumont, P.__________________________ 302 Schenkel, F. ___________________________ 581 Schiano, L. ____________________________ 832 Schmitz, M. ___________________________ 514 Schneider, A. __________________________ 221 Schneider, K. __________________________ 795 Schwarz, P. ____________________________ 884 Schwencker, R._________________________ 581 Sciuto, D. ____________________________ 1128 Sciuto, D. ____________________________ 1135 Sciuto, D. _____________________________ 744 Sedlmeier, A. __________________________ 870 Seepold, R. ____________________________ 310 Selic, B. ______________________________ 770 Sentieys, O.____________________________ 529 Sham, C. ______________________________ 696 Sheehan, B.____________________________ 826 Sherman, A. ___________________________ 804 Shrivastava, A. _________________________ 402 Shukla, S. _____________________________ 117 Shukla, S. _____________________________ 736 Shukla, S. _____________________________ 875 Silva, M. _____________________________ 1126 Silvano, C. ___________________________ 1128 Silveira, L. ____________________________ 923 Simmons, M. _________________________ 1131 Simunic, T. ___________________________ 1052 Simunic, T. ____________________________ 110 Singh, M. ____________________________ 1000 Sivasubramaniam, A. ____________________ 436 Skiba, K. ______________________________ 214 Skliarova, I. __________________________ 1094 Slomka, F.____________________________ 1095 Smirnov, A. ____________________________ 44 Soininen, J. ___________________________ 1132 Sommer, R.____________________________ 884 Sonza Reorda, M. _______________________ 847 Soudris, D. ____________________________ 977 Squillero, G. ___________________________ 847 Stan, M. _____________________________ 1106

Steinke, S._____________________________ 409 Steyaert, M. ___________________________ 357 Stievano, I. ___________________________ 1044 Stöhr, S. _____________________________ 1131 Stok, L. _______________________________ 672 Strojwas, A. ___________________________ 664 Stucchi, M. ___________________________ 1113 Su, C. ________________________________ 486 Sulimma, K. ___________________________ 677 Süße, H. _____________________________ 1083 Taddei, A. _____________________________ 499 Tang, W. ______________________________ 443 Tang, X. ______________________________ 470 Teich, J. ______________________________ 559 Teich, J. ______________________________ 854 Thomas, D. ____________________________ 522 Thornton, M.___________________________ 255 Thronicke, W.__________________________ 232 Tien, T. _______________________________ 683 Tomiyama, H.___________________________ 36 Torres, L. _____________________________ 553 Tragoudas, S. ___________________________ 84 Traver, C. _____________________________ 255 Tsai, T. _______________________________ 683 Tugsinavisut, S. _______________________ 1098 Ubar, R. ______________________________ 221 Uyttenhove, K. _________________________ 357 Van Achteren, T. _______________________ 428 van de Goor, A. _________________________ 89 van de Goor, A. ________________________ 944 van Eijk, K.___________________________ 1088 van Ginneken, L. _______________________ 677 van Meerbergen, J. ______________________ 423 Van Thielen, B.________________________ 1033 Vanassche, P. __________________________ 279 Vandenberghe, S. ______________________ 1113 Vandenbosch, G._______________________ 1033 Vandenbussche, J._______________________ 357 Vandersteen, G. ________________________ 352 Vandersteen, G. ________________________ 586 Vedula, V._____________________________ 730 Veidenbaum, A. ________________________ 168 Velev, M. ______________________________ 28 Vemuri, R. ____________________________ 760 Veneris, A. ____________________________ 716 Verbeyst, F. ___________________________ 586 Verkest, D. ____________________________ 994 Vernalde, S. ___________________________ 302 Vijaykrishnan, N. ______________________ 1091

Vijaykrishnan, N. ______________________ 1108 Vijaykrishnan, N. _______________________ 436 Vogels, M. ___________________________ 1110 Voorakaranam, R._______________________ 186 Vuletić, M. ___________________________ 1138 Wagner, I. _____________________________ 804 Wambacq, P.___________________________ 352 Wambacq, P.___________________________ 586 Wang, K.______________________________ 176 Watanabe, Y. __________________________ 964 Wehmeyer, L. __________________________ 409 Wehn, N.______________________________ 396 Weigel, R.____________________________ 1028 Wielage, P. ____________________________ 423 Williams, J.____________________________ 420 Williams, T. __________________________ 1121 Wilson, P. ____________________________ 1133 Wolf, W. _____________________________ 1059 Wolf, W. ______________________________ 296 Wong, D. _____________________________ 470 Wong, D. _____________________________ 702 Wong, W. _____________________________ 696 Worm, A. _____________________________ 396 Wu, C.________________________________ 486 Wu, K. _______________________________ 842 Xiang, H. _____________________________ 470 Xiang, W. _____________________________ 192 Xu, Q. ________________________________ 820 Yakovlev, A.__________________________ 1089 Yakovlev, A.___________________________ 338 Ymeri, H. ____________________________ 1113 Yoo, S. _______________________________ 620 Young, F. ____________________________ 1101 Young, F. _____________________________ 696 Zaccaria, V. __________________________ 1128 Zafalon, R. ___________________________ 1128 Zanella, S._____________________________ 192 Zelikson, M. ___________________________ 804 Zeng, Z. ______________________________ 285 Zervas, N. _____________________________ 977 Zhao, Q. _____________________________ 1021 Zheng, H. _____________________________ 628 Zhong, G. _____________________________ 690 Zhuang, C. _____________________________ 61 Zhuang, W. ___________________________ 1099 Zolotov, V. ____________________________ 456 Zorian, Y. ____________________________ 1123 Zorian, Y. _____________________________ 592 Zwolinski, M. _________________________ 1133