System-Level Design of a Reconfigurable CT SD Modulatorfor Multi-Standard Wireless Applications

Raphael A. C. Vieraraphael@ieee.org

Cesar Augusto Priorcesar.prior@ieee.org

Jorge de La Cruzjorgevdelacruz@pads.ufrj.br

João Baptista Martinsbatista@inf.ufsm.br

Microelectronics Group (Gmicro)Federal University of Santa Maria (UFSM)

Santa Maria, RS. 97105-900 - Centro de Tecnologia

ABSTRACTThis paper reports the system-level design of a reconfigura-ble continuous-time sigma-delta modulator that is capableto perform the analog-to-digital conversion for GSM, LTE5and WLAN wireless standards. The modulator architectureconsists of a third-order loop filter using feed-forward sum-mation topology and a 4-bit internal quantizer. The modu-lator coefficients were directly synthesized in the continuous-time domain which provides a more efficient modulator interms of noise shaping, efficiently placing the zeros and polesof the noise transfer function. The reconfiguration stra-tegy is performed at the circuit-level by using digital signalsthat selects the appropriate transconductances, capacitorsand the sampling frequency for each standard. SIMULINKbuilding blocks that model the non-idealities associated withthe modulator were employed in the system-level simula-tions. The results show that the modulator achieves asignal-to-noise plus distortion ratio of 96/83/81 dB within a0.2/5/10 MHz signal bandwidth.

Categories and Subject DescriptorsB.7.0 [Integrated Circuits]: General

General TermsPerformance, Design, Simulation

KeywordsCT sigma-delta modulator, system-level design, A/D con-version, high order noise-shaping

1. INTRODUCTIONThe majority of Σ∆ modulators reported in the literature

for audio-band applications have been implemented using

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Discrete Time (DT) techniques, however, the increasing de-mand for high data rates restrict the modulator performancebecause of the prohibitive unity-gain frequency requirementsof the operational amplifiers in Switched-Capacitor (SC) in-tegrators. Alternatively, Continuous Time (CT) Σ∆ modu-lators present fastest operation and low power consumptionbut suffer of high sensitivity to some circuit errors, parti-cularly clock jitter and time constant variations. In prac-tice, although these problems have been partially solved ina number of mono-standard Integrated Circuits (ICs) [1],they constitute a critical factor in multi-standard applica-tions.

Several researchers have proposed multi-standard Σ∆ADCs for broadband applications [2], most of them makinguse of topologies first synthesized in the discrete timedomain and then converting to the continuous time domain.A disadvantage of this technique is the increasingly sensitiveto circuit imperfections, especially at low oversamplingratios [3]. With this aim, this work presents a system-leveldesign of a multi-standard Σ∆ modulator that maintainsthe architecture unchanged for multiple bandwidths. Themodulator resorts to circuit-level reconfiguration strategiesin order to adapt its performance to the requirements of theproposed standards as described in Section IV.

Table 1 summarizes the targeted signal-to-noise plusdistortion ratio (SNDR) and bandwidth (BW) requirementsfor each standard implemented [4]. An up-to-date survey ofΣ∆ architectures, emphasizing on their application to thenext generation of wireless telecom systems is avaiable in[5].

Table 1: Specifications for different standardsWireless standard Channel bandwidth Peak SNDR

GSM 0.2 MHz 86 dBLTE5 5 MHz 68 dB

WLAN 10 MHz 68 dB

2. MODULATOR ARCHITECTURE

2.0.1 System-level parametersThe architecture of the Σ∆ modulator was defined by

setting appropriate values for the integrator loop order (L),the oversampling ratio (M) and the number of bits (B) that

permit to achieve the specifications of each standard. Theseparameters defined the dynamic range of the modulatorwhich is given by

DR =3

2

2L+ 1

π2LM2L+1(2B − 1)2 (1)

The WLAN receiver manages wideband signals whichimplies that the M value cannot be high since the maximumclock frequency is limited by the process technology.Thus, in order to maximize the signal bandwidth withoutincreasing the sampling frequency, the use of high ordertopology as well multibit internal quantizer are generallyused to reduce the oversampling ratio [3]. Figure 1 showsthe dynamic range of a multi-bit (B=4) modulator fordifferent values of L and M. Otherwise, for low bandwidthapplications, such as GSM, oversampling ratio can be madehigher, due to the smaller signal bandwidth.

1 2 4 8 16 32 64 1280

20

40

60

80

100

120

Oversampling ratio, M

Dynam

ic r

ange,

DR

(dB

)

L=1

L=2

L=3L=4L=5

Figure 1: Ideal dynamic range versus the oversam-pling ratio for different noise-shaping orders. Amulti-bit quantizer (B = 4) is assumed.

It is worth noting that the complexity of the modulatorincreases as well as the integrator order and the numberof bits of the quantizer. Also, higher sampling frequenciesrequires additional power consumption and larger area.Considering the above limitations, a third-order loop filterwith a 4-bit internal quantizer is proposed.

2.0.2 Loop topologyFor Σ∆ modulators two architectures are commonly

used, feedback and feed-forward. Feedback topologies areless suitable for low-voltage, deep submicron technologyimplementation due to the large signal swing at the outputof the first stage integrator opamp [6]. Whereas, the mainadvantages of feed-forward architecture is that the cascadedintegrators handle only a part of the input signal, therefore,the integrators can have a relaxed dynamic range andscaling requirements. The single-loop high-order multibitΣ∆ modulators offer an improved stability, allowing a moreaggressive noise shaping which results in an additionalaccuracy improvement. The main drawback of this approachis the high linearity required of the internal D/A converter

in the feedback path of the modulator. To improve theaccuracy of the internal D/A converter a large number ofstrategies have been reported, however, one of the most usedis the dynamic element matching (DEM) technique [5].

An extra feedback branch between the output and theinput of the quantizer and two D-latches are employed inorder to compensate for the effect of excess loop delay(ELD). Non Return-to-Zero (NRZ) DAC is used to minimizethe effect of jitter and DEM technique is also included toreduce the impact of DAC mismatch.

Finally, a local feedback loop is placed between the thirdand first integrator outputs in order to move the NTFzeros away from DC and optimally spread them over thesignal band to minimize the In-Band Noise (IBN), therefore,increasing the SNDR [7].

Figure 2 illustrates the architecture of the proposedmodulator.

1sTs___

Ki0

1sTs___Ki1

1sTs___Ki2 Ki3

Kf1

Kf2

Kf3

+4-bitsKfb

fs

out

Ke

DA

C

Latc

h

-sTdeLatc

hDAC

x(t)

γ

GSM

LTE5 - WLANst

st

st

Figure 2: Block Diagram of the CT Σ∆ modulatoremploying a third-order loop filter with multibitquantizer.

3. TOPOLOGICAL SYNTHESISCT Σ∆ modulator architectures are usually synthesized

using the invariant-impulse transformation (IIT) by firstsynthesizing a Σ∆ modulator with the same specificationsin the DT domain and then applying a DT to CTtransformation [8]. It results in a functional CT modulatorthat present several disadvantages such as: larger number ofanalog components, larger area, higher power consumption,and higher sensitivity to technology parameter variations.In this paper a direct synthesis method was used, meaninga more efficient modulator in terms of noise shaping,efficiently placing the zeros and poles of the noise transferfunction. The following systematic procedure was used forthe modulator synthesis:

First, the loop filter is obtained from a rational S-domainprototype

NTF (s) =A(s)

B(s)=

1

1 + kq × LF (s)(2)

For simplicity, kq can be arbitrarily set to unity [9].Therefore, the loop-filter transfer function can be derived

as follow:

LF (s) =B(s)−A(s)

A(s)(3)

Subsequently, the NTF prototype is designed with asuitable synthesis tool, usually using a Butterworth or aninverse-Chebyshev high pass function. Then, the poles ofthe transfer function are optimally placed in the signalbandwidth according to the pole/zero placement reportedin [7]. Table 2 gives the solutions and the signal-to-noiseratio (SNR) improvement these values offer when comparedto modulators using NTF’s with coincident zeros.

Table 2: Zero placement for minimum In-BandNoise

L zero locations, normalized to ωB SNR improvement1 0 0 dB2 ± 1√

33.5 dB

3 0, ± 1√3

8 dB

The loop-filter transfer functions for GSM/LTE5/WLANmodes for the modified architecture with additional feedbackDAC are shown in (4), (5) and (6) respectively.

LF(GSM)(s) =0.6703s2 + 0.2442s+ 0.04398

s3(4)

LF(LT E5)(s) =0.6692s2 + 0.2275s+ 0.0457

s3 + 0.02313s(5)

LF(W LAN)(s) =0.6683s2 + 0.2146s+ 0.04707

s3 + 0.04112s(6)

Finally, the modulator coefficients are obtained from asimulation-based procedure that optimizes the modulatorperformance in terms of dynamic range and stability asdescribed in [10] and illustrated in Figure 3. To preventsystem instability due to a circuit nonlinearity, loop filtercoefficients must be confined to the area of stable operation(darker area).

The resulting set of coefficients for the three standards isgiven in Table 3

Table 3: Coefficients of the triple-mode Σ∆ modu-lator

Coefficients GSM LTE5 WLANKi0 6.6 5.6 4.5Kfb 11 4.8 3.8Ki1 6 5 4Ki2 5 3 5Ki3 3 2 1Kf1 2.3 5 2kf2 4 4 4kf3 4 2 2γ - 1/3 1/5

4. RECONFIGURATION STRATEGYThe modulator presented in this paper provides an ar-

chitecture capable of reconfiguration with minimum adjust-ment of parameters when switching from one standard to

00.2

0.40.6

0.81

1.21.4

x 10−3

0

0.5

1

1.5

x 10−3

10

20

30

40

50

60

70

80

SN

DR

(d

B)

Ki0Ki1

Figure 3: Three-dimensional plot of SNDR asfunction of the coefficients ki0 and ki1.

another. The reconfiguration strategies are performed atthe circuit level with two digital signals that select the ca-pacitor and transconductor size for the standard in question(modulator coefficients implemented as transconductances),as well the division of the clock frequency (fs). Since thecenter frequency of the resonator is at ω0 = gm/C, the re-sonator feedback γ in Figure 2 is switched off (switch st)for GSM since there is a high oversampling ratio and wouldrequire proibitive values of C and gm.

5. BLOCK NON-IDEALITIESBehavioral simulations have been used to investigate the

overall circuit non-idealities effects that comprise mainlyCT Σ∆ modulators and to establish the analog blocksrequirements. The simulations were performed using aSimulink environment [11] with building blocks which takesinto account several non-idealities. The basic building blockswith its non-idealities are summarized in Table 4. A detaileddescription of the described non-idealities can be found in[12].

Table 4: Non-idealities associated to basic buildingblocks in a CT Σ∆M.

Building Block Associated non-idealitiesClock Jitter.

Comparator Offset, Hysteresis.Quantizers and Integral non-linearity, gain error,

DACs offset, jitter noise, delay time.Integrator and Finite and non-linear gain,

Resonators parasitic capacitors,high and low frequency poles,

thermal noise, offset,output range and linear input range.

The effect of the finite DC gain of the first integratorversus SNDR for the standards in question is illustratedin Figure 4. It can be observed that a finite DC gain

of aproximatelly 55 dB is enough to meet the modulatorspecifications (feed-forward architecture tolerates a smallerdc gain, without drastically performance degradation),however, in order to provide some margin for degradationdue to other non-idealities, a minimum gain of 70 dB isselected.

20 30 40 50 60 70 800

10

20

30

40

50

60

70

80

90

Gain (dB)

SN

DR

(d

B)

BW=10MHz

BW=0.2MHz

BW=5MHz

Figure 4: Effect of finite DC gain on the firstintegrator.

Another nonideality that can affect drastically the modu-lator performance is the excess loop delay. Figure 5 illus-trates the effect of ELD on the modulator performance forthe three standards. The quantizer delay is set to Ts/5. Thisdelay is compensated by an additional feedback path (Ke inFigure 2), hence, placement of NTF poles is not limited bythe negative effect of quantizer delay on loop stability [13].

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10−9

0

10

20

30

40

50

60

70

80

90

Seconds (s)

SN

DR

(d

B)

BW=0.2MHz

BW=5MHz

BW=10MHz

Figure 5: Effect of Excess Loop Delay on themodulator performance.

The main non-idealities included to test the modulatorperformance are summarized in Table 5.

Table 5: Non-idealities SummaryModulator non-idealities Value

Excess loop delay Ts/5First integrator DC gain 70 dB

First integrator opamp GBW fs*2.5Clock jitter 0.1% Ts

DAC mismatch error 0.15%DAC offset error 0.5%DAC gain error 0.15%

Integral non-linearity 0.15 LSB

5.1 Effect of MismatchesGmC circuits achieve the required coefficients by proper

component ratios. Inaccurate coefficients cause a shift ofzeros and poles position of the transfer function. A shiftin zeros of the noise transfer function modifies the noiseshaping, thus, degrading the modulator performance. Theeffect of circuit tolerances and component mismatch hasbeen taken into account in addition to the block non-idealities when designing the modulator. Cicuit tolerancescan be controlled by using tuning circuits in order tomaintain the GmC time constant, however there will stillexist mismatch error. To evaluate the impact of mismatcherror on the modulator performance, a Montecarlo analysiswith 200 samples was performed using a simulation toolprovided by [11]. To illustrate the analysis (consideringthe modulator with 5 MHz bandwidth), Figure 6 showsthe simulation of the modulator performance for a standarddeviation of 2% for the transconductances and 1% for thecapacitances. Note that the SNDR is above the specificationeven for the considered worst-case mismatch.

0.10.25

0.40.55

0.70.85

1

2

1.75

1.5

1.25

1

0.7579

79.5

80

80.5

81

81.5

82

82.5

C (%)Gm (%)

SN

DR

(dB

)

Figure 6: Effect of GmC variations over SNDR

Figure 7 shows the statistical histogram of 200-run MonteCarlo analysis for the transconductors with a standarddeviation of 10%, meanwhile Figure 8 shows a similaranalysis for the capacitors with the same standard deviation.Note that the SNDR is also above the specification for thisanalysis.

79.5 80 80.5 81 81.5 82 82.5 830

2

4

6

8

10

12

14

16

18

20N

um

ber

of

Even

ts

SNDR (dB)

Figure 7: Effect of transconductors variations overSNDR

76 77 78 79 80 81 82 830

5

10

15

20

25

30

35

40

45

Num

ber

of

Even

ts

SNDR (dB)

Figure 8: Effect of capacitor variations over SNDR

6. RESULTSThe output spectra for the three modes of operation

(GSM, LTE5 and WLAN) are shown in Figure 9, 10 and11 when nonideal effects are taken into account. Simulationwas performed in time-domain and the outputs spectrawere computed using 216 points FFT. The input signalsare at fin= BW/3 so that at least the second and thirdharmonics lie within the signal band. Note that shapedquantization noise presents a notch inside the signal bandwhich minimizes the in-band noise for LTE5 and WLANstandards.

Figure 12 presents the simulated SNDR versus inputsignal amplitude, for GSM/LTE5/WLAN standards.

The overall performance of the proposed sigma-deltamodulator is summarized in Table 6. The peak SNDRachieved by the modulator for the three standards isintentionally higher than the specification to account theperformance degradation by the action of other nonidealitiesas layout, circuit element tolerances, component mismatch,etc.

104

105

106

107

−220

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

Ma

gn

itu

de

(d

B)

Frequency (Hz)

Figure 9: Output spectra of the synthesized modu-lator with 0.2 MHz bandwidth.

104

105

106

107

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

Ma

gn

itu

de

(d

B)

Frequency (Hz)

Figure 10: Output spectra of the synthesizedmodulator with 5 MHz bandwidth.

Table 6: Performance SummaryWireless Standard Bandwidth Peak SNDR OSR

GSM 0.2 MHz 96 dB 128LTE5 5 MHz 83 dB 16

WLAN 10 MHz 81 dB 12

7. CONCLUSIONSA reconfigurable CT Σ∆ modulator with third-order loop

filter realized using Gm-C integrators and a cascade of reso-nator in feed-forward summation is presented. To reduce thenonlinearity effects of the analog circuits, a 4-bit quantizerwas employed. The system-level simulations of the modula-tor using simulink building blocks were performed to assurethat the non-idealities of the critical blocks are not affect-ing the modulator response. Based on these simulationsand the analysis of the modulator, the requeriments of theblocks at circuit-level were specified. The blocks were de-

104

105

106

107

−180

−160

−140

−120

−100

−80

−60

−40

−20

0M

ag

nitu

de

(d

B)

Frequency (Hz)

Figure 11: Output spectra of the synthesizedmodulator with 10 MHz bandwidth.

10−5

10−4

10−3

10−2

10−1

100

10

20

30

40

50

60

70

80

90

100

Input Signal Amplitude (dbV)

SN

DR

(d

B)

BW=5MHz

BW=10MHz

BW=0.2MHz

Figure 12: SNDR versus input signal amplitude. fin

at BW/3.

signed to reach the specifications even considering process(and mismatch), voltage and temperature variations [14].With minimum adjustment of parameters, the modulator isalso a potential candidate for extending reconfigurable sig-nal bandwidth range besides the GSM / LTE5 / WLANstandards. The simulation results indicate a peak SNDR of96/83/81 dB within a 0.2/5/10 MHz signal bandwidth.

8. ACKNOWLEDGMENTSThe authors would like to thank Financiadora de Estu-

dos e Projetos (FINEP), Fundacao de Apoio a Tecnologia eCiencia (FATEC/UFSM), Fundacao de Amparo a Pesquisado Estado do Rio Grande do Sul (FAPERGS) and Con-selho Nacional de Desenvolvimento Cientıfico e Tecnologico(CNPq) for supporting this project. We also thank the In-stituto de Microelectronica de Sevilla IMSE-CNM (CSIC /Universidad de Sevilla) for providing and supporting the de-sign environment.

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