ACFH-3548T Data Sheet

Data Sheet

ACFH-3548TAutomotive Gate Drive Optocoupler with Flyback DC-DC Controller, Adaptive Blanking, Advance Short Circuit Protection and Isolated Analog Feedback for Temperature Sensing

Description

The Broadcom® automotive gate driver optocoupler features integrated flyback controller for an isolated DC-DC converter with adjustable output voltage, adaptive blanking for precise kick-in of protection mechanism to enable fast protection, and patented adaptive soft-shutdown using IGBT desat/emitter current sensing. Temperature information from diodes or a thermistor is provided by an isolated analog feedback channel to the microcontroller on the low voltage side. This information is coupled with a simple compensation circuit that allows for accurate emitter sensing across operation temperature.

This full-feature optocoupler comes in a compact, surface-mountable SO-32 package with 0.8-mm pitch for space-savings and is suitable for HEV and EV applications. Broadcom R2Coupler™ isolation products provide reinforced insulation and reliability that deliver safe signal isolation critical in automotive and high-temperature industrial applications.

Figure 1: ACFH-3548T Functional Diagram

Features

Qualified to AEC-Q100 Grade 1 test guidelines

Automotive temperature range: –40°C to +125°C

Integrated flyback controller for isolated DC-DC converter for power supply control and diagnostic

– Adjustable regulated output supply voltage: 14.5V to 17.5V

– Programmable negative supply

– Supply output over load protection

– Supply output short-circuit protection

– External primary switch good for Load Dump test conditions and high power scaling

Integrated isolated analog feedback for IGBT temperature sensing

Integrated fail-safe IGBT protection

– IGBT emitter and desaturation sensing

– Temperature compensation for emitter sensing

– Adaptive shutdown during fault detection

– Short-circuit fault feedback

– Under Voltage Lock-out (UVLO) protection with feedback

High noise immunity

– Common-mode Rejection (CMR): 50 kV/µs at VCM = 1500V

– Miller current clamping

– Direct LED input with low input impedance and low noise sensitivity

– Support negative gate bias

SO-32 package with 8-mm creepage and clearance

Regulatory approvals: UL1577, CAN/CSA, IEC 60747-5-5

Applications

IGBT/SiC MOSFET gate driver for traction inverter, charger, and HVAC.

VEE2

LED2+ VCC2VE

VCC1

COMP

CA

/FAULT

/UVLO

AN

OSC

RS

Output Driver

PGD

VO

SSD Control

ControlLogic

Turn-on Control

MC

SSD

HSD Control

Miller Control

CS

VEE2

OT

TOK

FeedbackDecoder

TINTREF

TOUT

P_GND

VADJ

DSTVEE1

ISEN TemperatureCompensation

TB

VDST_TH

VUVLO

VTB_TH

VMC_TH

VISEN_TH

Broadcom ACFH-3548T-DS103July 14, 2021

ACFH-3548T Data Sheet Automotive Gate Drive Optocoupler with Flyback DC-DC Controller, Adaptive Blanking,

Advance Short Circuit Protection and Isolated Analog Feedback for Temperature Sensing

Ordering Information

To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry.

Example 1:

ACFH-3548T-500E is to order product of SO-32 surface mount package in tape and reel packaging with IEC/EN/DIN EN 60747-5-5 safety approval in RoHS compliant.

Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information.

Part Number Option (RoHS Compliant) Package Surface Mount Tape and ReelIEC/EN/DIN EN

60747-5-5 Quantity

ACFH-3548T -000E SO-32 X X 35 per tube

ACFH-3548T -500E X X X 850 per reel

Broadcom ACFH-3548T-DS1032



Package Outline Drawing

Figure 2: Package Outline Drawing (32-Lead Surface Mount)

Recommended Pb-Free IR Profile

Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest version).

NOTE: Non-halide flux should be used.

Product Overview Description

The ACFH-3548T (shown in Figure 1) is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit. It features flyback controller for isolated DC-DC converter, Miller current clamping, integrated temperature sensor and feedback, IGBT desaturation and emitter current sensing, under voltage lock-out protection and feedback in an SO-32 package. It also features an integrated temperature compensation circuit for emitter sensing short-circuit protection and adaptive turn-off during fault conditions. Direct LED input allows flexible logic configuration and differential current mode driving with low input impedance, greatly increasing noise immunity.




Package Pin Out

Figure 3: ACFH-3548T Pin Configuration

Pin Description

Table 1: Pin Description

Pin Number Pin Name Description

1 PGD Primary gate driver for external MOSFET

2 P_GND Power ground reference for primary gate drive. Connect to the VEE1 plane through vias locally.

3 ISEN Current sense for flyback controller

4 VEE1 Input ground

5 VCC1 Input power supply

6 VADJ Voltage to adjust VCC2

7 COMP Compensation network for flyback controller

8 /UVLO Under-voltage feedback for VCC1; under-voltage lock out feedback for VCC2

9 /FAULT IGBT short-circuit or over-current fault feedback triggered by the DST or CS pin

10 TOK TOUT validity indicator

11 NC No connection

12 TOUT Analog output for temperature sense

13 AN Input LED anode

14 CA Input LED cathode

15 DNC Do not connect (internally connected to VEE1 lead frame)

16 DNC Do not connect (internally connected to VEE1 lead frame)

17 VEE2 Output negative power supply

18 MC Miller current clamping output

19 TB Blanking time control

27

26

25

24

23

22

21

20

LED2+

NC

VEE2

VCC2

CS

VE

DST4

5

6

7

8

9

10

11

PGDP_GND

/UVLO

/FAULT

TOUT

VCC1

VADJ

VEE1

19

18

17

VO12

13

14 CA

TOK

MC15 DNC

VEE2

30

29

1

2

28

3

SSD

TIN

NC

TB

TREF

ISEN

COMP

NC

AN

16 DNC

32

31

VEE2




Organization Approval

The ACFH-3548T is approved by the following organizations.

20 SSD Soft shutdown output

21 VO Output driver for IGBT/MOSFET gate

22 VCC2 Output positive power supply

23 VE IGBT emitter/MOSFET source reference

24 TIN Temperature sensing input

25 CS Current sense input

26 NC No connection

27 TREF Reference voltage input for temperature compensation

28 NC No connection

29 DST Desaturation over-current sensing

30 LED2+ Do not connect, for testing only



UL Approved under UL 1577, component recognition program up to VISO = 5000 VRMS

CAN/CSA Approved under CAN/CSA-C22.2 No.62368-1

IEC/EN/DIN EN 60747-5-5 Approved under: IEC 60747-5-5, EN 60747-5-5, DIN EN 60747-5-5

Table 1: Pin Description (Continued)

Pin Number Pin Name Description




IEC/EN/DIN EN60747-5-5 Insulation Characteristics1

Insulation and Safety-Related Specifications

1. Isolation characteristics are guaranteed only within the safety maximum ratings that must be ensured by the protective circuits in the application. The surface mount classification is class A in accordance with CECCOO802.

Description Symbol Characteristic Units

Insulation Classification per DIN VDE 0110/1.89, Table 1

For rated mains voltage ≤ 150Vrms I-IV



For rated mains voltage ≤ 1000Vrms I - III

Climatic Classification 40/125/21

Pollution Degree (DIN VDE 0110/1.89) 2

Maximum Working Insulation Voltage VIORM 1230 VPEAK

Input to Output Test Voltage, Method ba

VIORM × 1.875 = VPR, 100% production test with tm = 1s, partial discharge < 5 pC

a. Refer to the optocoupler section of the Isolation and Control Components Designer's Catalog, under Product Safety Regulation section IEC/EN/DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.

VPR 2306 VPEAK

Input to Output Test Voltage, Method aa

VIORM × 1.6 = VPR, type and sample test, tm = 10s, partial discharge < 5 pC

VPR 1968 VPEAK

Highest Allowable Overvoltage (transient overvoltage tini = 60s) VIOTM 8000 VPEAK

Safety-limiting values – maximum values allowed in the event of a failure

Case Temperature TS 175 °C

Input Current IS,INPUT 350 mA

Output Power PS,OUTPUT 1200 mW

Insulation Resistance at TS, VIO = 500V RS > 109 Ω

Parameter Symbol Value Units Conditions

Minimum External Air Gap (Clearance)

L(101) 8.5 mm Measured from input terminals to output terminals, shortest distance through air.

Minimum External Tracking (Creepage)

L(102) 8.5 mm Measured from input terminals to output terminals, shortest distance path along body.

Minimum Internal Plastic Gap (Internal Clearance)

0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector.

Tracking Resistance (Comparative Tracking Index)

CTI >175 V DIN IEC 112/VDE 0303 Part 1.

Isolation Group IIIa Material Group (DIN VDE 0110).




ESD Ratings

Absolute Maximum Ratings

Unless otherwise specified, all voltages at input IC reference to VEE1, all voltages at output IC reference to VEE2.

Parameter Classification Note

Human Body Model 2 Per AEC Q100-002

Charge Device Model C2a Per AEC Q100-011

Parameter Symbol Min. Max. Units Note

Storage Temperature TS –55 150 °C

Operating Temperature TA –40 125 °C

IC Junction Temperature TJ — 150 °C

Average LED Input Current IF(AVG) — 20 mA

Peak Transient LED Input Current (<1-µs pulse width, 300 pps) IF(TRAN) — 1 A

Reverse Input Voltage (VCA – VAN) VR — 6 V

Primary Gate Drive Voltage VPGD – VP_GND –0.5 VCC1 + 0.5 or 6 V

ISEN Pin Voltage VISEN – VP_GND –0.5 VCC1 + 0.5 or 6 V

Input Supply Voltage VCC1 –0.5 6 V a

VADJ Pin Voltage VVADJ –0.5 VCC1 + 0.5 or 6 V a

COMP Pin Voltage VCOMP –0.5 VCC1 + 0.5 or 6 V a

/UVLO Pin Voltage V/UVLO –0.5 6 V a

/FAULT Pin Voltage V/FAULT –0.5 6 V a

TOK Pin Voltage VTOK –0.5 6 V a

TOUT Pin Voltage VTOUT –0.5 VCC1 + 0.5 or 6 V a

/UVLO Output Current (Sinking) I/UVLO — 4 mA

/FAULT Output Current (Sinking) I/FAULT — 4 mA

TOK Output Current (Sinking) ITOK — 4 mA

TOUT Output Current (Sinking) ITOUT — 1 mA

Total Output Supply Voltage VCC2 –0.5 30 V b

Positive Output Supply Voltage VCC2 – VE –0.5 22 V

Negative Output Supply Voltage VEE2 – VE –12 0.5 V

DST Pin Voltage VDST – VE –0.5 VCC2 – VE + 0.5 V

CS Pin Voltage VCS – VE –0.5 VCC2 – VE + 0.5 V

TREF Pin Voltage VTREF – VE –0.5 6 V

TIN Pin Voltage VTIN – VE –0.5 6 V

TB Pin Voltage VTB –0.5 VCC2 + 0.5 V b

Gate Drive Output Voltage, VO VO –0.5 VCC2 + 0.5 V b

Gate Drive Output Voltage, SSD VSSD –0.5 VCC2 + 0.5 V b

Gate Drive Output Voltage, MC VMC –0.5 VCC2 + 0.5 V b




Recommended Operating Conditions

Unless otherwise specified, all voltages at input IC reference to VEE1, all voltages at output IC reference to VEE2.

Peak Output Current, VO |IO(PEAK)| — 2 A c

Peak Output Sinking Current, SSD ISSD(PEAK) — 2 A c

Peak Output Sinking Current, MC IMC(PEAK) — 5 A c

Output IC Power Dissipation PO — 600 mW d

Input IC Power Dissipation PI — 150 mW e

a. Reference to VEE1.

b. Reference to VEE2.

c. Maximum pulse width = 1µs, maximum duty = 1%.

d. Output IC power dissipation is derated linearly above 105°C from 600 mW to 550 mW at 125°C for a high effective thermal conductivity board. For a low effective thermal conductivity board, output IC power dissipation is derated linearly above 105°C from 600 mW to 400 mW at 125°C. PCB thermal resistance characteristic must be considered so as not to exceed the absolute maximum rating. See Thermal Resistance Model for ACFH-3548T for details.

e. Input IC power dissipation does not require derating for a high effective thermal conductivity board. For a low effective thermal conductivity board, input IC power dissipation is derated linearly above 105°C from 150 mW to 120 mW at 125°C. See Thermal Resistance Model for ACFH-3548T for details.


Operating Temperature TA –40 125 °C

Input IC Supply Voltage VCC1 4.75 5.5 V a

a. Power-up sequence: Battery supply (VBAT+) to the DC-DC flyback transformer must be ready before VCC1 power up. When VCC1 is powered up from 0V to VCC1_TH+, DC-DC soft start current starts to charge the compensation network that is connected to the COMP pin. Subsequently, the VCC2 supply is regulated to its designed value. See Soft Start Operation for details.

Input IC Supply Decoupling Capacitor CVCC1 1 — µF

ISEN Input Voltage VISEN – VP_GND 0 1 V

Positive Output IC Supply Voltage VCC2 – VE 14.3 17.7 V

Negative Output IC Supply Voltage VEE2 – VE –6 0 V b

b. This supply is optional. It is required only when negative gate drive is implemented. Negative gate drive voltage can be programmed easily by connecting a Zener diode from VE to VEE2. Connect VE to VEE2 if negative gate drive bias is not required.

Output IC supply decoupling capacitor, VCC2 to VEE2 CVCC2 1 40 µF

Input LED Turn-on Current IF(ON) 10 16 mA

Input LED Turn-off Voltage (VAN – VCA) VF(ON) –5.5 0.8 V

DC-DC Flyback Controller PWM Duty Cycle DMAX — 50 % c

c. See Operation of Integrated DC-DC Flyback Controller for details.

TOUT Output Decoupling Capacitor CTOUT 1 10 µF

Full Scale TIN Input Voltage VTIN – VE 1.9 3.5 V

TREF Input Voltage VTREF – VE 2 5 V

CS Sense Voltage VCS – VE 0 5 V





Electrical and Switching Specifications

Unless otherwise specified, all minimum/maximum specifications are at recommended operating conditions; all voltages at input IC reference to VEE1, all voltages at output IC reference to VEE2. All typical values at TA = 25°C, VCC1 – VEE1 = 5V, VCC2 – VE = 16V, VE = VEE2 = 0V.

Parameter Symbol Min. Typ. Max. Units Test Conditions Figure Note

DC-DC Flyback Converter

VCC1 MOS Threshold VCC1_MOS_TH 0.85 1.3 1.7 V I/UVLO = 2 mA

VCC1 Turn On Threshold VCC1_TH+ 3.7 4.0 4.3 V

VCC1 Turn On Threshold

Hysteresis

VCC1_TH_HYS 0.05 0.25 0.5 V

PGD PWM Switching Frequency

fPWM 84 120 152 kHz a

Primary Gate Drive Output High Level

VPGD_H VCC1 – 0.5 VCC1 – 0.25 VCC1 – 0.01 V IPGD = –50 mA b

Primary Gate Drive Output Low Level

VPGD_L 0.01 0.2 0.4 V IPGD = 50 mA

Primary Gate Drive Rise Time tr_PGD 10 23 40 ns CPGD = 1 nF

Primary Gate Drive Fall Time tf_PGD 10 20 40 ns CPGD = 1 nF

Maximum PWM Duty Cycle DMAX 50 65 60 % VCOMP = 3.5V 7 c

ISEN Threshold VISEN_TH –

VP_GND

0.16 0.2 0.24 V

Regulated VCC2 Voltage

Tolerance

(VCC2 – VE) –5 0 5 % ICOMP = 0A,

VCC2 – VE = 16V

8

VCC2 Over-voltage Protection

Threshold, Low to High Reference to VE

VOV2_TH+ – VE 18.5 19.5 21 V

VCC2 Over-voltage Protection

Threshold, High to Low Reference to VE

VOV2_TH– – VE 17.5 18.5 20 V

IC Supply Current

Input Supply Current ICC1 4.7 7.5 9.8 mA 9

Output High Supply Current ICC2H 9.7 13.7 17.9 mA IF = 10 mA,

VCC2 – VE = 16V,

VE – VEE2 = 0V

10

Output Low Supply Current ICC2L 9.5 13.5 17.7 mA IF = 0 mA,

VCC2 – VE = 16V,

VE – VEE2 = 0V

10

Output High VE Supply Current IEH –2.3 –3.5 –4.8 mA IF = 10 mA,

VCC2 – VE = 16V,

VE – VEE2 = 5V

11

Output Low VE Supply Current IEL –2.3 –3.5 –4.8 mA IF = 0 mA,

VCC2 – VE = 16V,

VE – VEE2 = 5V

11




Logic Input and Output

LED Forward Voltage (VAN – VCA)

VF 1.25 1.55 1.85 V IF = 10 mA 12

LED Reverse Breakdown Voltage (VCA – VAN)

VBR 6 — — V IF = –10 µA

LED Input Capacitance CIN — 90 — pF

LED Turn On Current Threshold, Low to High

ITH+ — 2.6 7 mA VO = 5V 13

LED Turn On Current Threshold, High to Low

ITH– 0.3 2.0 — mA VO = 5V 13

LED Turn On Current Hysteresis

ITH_HYS — 0.6 — mA

/UVLO Logic Low Output Voltage

V/UVLO_L — — 0.4 V I/UVLO = 3 mA

/UVLO Logic High Output Current

I/UVLO_H — 0.015 10 µA V/UVLO = 5V

/FAULT Logic Low Output Voltage

V/FAULT_L — — 0.4 V I/FAULT = 3 mA

/FAULT Logic High Output Current

I/FAULT_H — 0.015 10 µA V/FAULT = 5V

TOK Logic Low Output Voltage VTOK_L — — 0.4 V ITOK = 3 mA

TOK Logic High Output Current

ITOK_H — 0.015 10 µA VTOK=5V

Gate Driver

High Level VO Voltage VOH VCC2 – 0.2 VCC2 –0.05 VCC2 – 0.01 V IO = –20 mA 14 d, e

Low Level VO Voltage VOL 0.01 0.05 0.2 V IO = 20 mA 15 e

Low Level SSD Voltage VSSD_L 0.01 0.05 0.2 V ISSD = 20 mA e

High Level VO Current IOH — — –1.5 A VO = VCC2 – 6V f

Low Level VO Current IOL 1.5 — — A VO = 6V f

Low Level SSD Current ISSD_L 2 — — A VSSD = 6V 16 f

VIN to High Level VO

Propagation Delay Time

tPLH — 130 250 ns VSource = 5V,

RLED = 260Ω,

Rg = 10Ω,Cload = 1 nF,f = 10 kHz,Duty cycle = 50%

17 g

VIN to Low Level VO

Propagation Delay Time

tPHL — 140 250 ns 17 h

Pulse Width Distortion PWD –50 10 100 ns i

Dead Time Distortion (tPLH – tPHL)

DTD –100 –10 50 ns j

VO 10% to 90% Rise Time tR — 25 — ns

VO 90% to 10% Fall Time tF — 25 — ns





Output High Level Common Mode Transient Immunity

|CMH| 50 — — kV/µs TA = 25°C

IF = 10 mA,

VCM = 1500V

k

Output Low Level Common Mode Transient Immunity

|CML| 50 — — kV/µs TA = 25°C

IF = 0 mA,

VCM = 1500V

l

Active Miller Clamp

Clamp Threshold Voltage VMC_TH 1.5 2 2.5 V

Clamp Low Level Sinking Current

ICLAMP 1.5 2.5 — A VCLAMP = VEE2 +

2.5V

18

VCC2 UVLO Protection (UVLO Voltage VUVLO Reference to VE)

VCC2 UVLO Threshold Low to

High

VUVLO2_TH+ 11.25 12.5 13.75 V VO > 5V m, n

VCC2 UVLO Threshold High to

Low

VUVLO2_TH– 10.35 11.5 12.65 V VO < 5V m, o

VCC2 UVLO Hysteresis VUVLO2_HYS 0.8 1 1.3 V

VCC2 to /UVLO High Delay tPLH_UVLO2 — 11.4 35 µs p

VCC2 to /UVLO Low Delay tPHL_UVLO2 — 38 100 µs q

VCC2 UVLO to VO High Delay tUVLO2_ON — 2.8 8 µs r

VCC2 UVLO to VO Low Delay tUVLO2_OFF — 1.9 6 µs s

Short-Circuit Protection (Reference to VE)

Blanking Release Threshold VTB_TH – VE 11.4 12.8 14.3 V

Desat Sensing Threshold VDST_TH – VE 9 10 11 V 19 t

Short-circuit Sense to /FAULT Low Signal Delay

TSC_FLT — 4.2 8 µs u

Output Mute Time due to Short-circuit FAULT

TSC(MUTE) 1.6 3 4.8 ms v

Time Input Kept Low Before /FAULT Reset to High

TSC(RESET) 1.6 3 4.8 ms w

Temperature Sense (TOUT Pin Reference to VEE1)

TOUT Output Voltage VTOUT – VEE1 1.692 1.750 1.830 V VTIN = 1.75V x

1.939 2.000 2.083 V VTIN = 2V x

2.185 2.250 2.336 V VTIN = 2.25V x

2.675 2.750 2.841 V VTIN = 2.75V x

Short Circuit Current Sense Threshold with Temperature Compensation (Reference to VE)

Short Circuit Current Sense (CS pin) Threshold

VCS_TH — 0.6 — V VTREF – VTIN =

1.2V

(VTREF –VTIN) / 2

a. PWM switching frequency of primary gate drive (PGD) is dithered in a range of ±6% typically over 3.3 ms.

b. The VPGD_H specification is guaranteed by design and is not subjected to production test.

c. The maximum PWM duty cycle, DMAX, is the hard limit set by IC for protection purposes. For discontinuous mode (DCM) operation, the maximum duty cycle for transformer design should be limited to 50% under system full load conditions.





Package Characteristics

d. For High Level Output Voltage testing, VOH is measured with a DC load current. When driving capacitive loads, VOH will approach VCC2 as IOH approaches zero.

e. Measured with a DC load, maximum pulse width = 1.0 ms, maximum duty cycle = 20%.

f. Maximum pulse width = 1 µs, maximum duty cycle = 1%.

g. tPLH is defined as propagation delay from 50% of input voltage source, VSource to 50% of high level output VO.

h. tPHL is defined as propagation delay from 50% of input source voltage, VSource to 50% of low level output, VO.

i. Pulse Width Distortion (PWD) is defined as (tPHL – tPLH) of any given unit.

j. Dead Time Distortion (DTD) is defined as (tPLH – tPHL) between any two parts under the same test conditions.

k. Common-mode transient immunity (CMTI) in the high state is the maximum tolerable dVCM/dt of the common-mode pulse, VCM, to ensure that the output will remain in the high state (that is, Output > 13V). A 330-pF and a 10-kΩ pull-up resistor are needed in fault, UVLO, and TOK detection modes.

l. Common-mode transient immunity (CMTI) in the low state is the maximum tolerable dVCM/dt of the common-mode pulse, VCM, to ensure that the output will remain in a low state (that is, Output < 1.0V). A 330-pF and a 10-kΩ pull-up resistor are needed in fault, UVLO, and TOK detection modes.

m. When UVLO is not active (VCC2 – VE > VUVLO2_TH+), VO of the ACFH-3548T is allowed to go high, the short-circuit protection features sensed by DST and CS pins of the ACFH-3548T will be the primary source of IGBT protection. When VCC2 exceeds VUVLO2_TH+, DST and CS sense remains functional, until VCC2 crosses below VUVLO2_TH–. Thus, the DST/CS detection and UVLO features of the ACFH-3548T work in conjunction to ensure constant IGBT protection.

n. This is the “increasing” (that is, turn-on or “positive going” direction) of VCC2 – VE.

o. This is the “decreasing” (that is, turn-off or “negative going” direction) of VCC2 –VE.

p. The delay time when VCC2 exceeded VUVLO2_TH+ to 50% of /UVLO positive going edge.

q. The delay time when VCC2 exceeded VUVLO2_TH– to 50% of /UVLO negative going edge.

r. The delay time when VCC2 exceeded VUVLO2_TH+ to 50% of VO positive going edge (that is, VO turn-on).

s. The delay time when VCC2 exceeded VUVLO2_TH– to 50% of VO negative going edge (that is, VO turn-off).

t. See During IGBT Short Circuit Event for further details.

u. The amount of time from when DST/CS threshold is exceeded to /FAULT negative-going edge.

v. The amount of time when DST/CS threshold is exceeded, driver output VO is mute to LED input.

w. The amount of time when DST/CS mute time is expired, LED input must be kept Low for /FAULT status to return to High.

x. The TOUT output voltage is tested at TA = 25°C and TA = 125°C.

Parameter Symbol Min. Typ. Max. Units Test Conditions Note

Input-Output Momentary Withstand Voltage

VISO 5000 — — VRMS RH < 50%, t = 1 minute, TA = 25°C a, b, c

a. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 VRMS for 1 second.

b. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table.

c. The device is considered as a two-terminal device: pins 1 to 16 are shorted together and pins 17 to 32 are shorted together.

Resistance (Input – Output) RI-O — 1014 — Ω VI-O = 500Vdc c

Capacitance (Input – Output) CI-O — 1.3 — pF f = 1 MHz




Thermal Resistance Model for ACFH-3548T

The diagram for measurement is shown in Figure 4. This is a multi-chip package with four heat sources, the effect of heating of one die due to the adjacent dice are considered by applying the theory of linear superposition. Here, one die is heated first, and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the second die is heated, and all the dice temperatures are recorded and so on until the fourth die is heated. With the known ambient temperature, the die junction temperature, and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 4 by 4 matrix for this case of four heat sources.

Figure 4: Diagram of ACFH-3548T for Thermal Resistance Model

Definitions

R11: Thermal Resistance of Die1 due to heating of Die1 (°C/W)R12: Thermal Resistance of Die1 due to heating of Die2 (°C/W)R13: Thermal Resistance of Die1 due to heating of Die3 (°C/W)R14: Thermal Resistance of Die1 due to heating of Die4 (°C/W)


27

26

25

24

23

22

21

20

4

5

6

7

8

9

10

11

19

18

17

12

13

14

15

30

29

1

2

28

3

16

32

31

Die 1:Input IC

Die 3:Output IC

Die 2:LED1

Die 4:LED2

R11 R12 R13 R14

.P1 T1

R21 R22 R23 R24 P2 T2R31 R32 R33 R34 P3 T3

R41 R42 R43 R44 P4 T4

=






P1: Power dissipation of Die1 (W)P2: Power dissipation of Die2 (W)P3: Power dissipation of Die3 (W)P4: Power dissipation of Die4 (W)

T1: Junction temperature of Die1 due to heat from all dice (°C)T2: Junction temperature of Die2 due to heat from all dice (°C)T3: Junction temperature of Die3 due to heat from all dice (°C)T4: Junction temperature of Die4 due to heat from all dice (°C)

Ta: Ambient temperature (°C)

T1: Temperature difference between Die1 junction and ambient (°C)T2: Temperature deference between Die2 junction and ambient (°C)T3: Temperature difference between Die3 junction and ambient (°C)T4: Temperature deference between Die4 junction and ambient (°C)

T1 = (R11 × P1 + R12 × P2 + R13 × P3 + R14 × P4) + Ta ------ ---------------------------------------------- (1)

T2 = (R21 × P1 + R22 × P2 + R23 × P3 + R24 × P4) + Ta ---------------------------------------------------- (2)

T3 = (R31 × P1 + R32 × P2 + R33 × P3 + R34 × P4) + Ta ---------------------------------------------------- (3)

T4 = (R41 × P1 + R42 × P2 + R43 × P3 + R44 × P4) + Ta ---------------------------------------------------- (4)




Measurement is done on both low effective thermal conductivity test board (according to JESD51-3) and on high effective thermal conductivity test board (according to JESD51-7).

Test Board TypeTest Board Conditions Thermal Resistance Power Dissipation Derating Chart

Low effective thermal conductivity board

Single layer board for signal.

Outer layer copper thickness: 2 oz.

Board size: 76.2 mm × 76.2 mm

R11: 44°C/W

R12: 40.3°C/W

R13: 24.5°C/W

R14: 37.2°C/W

R21: 28.5°C/W

R22: 145.2°C/W

R23: 27.8°C/W

R24: 34.5°C/W

R31: 26.7°C/W

R32: 43.4°C/W

R33: 39.5°C/W

R34: 44.7°C/W

R41: 28.6°C/W

R42: 39.9°C/W

R43: 32.2°C/W

R44: 101.4°C/W

Figure 5: Power Dissipation Derating Chart using Low Effective Thermal Conductivity Board

NOTE:

Input IC power dissipation is derated linearly above 105°C from 150 mW to 120 mW at 125°C.

Output IC power dissipation is derated linearly above 105°C from 600 mW to 400 mW at 125°C.

High effective thermal conductivity board

Four-layer board that embodies two signal layers, a power plane, and a ground plane.

Outer layer copper thickness: 2 oz.

Inner layers copper thickness: 1 oz.

Board size: 76.2 mm × 76.2 mm

R11: 34°C/W

R12: 20.3°C/W

R13: 15°C/W

R14: 22.2°C/W

R21: 16.2°C/W

R22: 119.2°C/W

R23: 17.5°C/W

R24: 19.5°C/W

R31: 15.1°C/W

R32: 22.3°C/W

R33: 30.4°C/W

R34: 29.3°C/W

R41: 16.3°C/W

R42: 18.9°C/W

R43: 22.2°C/W

R44: 91.5°C/W

Figure 6: Power Dissipation Derating Chart using High Effective Thermal Conductivity Board

NOTE:

Input IC power dissipation does not require derating for high effective thermal conductivity board.

Output IC power dissipation is derated linearly above 105°C from 600 mW to 550 mW at 125°C.




The application and environmental design for the ACFH-3548T must ensure that the junction temperature of the internal ICs and LED within the gate driver optocoupler do not exceed 150°C. The following examples are based on a typical circuit shown in Figure 23 for estimation of maximum power dissipation and corresponding effect on junction temperatures. This thermal calculation can only be used as a reference for thermal comparison between actual application board layout and PCB board according to JESD51-7. The actual power dissipation achievable will depend on the application environment (PCB layout, air flow, part placement, and so on).

Calculation of Input IC Power Dissipation, P1

Input IC Power Dissipation (P1) = PI(Static) + PIH(PGD) + PIL(PGD)

where

PI(Static) – Static power dissipated by the input IC = VCC1(MAX) × ICC1(MAX)PIH(PGD) – High side switching power dissipation at PGD pin

= (VCC1(MAX) × QG_ExtMOS × fPWM_DCDC(MAX)) × ROH_PGD(MAX) / (ROH_PGD(MAX) + RG_PGD) / 2PIL(PGD) – Low side switching power dissipated at PGD pin

= (VCC1(MAX) × QG_ExtMOS × fPWM_DCDC(MAX)) × ROL_PGD(MAX) / (ROL_PGD(MAX) + RG_PGD) / 2QG_ExtMOS – Gate charge of external MOSFET connected to PGD pin at supply voltagefPWM_DCDC(MAX) – Maximum DC-DC switching frequencyROH_PGD(MAX) – Maximum high side PGD pin output impedance = 0.5V/50 mA = 10ΩROL_PGD(MAX) – Maximum low side PGD pin output impedance = 0.4V/50 mA = 8ΩRG_PGD – Gate resistance connected to PGD pin

Example:

PI(Static) = 5.5V × 9.8 mA = 53.9 mWPIH(PGD) = (5.5V × 5 nC × 152 kHz) × 10Ω / (10Ω + 20Ω) / 2 = 0.70 mWPIL(PGD) = (5.5V × 5 nC × 152 kHz) × 8Ω / (8Ω + 20Ω) / 2 = 0.60 mWP1 = 53.9 mW + 0.70 mW + 0.60 mW = 55.2 mW

Calculation of Input LED Power Dissipation, P2

Input LED Power Dissipation (P2) = IF(LED) (Recommended Max) × VF(LED) (at 125°C) × Duty Cycle

Example:

P2 = 16 mA × 1.25V × 50% = 10 mW

Calculation of Output IC Power Dissipation, P3

Output IC Power Dissipation (P3) = PO(Static) + POH + POL

where:

PO(Static) – Static power dissipated by the output IC = (VCC2 – VEE2) × ICC2(MAX)(VCC2 – VEE2) – Total output power supply = Regulated VCC2(MAX) + Vz (Vz can be 0V if negative supply is not used)POH – High side switching power dissipation at VO pin

= (VCC2 – VEE2) × QG × fPWM × ROH(MAX) / (ROH(MAX) + RGH) / 2POL – Low side switching power dissipation at VO pin

= (VCC2 – VEE2) × QG × fPWM × ROL(MAX) / (ROL(MAX) + RGL) / 2QG – External buffer gate charge at supply voltage fPWM – Input LED switching frequencyROH(MAX) – Maximum high side VO pin output impedance at IOH(MIN) = 4Ω




RGH – Gate charging resistanceROL(MAX) – Maximum low side VO pin output impedance IOL(MIN) = 4ΩRGL - Gate discharging resistance

Example:

(VCC2 – VEE2) = 16.8V + 5.5V = 22.3VPO(Static) = 22.3V × 17.9 mA = 399.17 mWPOH = (22.3V × 200 nC × 10 kHz) × 4Ω / (4Ω + 20Ω) / 2 = 3.72 mWPOL = (22.3V × 200 nC × 10 kHz) × 4Ω / (4Ω + 20Ω) / 2 = 3.72 mWP3 = 399.17 mW + 3.72 mW + 3.72 mW = 406.61 mW

Calculation of LED2 Power Dissipation, P4

LED2 Power Dissipation (P4) = IF(LED2) (Design Max) × VF(LED2) (at 125°C) × Duty Cycle

Example:

P4 = 16mA × 1.25V × 50% = 10 mW

Calculation of Junction Temperature using High Effective Thermal Conductivity Board:

Input IC Junction Temperature = (37°C/W × P1 + 20.3°C/W × P2 + 15°C/W × P3 + 22.2°C/W × P4) + Ta Input LED Junction Temperature = (16.2°C/W × P1 + 119.2°C/W × P2 + 17.5°C/W × P3 + 19.5°C/W × P4) + Ta Output IC Junction Temperature = (15.1°C/W × P1 + 22.3°C/W × P2 + 30.4°C/W × P3 + 29.3°C/W × P4) + Ta LED2 Junction Temperature = (16.3°C/W × P1 + 18.9°C/W × P2 + 22.2°C/W × P3 + 91.5°C/W × P4) + Ta

Junction temperatures of the internal ICs and LEDs must not exceed 150°C.


ACFH-3548T Data Sheet Automotive Gate Drive Optocoupler with Flyback DC-DC Controller, Adaptive Blanking, Ad-

vance Short Circuit Protection and Isolated Analog Feedback for Temperature Sensing

Typical Performance PlotsFigure 7: PWM Duty Cycle vs. VCOMP Figure 8: ICOMP vs. Supply Voltage

0

10

20

30

40

50

60

0 1 2 3 4

D -

ELCYC YTUD

MWP

-%

VCOMP - COMPENSATION VOLTAGE - V-15

-10

-5

0

5

10

15

10 12 14 16 18 20 22

I COM

P-

TNERR

UC N

OITSNEP

MOC

-μA

VCC2 - SUPPLY VOLTAGE - V

Ta=-40°C

Ta=25°C

Ta=125°C

Figure 9: ICC1 vs. Temperature Figure 10: ICC2 vs. Temperature

6

6.5

7

7.5

8

8.5

-50 -25 0 25 50 75 100 125

I CC1

- T

NERRUC YLPP

US TUP

NI-m

A

TA - TEMPERATURE - C

12

12.5

13

13.5

14

14.5

15

-50 -25 0 25 50 75 100 125

i CC2

- T

NERRUC YLPP

US TUPT

UO

-mA


ICC2H

ICC2L

Figure 11: IE vs. Temperature Figure 12: IF vs. VF

-4.5

-4

-3.5

-3

-2.5

-50 -25 0 25 50 75 100 125

I E-

TNERR

UC YLPPUS EV T

UPTU

O-m

A


IEH

IEL

0.01

0.10

1.00

10.00

100.00

1.2 1.3 1.4 1.5 1.6

IF -

TNERRUC DRA

WROF DEL

-mA

VF - LED FORWARD VOLTAGE - V

Ta=25 C




Figure 13: ITH vs. Temperature Figure 14: VOH vs. IOH

1

1.5

2

2.5

3

3.5

4

4.5

-50 -25 0 25 50 75 100 125

I TH-

DLOHSERHT T

NERRUC DEL

-mA


ITH+

ITH-

10

11

12

13

14

15

16

0 0.5 1 1.5 2 2.5 3

V OH

- EGATL

OV HGIH TUPT

UO

-V

IOH - OUTPUT HIGH CURRENT - A

Ta=-40°C

Ta=25°C

Ta=125°C

Figure 15: VOL vs. IOL Figure 16: VSSD vs. ISSD

0

1

2

3

4

5

6

0 0.5 1 1.5 2 2.5 3

V OL

- EGATL

OV W

OL TUPT

UO

-V

IOL - OUTPUT LOW CURRENT - A

Ta=-40°C

Ta=25°C

Ta=125°C

0

1

2

3

4

5

6

0 1 2 3 4

V SSD

- EGATL

OV DSS-V

ISSD - SOFT SHUTDOWN CURRENT- A

Ta=-40°C

Ta=25°C

Ta=125°C

Figure 17: TP vs. Temperature Figure 18: ICLAMP vs. VCLAMP

50

70

90

110

130

150

170

190

210

230

250

-50 -25 0 25 50 75 100 125

T P-

YALED N

OITAGAPORP T

UPTU

O-n

s


TPLH

TPHL

0

1

2

3

4

5

6

0 2 4 6 8

I MC

-T

NERRUC G

NIKNIS LEVEL

WOL P

MALC-A

VMC - CLAMP LOW LEVEL VOLTAGE - V

Ta=-40°C

Ta=25°C

Ta=125°C




Figure 19: VDST vs. Temperature Figure 20: Propagation Delay Test Circuit

9

9.5

10

10.5

11

-50 -25 0 25 50 75 100 125

V DST

_TH

- DL

OHSERHT GNIS

NES TASED-V


27

26

25

24

23

22

21

20

LED2+

NC

VEE2

VCC2

CS

VE

DST4

5

6

7

8

9

10

11

PGDP_GND

/UVLO

/FAULT

TOUT

VCC1

VADJ

VEE1

19

18

17

VO12

13

14 CA

TOK

MC15 DNC

VEE2

30

29

1

2

28

3

SSD

TIN

NC

TB

TREF

ISEN

COMP

NC

AN

16 DNC

32

31

VEE2

DC+5V

260

5V0V

IF

Signal source

DC+16V

1μF

1μF

10 CLOAD

1nF

ACFH-3548T

10k

10k

10k

330pF

330pF

330pF

DC+4V

DC+2.8V0.1μF

0.1μF

Figure 21: CMR VO High Test Circuit Figure 22: CMR VO Low Test Circuit

27

26

25

24

23

22

21

20

LED2+

NC

VEE2

VCC2

CS

VE

DST4

5

6

7

8

9

10

11

PGDP_GND

/UVLO

/FAULT

TOUT

VCC1

VADJ

VEE1

19

18

17

VO12

13

14 CA

TOK

MC15 DNC

VEE2

30

29

1

2

28

3

SSD

TIN

NC

TB

TREF

ISEN

COMP

NC

AN

16 DNC

32

31

VEE2

DC+5V

165

16V

1μF

1μF

10 CLOAD

1nF

ACFH-3548T

5V +_

165

+_

+ _

High Voltage PulseVCM=1500V

10k

10k

10k

330pF

330pF

330pF

0.1μF

0.1μF 4V+_

2.8V+_

27

26

25

24

23

22

21

20

LED2+

NC

VEE2

VCC2

CS

VE

DST4

5

6

7

8

9

10

11

PGDP_GND

/UVLO

/FAULT

TOUT

VCC1

VADJ

VEE1

19

18

17

VO12

13

14 CA

TOK

MC15 DNC

VEE2

30

29

1

2

28

3

SSD

TIN

NC

TB

TREF

ISEN

COMP

NC

AN

16 DNC

32

31

VEE2

DC+5V

165

16V

1μF

1μF

10 CLOAD

1nF

ACFH-3548T

165

+_

+ _

High Voltage PulseVCM=1500V

1μF

10k

10k

10k

330pF

330pF

330pF

0.1μF

0.1μF 4V+_

2.8V+_




Figure 23: ACFH-3548T Typical Gate Driver Circuit with IGBT Desaturation/Emitter Over-Current Sensing, Temperature Sensing, and Negative Gate Bias Set by VZ

NOTE: The values of the components are subjected to change with various application requirements.

adcom Limited Proprietary and Confidential. © 2016 Broadcom Limited. All rights reserved.

uC

PWM_BOT

PWM_TOP

5V

Digital I/O

Digital I/O

VBAT + VCC2 - VE = 16V (Default)

VZ**

Flyback Transformerturn ratio 3.5

DC+5V

VBAT -

GND

IGBT

S

A

G

K

E

A/D

ACFH-3548T

27

26

25

24

23

22

21

20

LED2+

NC

VEE2

VCC2

CS

VE

DST4

5

6

7

8

9

10

11

PGD

P_GND

/UVLO

/FAULT

TOUT

VCC1

VADJ

VEE1

19

18

17

VO12

13

14 CA

TOK

MC15 DNC

VEE2

30

29

1

2

28

3

SSD

TIN

NC

TB

TREF

ISEN

COMP

NC

AN

16 DNC

32

31

VEE2

6.5V – 24V

VSE

VF

+

-

20μF20μF

1.8k220nF

100pF470k

22nF

>110V

>60V

Lp Ls

VDS > 60V

Rsense50m

20

Digital I/O

100pF

1.8k *

10k

200

15k *

19.1k * 5.9k *

4.7 *

12 *

Notes:* to be tuned to IGBT** to be shorted if negative

supply is not needed

1k *

RADJ1

RADJ2

10k 10k 10k

MOSFET

130

130

MURA160T3G

20 10uF

10uF

1μF




Description of Operations and Functions

Operation of Integrated DC-DC Flyback Controller

The ACFH-3548T integrated DC-DC flyback controller operates in a discontinuous conduction mode (DCM) at a fixed average switching frequency of 120 kHz. It converts a wide 6.5V to 24V input range to default 16V positive output supply (VCC2 – VE) when the VADJ pin is connected to ground of left open and programmable negative output voltage (VEE2 – VE) can be set by the Zener diode.

The primary control block implements direct duty cycle control logics for line and load regulation. Primary winding current is sensed and limited to VISEN_TH to prevent transformer short-circuit failure from damaging the primary switch. The sense resistor (Rsense) is selected based on the maximum primary winding current limit and maximum power dissipation requirement. Secondary output voltage, VCC2, is sensed and feedback to the primary control circuits. The closed loop control circuits always regulates VCC2 with reference to VE, based on the configurations set at the primary side of IC VADJ pin. The voltage ratio of VADJ over VCC1 determines (VCC2 – VE) voltage:

is defaulted at 0.4125 if the VADJ pin is left floating or tied to ground. VCC2 is approximated to the following:

Figure 24: Regulated Positive Supply Voltage (VCC2 – VE) vs (VADJ / VCC1) Ratio

= =+

21.48 ( 0.4125) + 16




The sum of the resistors used in the voltage divider for setting VADJ is to be less than 10 kΩ to avoid interference from the internal default voltage divider. The following table shows the typical resistor values for setting VCC2.

When VCC2 is greater than the specified VCC2 over-voltage threshold (VOV2_TH+), VCC2 over-voltage protection is triggered. The PGD pin on the primary side of gate driver is shut down to protect secondary over-voltage failure and the DC-DC flyback conversion will cease. When VCC2 reduces to VOV2_TH–, the PGD pin is released and DC-DC regulation resumes its normal operations.

While designing the flyback transformer for DCM controller, the maximum PWM duty cycle must be limited to 50% or less at the minimum input voltage (for example, VBAT+ = 6.5V) under full load conditions. A discrete flyback transformer should be connected to ACFH-3548T according to Figure 23 for complete isolated DC-DC converter. The input LED should be kept off while powering up the VCC1. To ensure proper operation of the DC-DC converter, fast VCC1 rise time (≤ 5 ms) is preferred for soft start function to control the inrush current. If VCC2 fails to rise above 6V at the end of the soft start period (about 20 ms), the primary switch is turned off to prevent a possible VCC2 short-circuit event during start-up. The DC-DC controller can be restarted by power reset VCC1.

The average PWM switching frequency of primary gate drive (PGD) is dithered ± 6% typically from center frequency of 120 kHz. Frequency dithering feature helps to achieve better EMI performance by spreading the switching and its harmonics over a wider band.

Soft Start Operation

ACFH-3548T is designed with built-in soft start feature. When VCC1 is higher than VCC1_TH+, the built-in soft start circuit starts to function. Typical soft start timing is 20 ms, where a typical soft start current profile steps up from 3 µA, then 6 µA, and finally 10 µA charges up the compensation network through the VCOMP pin and gradually increases the VCOMP voltage to the correct working level. Figure 25 shows the typical DC-DC start up waveforms.

Table 2: Typical Resistor Values for Setting VCC2

RADJ1 (kΩ) RADJ2 (kΩ) (V/V) VCC2 (V)

4.70 2.40 0.3380 14.4

4.70 3.32 0.4140 16.0

4.70 4.22 0.4731 17.3




Figure 25: Typical DC-DC Start Up Waveforms

NOTE:

VSAW is IC internal saw waveform and cannot be measured externally. VSAW frequency is not drawn to scale.

Typical DC-DC switching frequency at the PGD pin is 120 kHz. VPGD frequency is not drawn to scale.

Status Flags

The status flags at the input side reflect the state of the circuit operation. Figure 26 exemplifies how the status flags react when VCC2 ramps up and down when VCC1 is ready.

Normal operation: All of the status flags (/UVLO, /FAULT, and TOK) are in Hi-Z state. These pins are pulled high through the external resistors.

Under-voltage Fault: When VCC1 is below the VCC1 turn-on threshold (VCC1_TH+) or VCC2 falls below the UVLO2 threshold (VUVLO2_TH–), both of the /UVLO and TOK flags are pulled low.

VCC2 Over-voltage Fault: When VCC2 is over the VCC2 over-voltage protection threshold (VOV2_TH+), only the TOK flag is pulled low.

DC-DC Flyback Over-current Fault: When ISEN voltage exceeds the threshold VISEN_TH, the /UVLO flag is pulled low. It is reset to high upon next PGD switching cycle. If the DC-DC over-current fault persists, the /UVLO pulses at the PGD PWM frequency. In the case that /UVLO has a large filter capacitor, the short upward /UVLO pulses are filtered, resulting in a persistent low /UVLO for the affected PGD PWM cycles. See Figure 27.

IGBT Short-circuit Fault: If a short-circuit fault occurs by triggering at DST pin or CS pin, the IGBT gate is turned off adaptively according to the voltage sensed at the DST pin and the CS pin. The /FAULT flag is pulled low.

1.25

4.0

2.625VCOMP (V)

Time

5VCC1_TH+

VCC1 (V)

Time

VUVLO2_TH+

VCC2 – VEE2 (V)

Time

VSAW (V)

VPGD (V)5

(Note a)

(Note b)




LED2 Fault: When VCC2 – VEE2 supply voltage is greater than typical 6V, the secondary side LED2 starts to pulse to inform the primary IC that the feedback channel is working normally. If the primary IC detects no signal from LED2, it is presumed that LED2 is faulty and all the status flags (/UVLO, /FAULT, and TOK) are pulled low. The primary IC stops the DC-DC regulation by pulling the PGD pin and the COMP pin low. The driver IC’s power (VCC1) then needs to be recycled for IC reset. Figure 28 shows a typical gate driver circuit with low-dropout linear regulator (LDO) for primary IC (VCC1) reboot during LED2 fault condition.

TOUT Invalid: The TOUT reading is invalid with the indicator TOK pulled low, during UVLO fault, VCC2 over-voltage fault and IGBT short-circuit fault.

Figure 26: Status Indicators During VCC2 Ramp Up and Ramp Down

Table 3: Status Flags

Conditions

Status Flags

/UVLO /FAULT TOK

Normal operation Hi-Z Hi-Z Hi-Z

VCC1 under-voltage/VCC2 UVLO fault Low Hi-Z Low

VCC2 over-voltage fault Hi-Z Hi-Z Low

DC-DC over-current fault Pulsed Hi-Z Hi-Z

IGBT short-circuit fault High Low Low

LED2 fault Low Low Low

TOUT invalid Don’t Care Don’t Care Low

VCC2

TOK

/UVLO

/FAULT

LED2 fault UVLO fault Normal LED2 faultUVLO faultNormalOV fault

~6V

VUVLO2_TH+VOV2_TH+ VOV2_TH-

VUVLO2_TH-

~5V




Figure 27: DC-DC Flyback Over-Current Fault Reporting

Figure 28: Typical Gate Driver Circuit with Low-Dropout Linear Regulator (LDO) for VCC1 Reboot

PGD

ISEN

Case 1: /UVLO with small capacitor: /UVLO will follow PGD frequency

Case 2: /UVLO with large capacitor: /UVLO will be kept low due to large capacitor

ISEN over current thresholdOver-current event occurs

Broadcom Limited Proprietary and Confidential. © 2016 Broadcom Limited. All rights reserved.

uC

PWM_BOT

PWM_TOP

5V

Digital I/O

Digital I/O

VBAT + VCC2 - VE = 16V (Default)

VZ**

Flyback Transformerturn ratio 3.5

DC+5V

VBAT -

GND

IGBT

S

A

G

K

E

A/D

ACFH-3548T

27

26

25

24

23

22

21

20

LED2+

NC

VEE2

VCC2

CS

VE

DST4

5

6

7

8

9

10

11

PGD

P_GND

/UVLO

/FAULT

TOUT

VCC1

VADJ

VEE1

19

18

17

VO12

13

14 CA

TOK

MC15 DNC

VEE2

30

29

1

2

28

3

SSD

TIN

NC

TB

TREF

ISEN

COMP

NC

AN

16 DNC

32

31

VEE2

6.5V – 24V

VSE

VF

+

-

20μF20μF

1.8k220nF

100pF470k

22nF

>110V

>60V

Lp Ls

VDS > 60V

Rsense50m

20

Digital I/O

100pF

1.8k *

10k

200

15k *

19.1k * 5.9k *

4.7 *

12 *

Notes:* to be tuned to IGBT** to be shorted if negative

supply is not needed

1k *

RADJ1

RADJ210k 10k 10k

MOSFET

130

130

MURA160T3G

20 10uF

10μF

1uF

INEN

OUT

GND

5V LDO

Control




Description of Gate Driver and Miller Clamping

The gate driver is directly controlled by the LED current. When the LED current is driven high, the main output driver (VO) of the ACFH-3548T delivers 1.5A sourcing current to output buffer to drive the IGBT’s gate. While LED is switched off, it provides 1.5A sinking current to the output buffer to switch the gate off fast.

When UVLO is not active (VCC2 – VE > VUVLO2_TH+), VO of the ACFH-3548T is allowed to go high. IGBT desaturation fault detection (by the DST pin) and over-current detection (by the CS pin) of the ACFH-3548T is the primary source of IGBT protection. When VCC2 exceeds the VUVLO2_TH+ threshold, DST and CS detections remain functional, until VCC2 crosses below the VUVLO2_TH– threshold. Thus, the DST/CS detection and UVLO features of the ACFH-3548T work in conjunction to ensure constant IGBT protection.

The Miller clamping transistor (MC pin) and all pull-down drivers are activated when the gate voltage drops below VMC_TH voltage, to provide low impedance path to the Miller current.

Description of Under Voltage Lock Out

Insufficient gate voltage to IGBT can increase turn-on resistance of IGBT, resulting in large power loss and IGBT damage due to high heat dissipation. The ACFH-3548T monitors the output power supply constantly. When the output power supply is lower than under voltage lockout (UVLO) threshold, the gate driver output shuts off to protect IGBT from low voltage bias. During power up, the UVLO feature forces the ACFH-3548T’s output low to prevent unwanted turn-on at low voltage. When power supply (VCC2) voltage increases more than VUVLO2_TH+ threshold, the /UVLO fault status is cleared and the gate driver resumes its normal function automatically.

Figure 29: Circuit Behavior During Power Up, Power Down, and UVLO

VCC1

VCC2

LED IF

VO tUVLO_OFF

VUVLO2_TH-

/UVLO

VCC1_TH+

tUVLO_ON

tPHL_UVLO2 tPLH_UVLO2

VUVLO2_TH+

UVLO2UVLO2UVLO1

Low

UVLO2

VUVLO2_TH-VUVLO2_TH+VUVLO2_TH+

VCC1_TH-

Low

UVLO1UVLO2

High Z

/FAULT High Z

VUVLO2_TH-




Description of IGBT Short-circuit Protection and Shutdown Sequence

1. ACFH-3548T monitors the DST pin and the CS pin for IGBT short-circuit conditions.

2. Short-circuit detection on the DST pin and the CS pin is only active when the voltage at the TB pin is greater than the VTB_TH threshold. This corresponds to the period when the IGBT is in conduction mode.

3. Short-circuit protection is triggered in either of the following situations.

– Voltage on the DST terminal exceeds VDST_TH threshold.

– Voltage on the CS terminal exceeds the VCS_TH threshold.

4. Shutdown is triggered by LED input turning-off or short-circuit events. ACFH-3548T executes an adaptive shutdown for any shutdown operation.

a. CS information is latched into memory cells at the start of every shutdown sequence.

b. DST is first checked to find out whether IGBT is in desaturation short condition. If VDST > VDST_TH, the SSD driver is selected to softly shut down the IGBT gate throughout the shutdown process (IGBT arm short circuit, Figure 30).

c. If VDST < VDST_TH, main driver VO is first used to minimize Miller plateau time. As the IGBT collector voltage rises, DST will rise above VDST_TH, which also means that Miller plateau is coming to its end. Then the next most appropriate driver is selected based on the latched CS information VCS.

d. If VCS > VCS_TH, the SSD driver is selected for slow soft shutdown (IGBT wire short circuit, Figure 31). If VCS < VCS_TH, the main driver VO continues to be used for a quick normal shutdown (normal operation, Figure 32).

5. In a short-circuit event, /FAULT status is always reported to MCU (see Figure 33).

6. ACFH-3548T starts an adaptive shutdown.

7. /FAULT output goes low, notifying the microcontroller of the short-circuit fault condition.

8. PWM commands at input LED will be ignored during mute time tSC(MUTE).

9. When tSC(MUTE) expires, LED input must be kept low for tSC(RESET) duration before the fault condition can be cleared.

10. After the fault condition is cleared, /FAULT flag will then return to high, and output starts to respond to LED input.




Figure 30: Adaptive Shutdown (IGBT Arm Short Circuit – Direct Soft Shutdown)

VCS_TH

Hi-Z

Hi-Z

Hi-Z

VDST_TH VCC2

VMC_TH

VCC2

Blanking time set by TB

MC

SSD

IF

DST

VSENSE

ICE

VGE

VO

VCE




Figure 31: Adaptive Shutdown (IGBT Wire Short Circuit – Hard then Soft Shutdown)

Hi-Z

Hi-Z

Hi-Z

MC

SSD

IF

VO

VCS_TH

VMC_THVGE

Miller Plateau

VCE VCC2

VDST_THDST VCC2

VSENSE

ICE





Figure 32: Adaptive Shutdown (Normal Operation – Hard Shutdown)

Figure 33: Status Report During a Short-Circuit Event

VCS_TH

Hi-Z

Hi-Z

VMC_TH

VDST_TH

MC

SSD

IF

DST

VSENSE

ICE

VGE

VO

VCE

Miller Plateau

VCC2

VCC2


Short Circuit Event

tSC_FLT

IFVCS_TH

VGE

VSENSE

Hi-Z

Hi-Z

Hi-Z

TOK

/FAULT

tSC(MUTE)

tSC(RESET)


/UVLO




Description of Blanking Time Control

ACFH-3548T monitors the DST pin and the CS pin for short-circuit conditions when the input LED is turned on. However, during operations, the initial states of the DST and CS pins when the LED turns on may trigger a false short-circuit alarm. It is necessary to ignore DST and CS pins for the initial “blanking time” period when the IGBT gate voltage is still around its Miller plateau.

By comparing IGBT gate voltage, VG, with the internal reference VTB_TH of the TB pin, the end of the turn-on Miller plateau can be determined. Blanking time is only released when the gate voltage, VG, presented at TB pin is higher than VTB_TH.

A simple circuit shown in Figure 34 is used to tune the effective VG threshold lower to release blanking time more quickly. The effective VG threshold with VO adjusted is as follows.

R2 and CTB provide low-pass filtering of the spikes at VG.

For example, if VCC2 is 16V and VTB_TH is 13V, setting R1 = 1.8 kΩ and R2 = 1 kΩ sets the effective VG threshold to 11.3V. VG_TH should be larger than the Miller plateau gate voltage Vmiller that corresponds to the designed IGBT short-circuit protection current Ishort.

Figure 34: Simple Circuit for Blanking Time Control

Description of Temperature Sensor

1. TIN takes input of the voltage across temperature sensor diodes to sense temperature information.

2. Enabled by superior optical coupling and advanced sigma-delta (S-D) modulation technology, TIN voltage is transmitted over to TOUT pin on the primary side, with low offset and high gain accuracy.

3. High accuracy unity gain between TOUT and TIN is maintained for nominal temperature range.

4. No temperature information is transmitted during UVLO or short-circuit fault condition. The TOUT pin is pulled low for all fault conditions. The TOK flag is set to low as an indicator that TOUT reading is no longer valid during the fault conditions. See Table 3 for status flags information.

j

_ = _ ( _ )2

1 ×

TB 19

VO 21

CTBVEE2 17

IGBTGBuffer DriverVG

R2

R1




Figure 35: Transfer Function of Temperature Sensor (TIN and TOUT)

Description of Temperature Compensation Function

The input TREF is used to match the negative temperature coefficient of the temperature sensor diodes to the positive temperature coefficient of the IGBT emitter sense voltage, VSE.

The output of the temperature compensation block in Figure 1 gives the reference voltage, VCS_TH, for the comparator at the CS pin, providing the threshold for short-circuit detection.

TREF can be calculated using the following equation.

Where:

KVF: Normalized thermal co-efficient of temperature sensor voltage, VF

KVSE: Normalized thermal co-efficient of IGBT emitter current sensor voltage, VSE

VFTO: Temperature sensor voltage, VF at temperature T0 (for example: 25°C)

Where:

VFT1: Temperature sensor voltage, VF at temperature T1 (for example: 125°C)

Where:

VSET0: Emitter current sensor voltage, VSE at temperature T0 (for example: 25°C)

VSET1: Emitter current sensor voltage, VSE at temperature T1 (for example: 125°C)

3.5V0

3.5V

TIN

TOUT

= × 1

=

=




Printed Circuit Board Layout Considerations

Take care when designing the layout of printed circuit board (PCB) for optimum performance. Maintain adequate spacing between the high-voltage isolated circuitry and any input-referenced circuitry. Maintain the same minimum spacing between two adjacent high-side isolated regions of the printed circuit board as well. Insufficient spacing reduces the effective isolation and increases parasitic coupling that will affect CMR performance.

The placement and routing of supply bypass capacitors require special attention. During switching transients, the majority of the gate charge is supplied by the bypass capacitors. Maintaining short charging and discharging paths between capacitors and gate can help to achieve clean switching waveforms and low supply ripples. Have supply and ground planes for VCC2 and VEE2. Connect IC power pins, such as VCC2 (pin 22) and VEE2 (pins 17, 31, and 32) directly to these planes using multiple via holes right next to the pins. Figure 36 shows a good example of PCB layout arrangement in comparison with a bad one.

Figure 36: Good and Bad PCB Layout Example

Similar layout guidelines are applicable to input side circuitry, such as power supply VCC1 (pin 5), input side ground VEE1 (pin 4), and supply decoupling capacitors. Place the compensation network circuitry that connected to COMP (pin 7) next to IC with short traces. For thermal dissipation purposes, place the large copper area for top layer VEE2 (pins 17, 31, and 32) and connect the copper area with multiple via holes to VEE2 plane at the bottom layer of PCB as shown in Figure 37.

VCC2 plane

Pin 17, 31 and 32 are all connected to VEE2 plane.

VEE2

22VCC2

31VEE2

VEE2

32

17

VEE2 plane

Pin 17, 31 and 32 are all connected to VEE2 plane.

Bad Example: Decoupling capacitor is connected to VCC2 pin through a thin routing wire with no VCC2 plane

VEE2 planeLong Top layer VCC2 trace

Goode Example: Decoupling capacitor is connected between VCC2 and VEE2 planes

VEE2

22VCC2

31VEE2

VEE2

32

17




Figure 37: Example of Recommended Layout

VCC2 planeVEE2 planeVEE1 plane

VCC1 plane

ACFH-3548T

Large copper area for VEE2 at top layer with multiple via holes connected to bottom layer VEE2 plane for heat dissipation.

Bypass capacitor is connected between VCC2 and VEE2 planes.

Desat decoupling capacitor and schottky protection diode are placed right next to the DESAT and use kelvin connection to VE pin.

DC-DC compensation circuit is placed right next

to the IC COMP pin and grounded to VEE1 plane.

Connect P_GND to VEE1 plane directly.

Bypass capacitor is connected between VCC1

and VEE1 planes.27

26

25

24

23

22

21

20

LED2+

NC

VEE2

VCC2

CS

VE

DST4

5

6

7

8

9

10

11

PGDP_GND

/UVLO/FAULT

TOUT

VCC1VADJ

VEE1

19

18

17

VO12

13

14 CA

TOK

MC15 DNCVEE2

30

29

1

2

28

3

SSD

TIN

NC

TB

TREF

ISEN

COMP

NC

AN

16 DNC

32

31

VEE2


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ACFH-3548T Data Sheet

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