Account, Tool Setup and Study of the Basic I-V Equation of the MOS Transistor

7/26/2019 Account, Tool Setup and Study of the Basic I-V Equation of the MOS Transistor

1/16

ABM H. Rashid, Dept. of EEE, BUET Page 1 13/09/2011

Department of Electrical & Electronic EngineeringBangladesh University of Engineering & Technology

EEE458 VLSI II Laboratory

Lab. 1:Account, Tool Setup and Study of the basic I-V equation of the MOS transistor

in the technology library

Learning Objectives:

To login, start a shell tool and start the Cadence virtuoso software

To learn about PDK and add the PDK library to the Library Manager

To create a working library and getting familiar with technology

To study the IV characteristics of the MOS transistor in the technology library

1-1. Getting Started

Objective: To login, start a shell tool, start the Cadence Software

1. Log in to your workstation using the username and password provided. Your user name will be

EEE458GRPxand your password will bevlsi2, wherexis any number from 1 to 20

2. Open a terminal by selecting System Console. A console window opens with present

working directory as /vhome/EEE458GRPx

3. In the console execute >ssh -XC CadenceServer.local

The following prompt will appear

[email protected]'s password:

Provide the password. The CadenceServer> prompt will appear.

4. Now you should copy the following four files from the "pdk_install_directory" (which is

/usr/local/cadence/local/gpdk090_v4.6/ in our case) : (i) .cshrc (ii) .cdsenv (iii) cds.lib (iv)

display.drf

5. Source the .cshrc file. To do this in the console execute CadenceServersource .cshrc

6. Type virtuoso ( CadenceServer>virtuoso) and virtuosos Command Interpreter Window (CIW)

appears at the bottom of the screen.


2/16


1-2. Learning the Fundamentals of PDK

Objective : To learn about PDK and add the PDK library to the Library Manager

All VLSI design starts with a Process Design Kit known briefly as PDK. A PDK contains the

process technology and needed information to do device-level design in the Cadence Design

Framework II (DFII) environment. The following diagram shows the relationship of the various

components of the PDK and their relationship to the Cadence Design System (CDS) Tool .

Throughout the labs we will use a generic, foundry independent 90nm CMOS mixed-signal processkit developed by Cadence. We will call it generic PDK 90 nm briefly as gpdk90. As seen from the


3/16


figure above a PDK contains all the necessary design and technology data to successfully design

and simulate a VLSI chip on a particular foundry. The foundry provides the necessary

technological data, design rules, and the device models. Also PDK contains schematic symbols

with all necessary views, as well as device extraction rules for Layout versus Schematic (LVS)

check. It also provides parasitic extraction rules.

1-3. Starting the Online Help

In the CIW window Scroll the Helpmenu and select 'Cadence Documentation'. The Cadence on-

line help documents appear. Alternately you can type cdshelpin the Linux window and the same

documentation will appear.

1-4. Creation of a Design Project

A unique directory should be created for each circuit design project. The following command can

be executed in UNIX:

CadenceServer> mkdir ~/gpdktraining

1-5. Adding the gpdk090 library to your library path

The Cadence Library Path Editor helps you to define the libraries being used in your design. You

can set your cds.lib file or lib.defs file, or both, to point to the reference and design libraries youwant to use in your design.

1. In the CIW, execute ToolsLibrary Path Editor EditAdd Library. The add Library

form appears.

2. Add the gpdk090 library from /usr/local/cadence/local/gpdk090_v4.6/libs.0a22 and press ok

3. In the library path editor execute File Save as. Make sure that both cds.lib and lib.defs are

selected.


4/16


Click OK the new paths will be saved and you will be able to use the above library.

4. Following the above procedure add the analogLiblibrary from the following location

/usr/local/cadence/ic612/tools.lnx86/dfII/etc/cdslib/artist

5. Similarly add the library basicfrom the following location

/usr/local/cadence/ic612/tools.lnx86/dfII/etc/cdslib

1-6. Schematic Entry

To create a library and getting familiar with the technology : MOS I-V characteristics

Creating a library

Now we will create a working library to store our design and attach it to desired technology library.

1. In the CIW, execute FileNewLibrary

2. The new Library form appears. In the name field of the New Library type gpdktraining.

3. In the field under the Directory Section, verify that the path to the library is set to

/var/home/EEE458GRPx/4. Select Attach to an existing tech fileand click ok.


5/16


5. Attach Library to Technology Lib appears.

6. Select the gpdk90 technology library and click OK.

7.

In the Library Manager window verify that the gpdktraining library is listed.

Getting Familiar with Technology: MOS IV Characteristics

In this exercise, you will learn how to enter simple schematic and run a simulation to obtain

characteristics of transistors for our technology (gpdk090).

Entering Design Schematic

1. In the Command Interpreter Window (CIW) or Library manger execute File -->New --

>Cellview.2. Set up the create new file form as follows

Library Name gpdktraining, Cell Name MOS_IV,

View name schematic, Type Schematic,

Application Open with Schematic L

3. Click Okwhen done.


6/16


A blank schematic window for the MOS_IV design appears.

In the schematic window , execute CreateInstance.

4. Next, we will create simple schematic consisting of an NMOS, a PMOS, and a few bias

voltage sources. To create an instance, you can clickAdd Instancein the Virtuoso

schematic editor or simply use shortcut key i. The following dialog will appear:

Click Browse to select a library component

Another window will show up. Choose gpdk090 library, nmos1v cell, symbol view. (note:

while you are doing this, the Add Instance window is getting updated as well).


7/16


5. Similarly add pmos1v cell.

6. Now we can adjust the size of the transistors by editing instance properties. Left click on

the NMOS to select the component. Then, press q to modify its properties or in

schematic window selectEdit Properties Object. Modify the transistor width and set

Total Width to 240nm (this is 2x the minimum channel width), then press Tab key and the

Finger Width will be set to the same value. Click OK


8/16


7. Repeat this for PMOS to set Total Width and Finger Width to 480nm. To deselect the

object press keyboard command contrl-d.

8. Next, instantiate DC voltage source (cell vdc from analogLib library) to bias the transistors.

Place VDC in a suitable place in the schematic window to simulate Drain-Source Voltge

VDS. Similarly place VDC to simulate Gate Source Voltage VGS. Since we are going to

sweep values of gate and drain voltages, specify parametric values VGS and VDS as DC

voltage under object properties.

Now save the parametric settings shown below:

9. Use Add Wire menu or simply press w key to enter wiring mode / Esc to exit. It is a

good practice to periodically save your work by clicking on Check and Save button (the


9/16


checkmark button just below of the Tools menu). You can also save your work from the

drop-down menu DesignSave.

10.The last step is to add zero valued voltage sources in series with the transistors in order to

be able to probe the currents. The final schematic looks like this:

Click Close and point your mouse cursor over the Virtuoso editing window.

Make sure that the view name field in the form is set to symbol. You will update the Library

Name, Cell Name, and the property values given in the table below as you place each

component.

1-7. Netlist Creation and Simulation using Spectre and observation of MOS I-V

Characteristics

Opening the Analog Design Environment

1. In the Schematic window execute LaunchADE L

Analog Design Environment (ADE) window will open.


10/16


2. Select your design by executing SetupDesignMOS_IV

3. Select the directory where the simulation data will be saved by executing Setup

Simulator/Directory/host. The default directory is created in your working directory with

name 'simulation'. You can choose this directory or choose any other directory.

4. Set up the model libraries by executing Setup Model Libraries. Select the following

model library /usr/local/cadence/local/gpdk090_v4.6/models/spectre/gpdk090_mos.scs

5. In this model libraries there are models to simulate various corners like fast-fast (FF), fast-

slow (FS), typical-typical(TT) etc. We will choose the section typical from the section scroll

bar and select the section 'TT_s1v'. These will enable us to use the TT models of the 1.2 V

MOS transistors.

6. Now we will edit the variables. Execute Variables Editto specify initial values for VDS

and VGSparameters. Enter VDS in the Name field and 0.5 in the Value (Expr) field and


11/16


click Add to save the variable settings. Repeat this for VGS, you should get the window as

shown on the left and click OK.

7. Now choose the analysis to be done. Select DC analysis. In the DC analysis window select

Design Variable and put Variabel Name VDS. Select Sweep range as start 0 stop 1, Step

type Linear, Step Size 0.05. Repeat the same for the variable VGS.


12/16


8. Your Analog Design Environment window should now look like this:

9.

Select the output to be plotted by executing Outputs To be plotted Select on

schematic in the ADE window. Schematic window will pop up, click on the positive

terminal of dummy voltage sources to select IDS for NMOS and PMOS.


13/16


The Analog Design Environment window should now look like this:

10.Before closing the Virtuoso Analog Environment window, it is a good idea to save design

settings in a state file, so we can load it up next time. To do this, click on Session Save

State and save state name in the Save As field as state_MOS_IV. Next time you run

Cadence, you can simply load the simulation settings from this file.

Note: when you are loading up the file, dont forget to specify the correct path (in our case,

it is: Var/home/GRPxxx/.state_MOS_IV).

11.The settings so far would generate I-V curve for a single value of VGS variable (0.5V). In

order to sweep VGS, go to ToolsParametric Analysis and set the parameters as shown

below:


14/16


Here select sweep 1 variable VGS, From 0.2 to 1 Step control Linear, Total Steps 5.

12.It is a good idea to save design settings again in a state file, so we can load it up next time.

To do this, click on Session Save Stateand set State Save Directory to

~/.artist_states

and save state name in the Save As field as state_MOS_IV. Next time you run Cadence,

you can simply load the simulation settings from this file.

Note: when you are loading up the file, dont forget to specify the correct path (in our case,

it is: ~.artist_states).

13.Now in Parametirc analysis window perform Analysis Start-selected. to create netlist

and run parametric simulation. After the simulation finishes, you will get a plot of

overlapped I-V curves for NMOS and PMOS that look like this:


15/16


Finally, we are going to separate the plots into two sub-graphs. Click on the New Subwindow

button as shown in the figure above. Left click on the V4 curves, one by one, and drag over to the

right plot. We can format the axis to display currents on the same scale. Double-click on the Y-

axis labels for the NMOS (left plot) and enter the Y-axis setting from 0 to 175 A. Do the same for

PMOS (right plot) to plot both currents on a 0-175A scale. You can also color the lines and addlabels (Graph > Label > Add).

The final plot should look like as shown below.


16/16


Exercise:

[Note: Details about different types of devices available in the gpdk and their rules are available in

the following location :[ /usr/local/cadence/local/gpdk090_v4.6/docs/gpdk090_DRM.pdf

(/usr/local/cadence/local/gpdk090_v4.6/docs/gpdk090_pdk_referenceManual.pdf ]

Repeat the above simulation with Slow and Fast NMOS by selecting the SS and FF model corners.

Explain the difference in I-V curve.(1)Repeat the above procedure and examine the I-V curve of the High threshold voltage (high

vt) NMOS and PMOS and also the High voltage (2.5 volts) NMOS and PMOS in the

technology library. Explain the difference in I-V curves.

(2)The practical way of measuring the threshold voltage of a MOS transistor is to plot the

(IDS) vs. VGScurve by keeping the transistor in saturation region (VGS=VDS). The slop of

the curve is linear. The interception of the slope of the curve with V GSaxis is taken as the

threshold voltage of the device. Find the threshold voltage of the TT, FF, SS MOS model

corners. Also find the threshold voltage of the high threshold voltage (high vt) and high

voltage (2.5 volts) NMOS transistors.

Report :

All the Reports relating to EEE458 have to be submitted in the form of the standard lab report

template for EEE458. In addition to the requirements in the template answer the following

questions:

(1)Observe the BSIM3v3 MOS models of the different MOS transistors available in the

gpdk090 technology library and try to understand the meaning of different parameters. In a

Table summarize the values of the critical parameters for different types of MOS transistors

and make comment about the difference. (see ../gpdk090_v4.6/models/spectre/gpdk090_mos.scs)

Account, Tool Setup and Study of the Basic I-V Equation of the MOS Transistor

Documents

Transcript of Account, Tool Setup and Study of the Basic I-V Equation of the MOS Transistor