Acceleration of XML Parsing through Prefetching

04/13/2023 Department Of Computer Science and Engg.

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Acceleration of XMLParsing through Prefetching

IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 8, AUGUST 2013Authors: Jie Tang, Student Member, IEEE, Shaoshan Liu, Chen Liu, Member, IEEE, Zhimin Gu, and Jean-Luc Gaudiot, Fellow, IEEE

Presented By :Rohit Deshpande

Mtech CSE 2nd sem130913016


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Contents• Introduction• Motivation• The XML Parsing Process• Prefetching Techniques• Methodology• Performance Analysis of XML Parsing• Memory-Side Acceleration• Implementation Feasibility• A Exemplary Hardware Implementation• Conclusion• Future Work


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Introduction

• Extensible Markup Language (XML) has become a widely adopted standard for data representation and exchange.

• Neutrality, Application independency and Flexibility. • Morgan Stanley’s Financial Services system, spends

40% execution time on processing XML documents.• This paper proposes to accelerate XML parsing from

the memory side.


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Motivation

• XML is widely adopted standard for data representation and exchange.

• Parsing of XML data introduce significant overhead.


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The XML Parsing Process


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• XML data parsing consists of three steps: • Character conversion • Lexical analysis• Syntactic analysis.


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XML Parsing Modeling


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• Event Driven Parser

• Tree-Based Parser


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Prefetching Techniques

• Data prefetching has been proposed as a speculative technique to bridge the speed gap between CPU and memory subsystem.

• Classic Prefetching Techniques:-• Sequential Prefetching• Stride Prefetching• Strem Prefetching• Correlating Prefetching


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Overview of Hardware Prefetching• System Integration of Hardware Prefetcher


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Architecture of Hardware Prefetcher


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Methodology

• XML Parsers and Benchmarks


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• Performance and memory Modeling


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Native versus Managed Execution


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Performance Analysis Of XML Parsing

• Data Flow of XML Parsing


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• Disk Data Loading


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Data Loading from Memory Side

• Data flow starting from main memory, going through each cache layer and finally fetched in to CPU.

• The CPI of speed test is 0.80. • Using the SAX parser, the CPI of standard is

1.27, which introduces 58.75 % of overhead.• Using the DOM parser, the CPI of standard

becomes 1.42, which introduces 77.5% of overhead.


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Memory-Side Acceleration

• Prefetchers


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• Performance Analysis


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• Performance Improvement for SAX Parsing


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• Performance Improvement for DOM Parsing


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Implementation Feasibility

• Bandwidth Utilization


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• Hardware Cost and Energy Consumption


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• Energy Consumption of SAX Parsing


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• Energy Consumption of DOM Parsing


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A Exemplary Hardware Implementation

• Power consumption of the prefetcher on FPGA


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• Hardware Cost and Power Consumption Comparison between eMIPS and Prefetcher


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Performance comparison of L2-only versus two-level prefetcher


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consumption comparison of L2-only versus two-level prefetcher


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Conclusion

• Authors Proposed to make acceleration for XML parsing from memory side by improving its data loading performance.

• Reduce cache misses by up to 80 percent, which translates into up to 20 percent of performance improvement.

• 12.77 percent of energy saving.


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Future Work

• The ultimate goal is to built a many core chip in which one core perform conventional general computing workloads and the other cores do XML parsing and Garbage Collection.


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• W3C, “Document Object Model (DOM) Level 2 Core Specifica-tion,” http://www.w3.org/TR/DOM-Level-2-Core, 2013.

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Acceleration of XML Parsing through Prefetching

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