Accelerating Industrialization and remaining challenges for SiC...
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Accelerating Industrialization and remaining challenges for SiC power devices Thomas NEYER, tech. fellow, SiC Technology
Transcript of Accelerating Industrialization and remaining challenges for SiC...
Accelerating Industrialization and remaining challenges for SiC power devices
Thomas NEYER, tech. fellow, SiC Technology
- Substrate needs
- critical substrate supply
ON’s status chart for SiC
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- Product releasesDiodes:4A – 50A for 650V available as discretes6A – 50A for 1200V an in modules
MosFET:Q1/2018: 80mΩ 1200V in TO247 released – safe launchfrom Q2/2019:20mΩ, 40mΩ, 160mΩ in TO247-3LQ2 same products in D2PAK-7L, TO247-4L
alt. sources under evaluation
Sources secured
SiC 6” Volume ramp-up
Huge Fab capacity available: >10.000 WSPWGlobal Development - 24hrs: Asia/EU/US
12/12/20183
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SIC WEEKLY WAFER STARTSSBD MosFET Modules
Customer projects SiC MosFET - OBC
40kW on-board rapid charger for E-Bus fleet (36 SiC MosFETs/system)
Performance traits:- Excellent current sharing- Good dvdt control (>25V/ns)- Active rectification- zero field fails
Customer projects SiC MosFET – FormulaE
High performance traction system:50A Diodes1200V 160A MosFET (16 in parallel)Overdrive boost (increased VDC, VGS_op)
12/12/20185
SiC performance beats Silicon in volume applications
Traction system level evaluation:
12/12/20186
UpperIGBT
LowerIGBT
UpperDiode
LowerDiode
UpperMOSFET
LowerMOSFET
UpperMOSFET
LowerMOSFET
UpperMOSFET
LowerMOSFET
SW Loss, W 312.29 314.02 54.16 53.80 7.35 7.35 13.68 13.67 8.14 8.13Cond Loss, W 190.45 191.01 38.25 37.74 501.99 501.69 140.42 140.50 178.22 177.93Max Temp, °C 116.52 116.52 81.11 81.11 141.80 141.80 83.73 83.73 87.62 87.62
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Motoring Operation Die Losses (per switch) and Temperature
Cond Loss, W SW Loss, W Max Temp, °C
IGBT/Diode 2X5.6mm2 2X8mm2 4X5.6mm2
2X15mm2 + 2X10mm2
Other system evaluations in ON: 3-phase 10kW OBC/PFC stage
70-140kHz Peak efficiency: ~99% (limited by inductor)
Full-bridge DCDC converter (hard switching)
Vin=400V, Vout=220V, Tj=110 C, 13ARMS
4xNTHL040N65S3F (650V, SuperFETIII): Peak efficiency: 90.6%
4x60mΩ (900V, SiC MosFET): Peak efficiency: 94.0%
SiC MosFET competitive in Si Super Junction applications
Example 900V SiCFET vs 650V SuperJunction FET for LLC
due to low QOSS, QG and Qrr – SiCFET excellent in LLC
12/12/20187
SiC performance beats Silicon IGBTs in the lab
12/12/20188
FS4-1200V 20A vs. ON Semi SiC MOSFET under identical drive conditions
no current tail
faster Turn-on current
fast SiC turn-off600V 500A turn on
VGE= - 5 / +20V
Eon at 25°C
Paralleling of 20mΩ ON Semi SiC MosFETs vs IGBTs
Eoff at 25°C
fast SiC turn-on
Challenges – limiting factor for scaling
Limiting factor for SiC MosFET: Rsp [mΩ.cm2] – channel resistance
Approaches:- Vertical channel (ie Trench) – E shielding challenge- Deposited GOX – intrinsic quality- Low temperature GOX formation - research
12/12/20189
Resistancecomponent
Resistancepercentage
N+ source 0.6 %
Channel 59.0 %
JFET 20.5 %
N Epi 14.3 %
Sub 5.6 %
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Challenges – cooling for small die sizes
Real estate for a 60kW 800V DC inverter switch
in scaleGen 1: 20%
die area
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Power density [W/mm2]
Perfect cooling
singleside
direct cooling
doublesidedirect cooling
Increase SiC Tjmax to 200 C
Ag sinteringGen 2
Gen 3
Challenges - SiC chip in discrete package
Large SiC chips in discrete packages
Temperature cycling (-55C – 150C)
12/12/201811
FEA modeling discovers:
Dependent on chip design, certain locations experience >20 times stress and strain during cycling than Silicon chip
Material Si SiC
Elastic Modulus (Gpa) 130 410
Tensile strength (Mpa) 7000 3440
Hardness (mohs) 6.5 9
CTE (1E-6/C) 2.6 4.5
Overcame problem with patented design and optimized assembly BOM
Typical failure cases for GOX (HTGB – burn-in):
SiC MosFET in its infancy of volume production (compared to Si), Oxide is thinner and intrinsically less clean
Challenges - SiC MosFET in its infancy
Gate oxide integrity for SiC MosFETs and TDDB
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Bias voltage [V]Fa
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In (early) mass production SiC MosFETs need - optimized cleaning, oxidation and anneal- Very low electric field (<3 MV/cm)- tight inline contamination control- highest substrate and Epi quality
Implemented at ON-Semi:
- 100% Epitaxy defect screening- 100% metallic cleaning efficiency- 100% electrical test screening (incl. burn-in)- 100% in-process defect control
Challenges - SiC Epitaxy and defectivity control
Tracing back burn-in failures to substrate defects
Made visible by post Epi scans
12/12/201814
Challenges - unconstrained supply chain
Cost: 30% 30% 15% 12% 13%
12/12/201815
external
within ON Semi
SiC Wafering
Roznov, Czech Republic
ON SiC Vertical Integration
External boule supply
several sources
SiC FE Process
Bucheon, Korea
Thinning, backmetal
Bucheon, Korea
WAT/Sort test
Bucheon, Korea
Assembly, test
Suzhou, China and Seremban, Malaysia
Applications
SiC Epi, Metrology
South Portland, MA, USAand Bucheon, Korea
