Abstract

At Inmotion Technologies, a special method of measuring phase currents is usedin the high power inverters for automotive applications. This method requiresa considerable amount of control logic, currently implemented with discretelogic gates distributed over a number of integrated circuits. In this thesis, thefeasibility of replacing this with programmable logic hardware in one singlepackage is investigated.

The theory behind the current measurement method as well as the operationof the discrete implementation is analysed and described. Requirements ona programmable logic device to implement this was identified and a suitabledevice chosen accordingly. A prototype was developed and tested, interfacingan existing product.

Benefits in terms of cost and size are evaluated as well as required changesto the existing system and the possibility for improvements brought by such achange is analysed. Since the products in question have high requirements onfunctional safety, possible impacts in this regard are discussed.

Sammanfattning

Inmotion Technologies använder en speciell metod för att mäta fasströmmari sina högeffektsväxelriktare för elektrisk motordrift i fordon. Denna metodkräver en ansenlig mängd styrlogik vilken för närvarande är implementerad meddiskreta grindar i ett antal integrerade kretsar. I det här examensarbetet under-söks gångbarheten i att ersätta dessa med programmerbar logik i en enda kapsel.

Teorin bakom mätmetoden liksom funktionaliteten hos den diskreta imple-mentationen analyseras och beskrivs. Krav på en programmerbar integreradkrets indentifierades och en lämplig typ valdes i enlighet med dessa. En proto-typ togs fram och testades som en del av en existerande produkt.

Fördelar i form av kostnad och storlek utvärderas liksom nödvändiga för-ändringar av det existerande systemet samt de potentiella förbättringar en för-ändring av det här slaget kan tänkas medföra. Då produkterna i fråga har högakrav på funktionssäkerhet diskuteras även vilken inverkan teknikbytet kan ha idetta avseende.

i

Acknowledgements

First and foremost I would like to thank Johan Lans for acting as my supervi-sor at Inmotion Technologies, helping with varying technical and non-technicalquestions and supporting me in the project work.

Thanks also to Lars Lindberg for giving me the opportunity to work withthis in the first place and welcoming me as part of the hardware developmentdepartment at Inmotion Technologies.

I would like to thank Kenneth Lindgren for answering questions regarding thecurrent system design as well as helping with the lab set-up, Christer Thomssonfor giving advice on CAD layout and Tobias Ljungström for help with estimatingmounting costs. Thanks also to Ulf Karlsson, Hans Sandblom and everyone elseat Inmotion who has given ideas, suggestions or helped in any other way duringthe project.

I would also like to give a big thanks to Christian Rojas for taking on thetask of being both supervisor and examiner at KTH for this thesis project.

ii

Contents

1 Introduction 11.1 Previous work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 This report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

I Theoretical background 4

2 Current measurement 42.1 Measurement transformer . . . . . . . . . . . . . . . . . . . . . . 42.2 Hall-effect method . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3 Maximized saturation method . . . . . . . . . . . . . . . . . . . . 6

2.3.1 H-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3.2 Saturation detection . . . . . . . . . . . . . . . . . . . . . 72.3.3 Current direction . . . . . . . . . . . . . . . . . . . . . . . 92.3.4 Idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Deadband 113.1 Miller effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 System analysis 134.1 Discrete implementation . . . . . . . . . . . . . . . . . . . . . . . 13

4.1.1 Forward pulse generation . . . . . . . . . . . . . . . . . . 144.1.2 Combinational logic . . . . . . . . . . . . . . . . . . . . . 144.1.3 Direction control . . . . . . . . . . . . . . . . . . . . . . . 164.1.4 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1.5 Boot-up protection . . . . . . . . . . . . . . . . . . . . . . 18

4.2 Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.3 Available power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.4 Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4.1 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.4.2 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.5.1 Control state timing . . . . . . . . . . . . . . . . . . . . . 224.5.2 Direction update . . . . . . . . . . . . . . . . . . . . . . . 224.5.3 Sum current . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Programmable logic devices 245.1 Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1.1 Field Programmable Gate Array (FPGA) . . . . . . . . . 245.1.2 Complex Programmable Logic Device (CPLD) . . . . . . 245.1.3 Cross-over . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . 255.2.1 Synchronous logic . . . . . . . . . . . . . . . . . . . . . . 255.2.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265.2.3 Inputs and outputs . . . . . . . . . . . . . . . . . . . . . . 265.2.4 Power requirements . . . . . . . . . . . . . . . . . . . . . 27

5.3 Additional requirements . . . . . . . . . . . . . . . . . . . . . . . 27

iii

5.3.1 RoHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275.3.2 Automotive classification . . . . . . . . . . . . . . . . . . 285.3.3 ESD and EMC . . . . . . . . . . . . . . . . . . . . . . . . 285.3.4 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285.3.5 Production lifetime . . . . . . . . . . . . . . . . . . . . . . 28

5.4 Pricing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.5 Hardware Description Language . . . . . . . . . . . . . . . . . . . 29

5.5.1 Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 295.5.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Clock generation 316.1 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.2 Pierce oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.3 Oscillator integrated circuit . . . . . . . . . . . . . . . . . . . . . 32

II Practice 34

7 Implementation 347.1 Internal function blocks . . . . . . . . . . . . . . . . . . . . . . . 34

7.1.1 Control state . . . . . . . . . . . . . . . . . . . . . . . . . 347.1.2 Saturation handler . . . . . . . . . . . . . . . . . . . . . . 357.1.3 Phase outputs . . . . . . . . . . . . . . . . . . . . . . . . 367.1.4 Supervision outputs . . . . . . . . . . . . . . . . . . . . . 36

7.2 Additional functionality - deadband control . . . . . . . . . . . . 367.2.1 State transition timer . . . . . . . . . . . . . . . . . . . . 377.2.2 Saturation timer . . . . . . . . . . . . . . . . . . . . . . . 377.2.3 Phase outputs . . . . . . . . . . . . . . . . . . . . . . . . 38

7.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.3.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.4 State encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.4.1 Forming outputs . . . . . . . . . . . . . . . . . . . . . . . 40

7.5 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.5.1 Minimum change . . . . . . . . . . . . . . . . . . . . . . . 417.5.2 Dedicated driver chip . . . . . . . . . . . . . . . . . . . . 417.5.3 Modified discrete driver . . . . . . . . . . . . . . . . . . . 41

8 Simulation 448.1 VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9 Prototype 459.1 Breakout board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.2 Custom PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10 Test setup 4710.1 Logic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.2 Interfacing a drive . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2.1 Control board modifications . . . . . . . . . . . . . . . . . 4710.2.2 State transitions . . . . . . . . . . . . . . . . . . . . . . . 48

iv

10.2.3 Measurement accuracy . . . . . . . . . . . . . . . . . . . . 4810.2.4 Saturation detection . . . . . . . . . . . . . . . . . . . . . 4910.2.5 Power consumption . . . . . . . . . . . . . . . . . . . . . . 4910.2.6 Deadband timing . . . . . . . . . . . . . . . . . . . . . . . 50

11 Test results 5111.1 Response times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5111.2 Measurement accuracy . . . . . . . . . . . . . . . . . . . . . . . . 5611.3 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 5711.4 Deadband timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

III Evaluation 65

12 Evaluation 6512.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12.1.1 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6512.1.2 Gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12.2 Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6512.3 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6612.4 Safety considerations . . . . . . . . . . . . . . . . . . . . . . . . . 67

12.4.1 Metastability and race conditions . . . . . . . . . . . . . . 6712.4.2 Clock oscillation . . . . . . . . . . . . . . . . . . . . . . . 6812.4.3 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . 69

13 Summary 7013.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7013.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.2.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . 7113.2.2 Added functionality . . . . . . . . . . . . . . . . . . . . . 7113.2.3 Programming . . . . . . . . . . . . . . . . . . . . . . . . . 7113.2.4 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

v

Acronyms

ADC analogue-to-digital converter. 13, 24, 48, 49, 57

AEC Automotive Electronics Council. 28

ASIC application specific integrated circuit. 24

BGA ball grid array. 28, 45, 67

CAD computer aided design. 61, 71

CAN controller area network. 48

CMOS complementary metal oxide semiconductor. 31, 47

CPLD complex programmable logic device. 24–26, 36, 45

CPU central processing unit. 24

DAC digital-to-analogue converter. 24

EEPROM electrically erasable programmable read-only memory. 25

EMC electromagnetic compatibility. 28, 71

EMI electromagnetic interference. 26

ESD electrostatic discharge. 28

FIT failure in time. 71

FPGA field programmable gate array. 1, 24–26, 31, 36, 40, 44, 45, 47–49,51–56, 61–69, 71

FSM finite state machine. 13, 25, 34–36

HDL hardware description language. 2, 29, 34

I/O input/output. 20, 21, 27, 36, 41

IBIS input/output buffer information specification. 45

IC integrated circuit. 20, 21, 27, 31, 32, 41, 42, 45, 48, 49, 65, 67, 69, 71

ISR interrupt service routine. 24

JTAG Joint Test Action Group. 29, 45

LDO low dropout regulator. 20, 49

LE logic element. 24, 25, 44, 45, 67

LSB least significant bit. 57

vi

LUT lookup table. 24–26

LVCMOS low voltage CMOS. 20

LVTTL low voltage transistor-transistor logic. 20, 21, 41

MC macrocell. 24–26, 36

MCU microcontroller unit. 13, 14, 17, 20–22, 24, 27, 30, 31, 36–38, 41, 44, 47,48, 53, 54, 68, 69

MEMS microelectromechanical system. 31

MOSFET metal oxide semiconductor field effect transistor. 6, 7, 10–12, 14,17–21, 23, 27, 35–38, 40–42, 44, 47, 61, 65, 68, 70

MSM maximized saturation method. 1, 2, 6, 47

PAL programmable array logic. 36

PCB printed circuit board. 2, 3, 29, 31, 32, 45, 66, 67, 71

PCBA printed circuit board assembly. 36, 65

PIA programmable interconnect array. 25

PLD programmable logic device. 1, 2, 20, 21, 24, 25, 27–30, 32, 34, 36, 38,40–42, 44, 67, 69–71

PLL phase-locked loop. 26, 31, 45, 68

PMSM permanent magnet synchronous machine. 1

PWM pulse-width modulation. 41

RoHS directive on the restriction of the use of certain hazardous substancesin electrical and electronic equipment. 27

SDC Synopsys design constraints. 29

SMD surface mounted device. 46

SRAM static random access memory. 24, 25

TQFP thin quad flat package. 45, 67

VFD variable frequency drive. 1, 5, 13, 21, 47

VHDL very high speed integrated circuit hardware description language. 29,34, 38, 51, 68

vii

1 Introduction

Inmotion Technoligies AB develops and manufactures equipment for the indus-trial vehicle industry. A major part of this are the variable frequency drives(VFDs) that control the permanent magnet synchronous machines (PMSMs) orinduction motors used for propulsion of vehicles.

The current in each phase of the motor needs to be known to control themotor. Therefore, an integral part of the drive is the current measurement.These measurements require consideration when scaling up to applications usinghigh voltages and currents.

One field which has seen a significant increase in recent years is the areaof heavy hybrid vehicles. These motors and drives operate at higher voltagesand currents than their light weight vehicle counterparts. To accommodate this,Inmotion use a special measurement technique in their high voltage drives calledthe maximized saturation method (MSM).

This technique achieves high precision and efficiency at high powers whileavoiding the cost and weight increases other approaches would bring. The draw-back is the requirement for more complex control logic.

1.1 Previous work

One of the first to propose this method of current measurements was the Swisscompany Socapel SA [1], later acquired by what is now Inmotion. This wastested for higher currents by Inmotion under the company name of Atlas CopcoControls [2].

Two master’s theses have been written on the subject of this method. Thefirst one focused on the electromagnetic properties of the measurement trans-former coils [3]. The other worked on the development of the discrete logiccontroller [4]. Both were performed at Inmotion although the company nameat the time was Danaher Motion and Kollmorgen respectively.

1.2 This report

With increased safety requirements and a demand for drives controlling morethan one three-phase motor, the size of the control logic in these drives hasgrown to a considerable size. A more modern and compact solution is thereforedesired. This report investigates an approach towards this by moving the currentmeasurement control logic from an implementation consisting of many discretecomponents into a single programmable logic device (PLD).

While programmable logic has been around for a while, most applicationscan be divided into two groups. One is the replacement of a few very simplelogic functions with one low density PLD. The other, which has seen a bigincrease in usage over the past decade or so, is the utilisation of high densityPLD for reconfigurable hardware acceleration in data intensive computing andcommunication applications.

The application in this report does not quite fit into either of these twogroups. The functionality is more complex than a few small combinatorial logicnets or a shift register but not nearly on the level where developers often lookinto field programmable gate arrays (FPGAs).

1

Other factors making the application atypical is the close connection to thephysical world and the need for safe and reliable operation while at the sametime being cost effective. With the intention of using this in series productioninstead of jellybean parts renders it is much more cost sensitive than for instancea hardware simulation test bed.

While this method for measuring current is known from before and havebeen used by Inmotion in a few products, it is still fairly uncommon and farfrom an industry standard. Despite being described in previous theses and otherreports, it has seen several changes over the years and may have more to come.For this reason, the flexibility in a programmable hardware has the potentialto be very advantageous. It also makes it an interesting application from atechnical standpoint.

The work going into this report started with an analysis of the measurementmethod in its present implementation as well as the workings of PLDs in orderto break down the intended application into requirements for selecting a device.Limitations arising from the new type of implementation were also identified.The PLD market was investigated and a suitable device chosen.

The control for the maximized saturation method based on the existinginput signals was then developed in several steps. The functionality was brokendown into necessary code blocks which were written, simulated and tested inevaluation hardware.

Possibilities for extended functionality made possible by the intended newimplementation were also investigated and an alternate setup was developed. Acustom printed circuit board (PCB) was designed to support both the simpleand the extended version.

Test were performed on a product in production to set a baseline. Thecustom hardware was assembled and necessary modifications to the existinghardware were performed to interface the custom board. The custom boardwas tested as part of the existing product and performance was compared.

The economic effects of such a change for a production part were estimatedand things to consider both in a more general sense and for this applicationin particular were summarised. Altogether this report tries to investigate thepossible impact of moving to programmable logic from a wide perspective inapplications where it might not be the first choice to come to mind.

1.2.1 Structure

This report is divided into three major parts. Part one explains the theoreti-cal background. Theory for current measurements and the motivation for thismethod is given in Section 2. Section 3 gives a background into why an extendedfunctionality in the logic with a controllable deadband could be an improvementwhen controlling the magnetic flux in an inductor with an H-bridge. Section 4analyses how the circuits in the existing implementation work. Section 5 givesa brief summary of different types of programmable logic devices and the re-quirements for choosing one for this particular application. Section 6 discussesoptions for generating a necessary clock signal.

Part two is about implementing this functionality with a PLD. Section 7 de-scribes how the hardware description language (HDL) code setup is structured.Simulation and development of the prototype board is described in Sections 8

2

and 9 respectively. Section 10 explains the test setup used for evaluating it andthe results are given i Section 11.

Part three evaluates the results from the practical tests as well as other fac-tors affecting the choice of implementation such as economics and PCB area.In Section 13 conclusions are drawn, things to consider when moving to pro-grammable logic discussed and a few topics to look further into are mentioned.

3

Part I

Theoretical background

2 Current measurement

A common and simple way of measuring currents is by using a shunt resistor.The current is passed through a low valued resistor and the voltage over theresistor is measured directly. The current can then be calculated through Ohm’slaw, I = U/R.

One big disadvantage of this method is that the voltage sensing electronicsneed to be directly connected to the conductor through which the current isflowing, in this case the energized motor cables. Even though the measuredvoltage differential over the resistance is low, the common mode voltage swingcan be very high, putting high requirements on the electronics. The electricalconnection is also undesirable from a safety standpoint as a component failuremay provide a current path to other parts of the circuit or vehicle. To solve thisproblem, some sort of galvanic isolation is required.

2.1 Measurement transformer

A common way of achieving galvanic isolation is by using a measurement trans-former, feeding the current to be measured through the primary winding andconnecting the shunt resistor to the secondary. This also enables the current tobe scaled up or down according to the turns ratio of the transformer coils.

In the case of an ideal transformer, where there are no leakage inductances orcore losses and the permeability is infinite, the relationship between the magneticfield strength H, current i and number of turns N as given by Amperes law canbe written as (2.1) if the field is also homogeneous.

∮

H · dl =

∫

A

J · dA = Ni (2.1)

The magnetic field is the same for the primary and secondary windings asthey are wound on the same core. According to Faraday’s law (2.2) the voltageu(t) over a coil is equal to the time derivative of the linked flux ψ, or the flux φthrough each individual turn times the number of turns N , so the relationshipbetween current and voltage in the coils is constant, giving (2.3).

u(t) =dψ

dt= N

dφ

dt(2.2)

u1N1

=dφ

dt=u2N2

(2.3)

The magnetic energy W stored in an inductor is given by (2.4). L is theinductance as given in (2.5) where l is the magnetic length, A is the crosssectional area of the core and µ is the permeability as in (2.6) [5][6]. If the crosssectional area of the coil is small relative to its diameter, the assumption that themagnetic field is homogeneous over the cross section is a good approximation [7].Combining these results with (2.1) gives the relationship (2.7).

4

W =1

2Li2 (2.4)

L =N2

lµA

(2.5)

B = µH = µrµ0H (2.6)

W =1

2µH2Al (2.7)

Consequently the stored magnetic energy depends on the volume of thecore, its permeability and the H-field which in turn depends on the current andnumber of turns in the coil. Note that µr is not a constant but has a non-linearrelationship with B for other materials than vacuum.

B

H

Figure 2.1: Hysteresis curve for a ferromagnetic material.

For ferromagnetic materials the value of µr is very high, on the order of 50000for the core used here, and very little current is needed to create a big change inthe magnetic flux density B. As the B-field approaches a high enough level, thevalue of µr tapers off towards one as depicted in Figure 2.1. When this pointhas been reached, an increase in primary current will not change the magneticflux noticeably and thus will not be seen at the secondary. Measurement valuescalculated with the nominal value of µr in the linear region will therefore nolonger be valid.

Since a VFD naturally must be able to operate at very low frequenciesand thus long periods while handling large currents, a normal measurementtransformer would have to be very large in order not to saturate. This becomesimpractical and expensive.

Another important effect of saturation is that since the value of µ in (2.5)approaches one, the inductance is significantly lowered.

5

2.2 Hall-effect method

Another method is to use a transformer which has an air gap with a hall effectsensor in it. The Hall-effect sensor measures the B-field in the core as a voltagedirectly, using the Hall effect.

As current passes through a magnetic field, the Lorentz force will act on theelectrons forcing them to one side of the conductor. This generates a voltageperpendicular to both the current and the magnetic field which can be measureddirectly.

Either this reading is used directly, or it is used in a control loop applyinga current to a secondary control winding. The current in the control windingis adjusted to cancel the magnetic field induced by the primary. The requiredcurrent for cancellation is then measured using a shunt resistor. This currentand voltage source can operate at a lower level than the measured currentsaccording to the turns ratio of the transformer and it also benefits from thegalvanic isolation.

The air gap reduces the risk of saturating the core and in the closed loopconfiguration the risk of saturation is avoided even further giving the opportu-nity to use a smaller transformer core. However, power is required continuouslyto regulate the field in the core.

The main disadvantage of these methods is the limited accuracy coupled withthe relatively high cost of the Hall-effect sensors. In high power applicationssuch as in the drives for high voltage motors in hybrid vehicles it is necessaryto be able to measure high currents with good precision. For this reason, atInmotion, the use of Hall-effect sensor based current measurement is limited tolow power drives.

2.3 Maximized saturation method

At Inmotion Technologies, another measurement technique has been used in acouple of motor drives. This method borrows some of the elements of the Hallmethods. It utilises the idea of applying a voltage to the secondary coil butinstead of controlling the flux to a minimum at all times, the core is only drivenout of saturation right before sampling. This reduces the mean power requiredto control the flux density compared to the closed loop Hall-effect method anddoes not require an air gap.

The core is allowed to saturate in between measurements, hence the name.This lowers the inductance seen at the primary coil and also reduces the currentgenerated in the secondary as the derivative of the flux is lowered in (2.2). Theenergy dissipated as heat in the shunt resistors is therefore lowered in betweenmeasurements.

The material used for the magnetic cores in this system was originally aproprietary cobalt alloy with a very steep hysteresis curve and a sharp transitioninto saturation at around 0.58 T [8] which makes it suitable for this application.Later on this has been changed to cores from another manufacturer with similarmagnetic properties.

2.3.1 H-bridge

To drive the current in the secondary winding, an H-bridge is used. This consistsof four metal oxide semiconductor field effect transistors (MOSFETs) in the

6

Usupply

RS1 RS2

P+

N+

P–

N–

Figure 2.2: H-bridge controlling the secondary current.

configuration shown in Figure 2.2. This allows current from the power supplyto be passed in either direction of the coil as well as let the coil be either openor short circuited through the shunt resistors to ground. The H-bridge is driveninto four different states as follows, depicted in Figures 2.3 through 2.5.

Forward One of the diagonal pairs of MOSFETs, either P+ and N– or P– andN+ turns on, driving current from the supply voltage through the secondarycoil. Which of the pairs is determined by the flux in the core. The currentdirection is applied to counteract the field induced by the primary coil, i.e., themotor current.

Back This is the reverse of the Forward state. The other diagonal pair isturned on, inducing a field in the core with the same direction as the one inducedby the primary.

Measure In this state, N+ and N– are conducting. This is effectively short-circuiting the coil through the two shunt resistors.

Idle The idle state turns off all the MOSFETs. The secondary coil is open-circuited except for the body diodes of the MOSFETs. These will however onlyconduct current if the voltage over coil is greater than the supply voltage plusthe forward voltages of the two body diodes.

2.3.2 Saturation detection

As the saturation results in a significant reduction of the coil inductance, thecurrent in the coil will increase rapidly. It is important to detect this in order toswitch off the power and limit the current rush. This is done with a comparator,

7

Forward.

On

Off

Off

On

i

i

Back.

Off

On

On

Off

i

i

Measure.

Off

On

Off

On

i

Idle.

Off

Off

Off

Off

Figure 2.3: Nominal secondary current direction in the different states.

comparing the voltage over the shunt resistors to a reference. When too biga current is detected, the core is assumed to be saturated and the H-bridgeswitches into the measurement state. If this is not done quickly enough, thepower consumption will increase significantly and excessive stress is put on thecomponents.

2.3.3 Current direction

The earlier methods [1] and [2] always saturate the core in one direction duringthe forward pulse independent of the actual current direction in the motor phase.Then the Back -pulse drives it back into the linear region. This is not the mostefficient use of power since one measurement may require up to a full loop ofthe hysteresis curve.

This is improved upon by taking the direction of the last measurement intoaccount in the implementations [3] and [4]. This way the forward -pulse directionshould never have to drive the core from one saturated state to the other andpower is saved, at the expense of added circuit complexity.

This is done in slightly different ways. The implementation described byLindgren [3] assumes the core to be saturated at the start of every measurementcycle. A forward pulse is applied to drive the core out of saturation. Themeasurement state is entered and a sample is taken. Then a back pulse is appliedto drive the core back into saturation. This approach causes some samples to

8

B

H

Forward

Back

Measure

Figure 2.4: Normal operation.

B

H

Forward

Back

Measure

Figure 2.5: Saturation detected.

be invalid as the assumption of a saturated core before the desaturation is notvalid when the primary current has changed sign since the last measurement.

The more recent implementation described by Wisten [4] on the other handalways applies both the forward and the back pulse before doing the measure-ment. This back pulse is shorter than the forward pulse in order not to drivethe core back into saturation, see Figure 2.4, but long enough to drive the coreback into the linear region in the case of the forward pulse being interrupted bysaturation detection, see Figure 2.5. If that happens, this implies that the signof the primary current has changed and a flip-flop that stores the informationon current direction is toggled. The following measurement cycle will have theopposite direction for the states forward and back.

2.3.4 Idle state

Another difference between the two implementations [3] and [4] is the choiceof state in between measurements. While [3] uses the measurement state toreduce the drift of the magnetic flux, [4] opens all the MOSFETs to insteadlet the flux drift easily and reduce power loss in the shunt resistors in betweenmeasurements. The latter method is the one currently used in both regards.

9

3 Deadband

When using MOSFETs as switches, the current is not immediately turned onor off with the control signal. There is a slight delay and the channel currentiDS changes with the charge or discharge of the gate capacitance.

When using them in a half bridge configuration there is a need to delay theturn-on of one a while after the turn-off of the other. This is called deadband asthere is a time during the transition from the high to low MOSFET conductingor vice versa when none of them are turned on. Without this feature the halfbridge would experience what is called shoot-through, i.e., both MOSFETs areconducting simultaneously, shorting the supply to ground.

The transition times are longer for P-channel than N-channel MOSFETsince electrons have higher mobility than holes [9]. They also generally have ahigher input capacitance making the transition slower as well as higher channelresistance, RDS . For this reason many applications use an N-channel MOSFETfor the high side as well as the low side. This does however require a gatevoltage higher than the supply for the high side to turn it on efficiently. Thiscan be solved with a bootstrap capacitor which is charged up when the low sideis conducting and then supplies the high side gate driver when the low side isturned off.

This type of solution has the limitation that the low side has to be turnedon occasionally to charge the capacitor. A duty cycle of 100% is therefore notpossible. For this application this is not a problem since the measure state isentered every cycle with both low sides turned on but it is using a rather lowswitching frequency with a long delay between the measure state and the nextforward, requiring the bootstrap capacitor to hold its charge for a long time.

Bootstrapping also requires a bit more complicated circuitry and, since theMOSFETs used here have a low RDS of around 20 mΩ even for the P-channels,it is not used here.

3.1 Miller effect

Usupply

Coil

P

N

Figure 3.1: Miller capacitance.

10

Another consideration when swithing the MOSFETs is the Miller effect. Alltransistors have parasitic capacitances between the leads. These are generallyvery small, on the order of a few pF. The capacitance from gate to drain in aninverting amplifier is however multiplied by the amplification plus one and thusappears to be significantly larger [9].

When switching one MOSFET of a half bridge, the voltage change at thedrain is coupled through this capacitance to the gate of the other MOSFET andadds to its gate voltage. If the turn-on of one MOSFET occurs before the gatevoltage of the other has discharged to a low enough level, this voltage spike canturn on the MOSFET and cause shoot-through.

To mitigate both of these problems, the turn-on of one MOSFET in a halfbride is delayed some time after the turn-off of the other. This lets the firstgate capacitance discharge to a safe voltage level and is called a deadband sincethere is a time in each switching occurrence where none of the MOSFETs areturned on.

11

4 System analysis

The VFD consists of several modules for different tasks such as power supply,communication, supervision, current measurement, etc. All these modules aregoverned by a main microcontroller unit (MCU) as well as a supervision MCU.

This thesis concerns the current measurement unit. It receives two signalsfrom the main MCU: Enable (ENL) and Back (BCK). Based on these pulses,the current measurement module should return valid voltages representative ofthe motor currents to the analogue-to-digital converters (ADCs) at the correcttime. The voltages are sampled at a frequency of 4 kHz, i.e., the pulses startwith an interval of 250 µs. The ENL-pulse has a duration of around 20 µs. TheBCK-pulse starts 10 µs into the ENL and lasts for 5 µs. The exact values maybe reconfigured but the resulting duty cycle for ENL lies around 8 %.

4.1 Discrete implementation

The logic in place today for controlling the H-bridge from these pulses is madeup of a mix of analogue and digital circuits with an emphasis on the latter.Together they implement the finite state machine (FSM) depicted in Figure 4.1for each phase. These circuits can be divided into a couple of blocks as follows,with prevalent signals summarized in Table 4.1.

offstart idle

frwd

back

meas

measmeas

HDE=1

ENL=1

SATF=0

BCK=1 BCK=1

BCK=0 SATB=0

BCK=0

ENL=0

Figure 4.1: State diagram.

Signal Full name OriginENL Enable Main MCUBCK Back Main MCUSAT Saturation ComparatorsFWD Forward Figure 4.2DSC Driver state control Figure 4.4SDL Saturation detection latch Figure 4.4DIR Direction Figure 4.5HDE High-side driver enable Figure 4.7

Table 4.1: Summary of signals.

12

4.1.1 Forward pulse generation

R

SBCK

Q

ENL

ENL

FWD

Figure 4.2: Logic to produce the Forward -pulse.

The two pulses from the MCU are fed to the network of NOR-gates shownin Figure 4.2. The leftmost is wired up as an inverter giving the output of ENL.The centre two that feed back into each other form an active-high SR-latchwith BCK connected to Set and ENL to Reset. The output of this latch, Q, iscombined with ENL in the rightmost NOR-gate to form the forward -pulse.

-5 0 5 10 15 20 t[µs]

ENL

BCK = S

ENL = R

Q

FWD

Figure 4.3: Signals involved in the Forward -generation.

The signal sequence is shown in Figure 4.3. At the start of every measure-ment cycle, Q is low. When ENL goes high, its inverse ENL goes low. Thelatch retains its low value and FWD goes high. At the rising edge of BCK, thelatch is set and FWD goes low. When BCK falls back down, Q remains highuntil the falling edge of ENL where Q is reset. FWD is kept low until the nextenable-pulse.

4.1.2 Combinational logic

The currently available signals: ENL, FWD and BCK along with the saturationsignals as well as the signal DIR and its inverse, which keep track of the cur-rent direction in the phase, are combined in the circuit depicted in Figure 4.4.The output signal DSCU−

is fed to the MOSFET-driver circuitry described inSection 4.1.4.

13

DSCU−

G1

G2

G3

DIR

FWD

DIR

BCK

ENL = S

SATU+ = R

SDLU−

Figure 4.4: Signals to drivers.

The input connections in Figure 4.4 are for the negative terminal of the coilof phase U in motor 1. For the positive counterpart DSCU+, the DIR and DIRsignals are interchanged and the SAT+ signal is changed to SAT− coming fromthe other comparator. The other phases have equivalent combinational circuits.

The lower part is once again an SR-latch but this time active-low. At theend of a measurement cycle, when ENL goes low, the latch is set giving SDLa high level. If the comparator output SAT+ goes low due to core saturation,SDL is reset to a low value for the rest of the enable pulse. The value of DSCU−

is given by equation (4.1) and presented in Table 4.2.

DSCU−= SDL ·G3

G3 = G1 ·G2

G1 = DIR · FWD

G2 = DIR · BCK

=⇒

=⇒ DSCU−= SDL ·DIR · FWD ·DIR · BCK =

= SDL + (DIR + FWD) · (DIR + BCK) =

= SDL +DIR ·DIR︸ ︷︷ ︸

=0

+DIR · BCK+ FWD ·DIR + FWD · BCK

(4.1)

From (4.1) follows that whenever SDL is low, DSC is high. The results forthe other signals are shown in Table 4.2. FWD and BCK are mutually exclusiveso the only valid combinations giving a low value on DSCU−

are FWD ·DIRand BCK ·DIR. For the positive side half-bride, the signs of DIR and DIR areinterchanged.

14

SDL DIR FWD BCK DSCU−

0 X X X 11 0 0 0 11 0 0 1 11 0 1 0 0

(1 0 1 1 0)1 1 0 0 11 1 0 1 01 1 1 0 1

(1 1 1 1 0)

Table 4.2: Truth table for DSCU−.

4.1.3 Direction control

The outputs of the comparators for saturation detection are normally pulledhigh by pull-up resistors. When they are triggered by the shunt resistor voltageexceeding the reference voltage, their output is pulled low resetting the latchmarked SDL in Figure 4.4.

The latched comparator signals SDL of both sides of the coil are connectedto an AND-gate. The output of this gate is connected to the clock input of aD-type flip-flop as shown in Figure 4.5. The output from the flip-flop is thesignal DIR and the complementary is DIR. The complementary output is alsofed into the flip-flops data input.

D Q

CLK QSDL+

SDL−

DIR

DIR

Figure 4.5: Direction memory.

If either of the comparators detects saturation, their respective latch will bereset. The AND-gate connected to the clock input will go low and stay low untilthe latch is once again set by the falling edge of the Enable-pulse. This risingedge will toggle the state of the flip-flop and the values of DIR and DIR.

The use of two different comparators and latches makes it possible to inhibitthe low signal of DSC on one side due to saturation while the other still oper-ates normally. If saturation is detected during the forward pulse, for instancewhen DSCU−

is low, this signal will go high at saturation. During the followingBCK pulse, DSCU+ can still go low unless it is also interrupted by saturation.Normally saturation will only occur during the Forward pulse but having pro-tection against it during the Back pulse is still preferable and which half bridgeis active during forward depends on DIR.

15

4.1.4 Gate drivers

Driving the H-bridge is a bit more complicated than assigning logic levels to thegates of the MOSFETs. The drain-to-source resistance and switching speed ofthe MOSFETs depend on the applied gate-to-source voltage. Higher voltagesresult in quicker switching. At the same time the MOSFETs cannot withstandthe full 27 V of the supply from gate to source but is limited to ± 16 V for theN-channel and ± 20 V for the P-channel. These voltages are also referenceddifferently with the source connected to ground and supply respectively.

To accomodate this, the circuit depicted in Figure 4.6 changes the voltageto appropriate levels and also provides some logic functionality.

DSC

ENL

HDE

Usupply

T1

Coil

Meas

R1

R8

R4

R3

R2

R5

R7C1

R6

RS2

Figure 4.6: MOSFETs and driver for one coil terminal of one phase.

This block takes the inputs ENL from the MCU and DSC from the circuit inFigure 4.4 and controls the power MOSFETs in order to connect one terminalof the secondary coil to either the supply (+, 27V), through the shunt resistorsto ground (–) or none (Z) according to Table 4.3.

It is worth noting that DSC only goes low during the forward or back pulsewhich in turn only occurs during an ongoing enable. The state where both DSCand ENL are low will therefore never occur. The possible signal combinations

16

ENL DSC Coil(0 0 +)0 1 Z1 0 +1 1 –

Table 4.3: Coil state according to signals.

and the corresponding states of the MOSFETs are displayed in Table 4.4.

State ENL DSC+ DSC−

P+ N+ P– N–Idle 0 1 1 off off off offForward 1 0 1 on off off onBack 1 1 0 off on on offMeasure 1 1 1 off on off on

Table 4.4: MOSFET control signals.

This circuitry includes a deadband feature, making sure that there is a delaybetween turning off the P-channel and turning on the N-channel.

When ENL and DSC are high, the low side gate is charged from the NAND-gate through R5 and R6. The MOSFET connected to R7 is turned off. Thecapacitor to ground increases the turn-on time of the low side power-MOSFET.

When DSC goes low, the MOSFET opens, allowing a quick discharge of thegate and capacitor on the low side. Current flows through both R7 via theMOSFET and through R5 via the NAND-gate to ground.

4.1.5 Boot-up protection

An NPN-transistor, apart from a transistor, also forms a diode which can con-duct current from the base to the collector. This is generally not a problem asthe collector potential is normally higher than the base. During system start-up however there is a possibility that the 27 V supply rises slower than the5 V. Current can then pass through both the NPN-transistors in the circuitup to the 27 V supply while the gate of the P-channel MOSFET is still low.The voltage over the P-channel MOSFET can cause it to turn on and result inshoot-through.

To mitigate this problem there is a resistor R8 in this path. More impor-tantly, the input HDE is kept low initially to avoid spurious signals turning onthe P-channels at start-up. When the system has booted, this input is kept at5 V unless the supply voltage falls below a certain threshold.

Figure 4.7 displays the circuit controlling this. It compares an input signalof 0−3.3 V to a reference voltage. The comparator has an open collector outputwhich is pulled up to 5V by R9. The output of the circuit is pulled to groundby R11. The PNP-transistor reduces the output impedance and is turned onwhen the comparator output goes low.

Apart from stepping up the signal voltage from 3.3 to 5 V this circuit in-creases stability of the signals during boot-up. The comparator output is moredeterministic than logic gates before the supply reaches its nominal value.

17

−

+

URef

R13

C2

Input

R10

5V

R9

R11

R12

C4C3

HDE

Figure 4.7: High-side driver enable circuit.

4.2 Delays

One of the most critical timing factors in the application is the time it takesfrom the core going into saturation until the forward -pulse is turned off. If fullpower is continuously applied after saturation, the MOSFETs will be destroyedin a couple of microseconds.

Comparators When the voltage over the shunt resistor exceeds the reference,the comparator output goes from high to low in about 300 ns.

Combinational logic From the comparator to the signal DSC, there arethree gates with a worst case propagation delay of 9, 9 and 17 ns respectivelyresulting in 35 ns in total.

When changing state, for instance going from forward to back, the path is abit longer with a worst case delay of 59.5 ns.

Driver circuit The driver circuit has by design different state transition timesfor different directions. When DSC goes from high to low, the low side startsto turn off after around 40 ns and after around 80 ns the coil terminal haslevelled out at a voltage in between ground and supply. The coil terminal isbasically floating at this point. 105 ns after the falling edge of DSC, the P-channel starts conducting and the coil is connected to the supply after around220 ns. Figure 4.8 depicts these transitions together with the voltages at thegates. For increased visibility the coil voltage has been divided by five and theP-gate voltage has been shifted down by 22 V.

When the signal DSC goes from low to high, the coil starts to drop from thesupply voltage after 40 ns levels out midway after 70 ns. After 160 ns it startsto drop towards ground and reaches a low level after around 250 ns which canbe seen in Figure 4.9.

At saturation, the forward state transitions into measure so the latter caseapplies. In the simulation, the propagation delay of the logic gates in the driver

18

circuit was omitted so only the rise times were included. This could delay theturn-off of the N-channel by up to 9 ns and the turn-on by 20 ns more.

The actual curves would be largely affected by the big inductive load andthe transformed current during operation. Simulation was done with a mainlyresistive load since the sought after result was the behaviour of the driver it-self. Furthermore, simulation was severely slowed down by the induced currentthrough the body diodes generating singular values in the model of the power-MOSFETs when including a large inductance.

4.3 Available power

The power board supplies a lot of different voltages around the system. Thecurrent measurement board uses a couple of them in the current implementation.The H-bridge and its drivers are fed by 27 V. The comparators use a 15 V source.Most of the discrete logic use a 5 V source while the NOR-gates generating theforward -pulse use 3.3 V power.

The 3.3 V supply is generated by a low dropout regulator (LDO) capable ofdelivering 800 mA of current. This supply is in turn fed 5 V from another LDOcapable of delivering 1 A.

4.4 Interfacing

As the main objective of this project is to investigate a change from the discretelogic into programmable logic it is reasonable to try and leave as much of theother circuitry unchanged as a first approach. If only the circuitry taking thepulses from the MCU and the comparators to produce the signal DSC were tobe changed, this would result in replacing the integrated circuit (IC) packagesin Table 4.5. This amount of circuits could possibly on its own motivate amigration into programmable logic. This section explains the interfacing of thiscircuitry towards the rest of the system.

Function Single drive Dual drive4×2-NAND 9 184×2-NOR 1 22-AND 3 6D-flip-flop 3 6Total 16 32

Table 4.5: Replaceable logic chips when maintaining drivers and comparators.

4.4.1 Inputs

The MCU runs from the the 3.3 V supply. The two input pulses ENL and BCKit sends to the current measurement circuit are therefore at that level. Thelogic gates they are fed into work from a 5 V supply but they accept 3.3 V lowvoltage transistor-transistor logic (LVTTL) or low voltage CMOS (LVCMOS)levels as input.

The comparators for saturation detection have an open collector outputpulled up to 5 V by a resistor each. Most modern PLDs support 3.3 V in-put/output (I/O) logic levels but some are tolerant to 5 V inputs. If this is not

19

the case then the pull-up configuration can still be adapted to use 3.3 V insteadrather easily.

The comparators used support tying the outputs together for logic ANDfunctionality. This implies that the input signals to the circuit could be reducedto one rather than two saturation signals per phase, plus the two signals fromthe MCU.

4.4.2 Outputs

The MOSFET-drivers still include one NAND-package per phase, two gates perhalf-bridge in the low-side driver. While there is a MOSFET sinking the gateof the N-channel to turn it off, the logic IC in place provides the 5V to turn iton. The 3.3 V output of most PLDs is not enough to achieve good and robustperformance in driving the N-channel MOSFET gates high. The NAND-gateswould serve the added purpose of logic level shifters.

Removing these NAND-gates would also require supplying the complemen-tary signal of DSC from the PLD to control the signal-MOSFET if the drivercircuitry is otherwise left unaltered. In the current configuration, the combina-tional logic supplies the signal DSC while ENL can be routed directly from theMCU.

The high-side driver, i.e., the circuitry controlling the P-channel power-MOSFET, is also interfaced using the signal DSC. When this goes low, theNPN-transistor turns on. The gate outputting DSC must therefore be able tosink the current from the emitter, which in the current configuration is around11 mA.

For this reason, another type of NAND-gate is used here than for most otherplaces where a 2-input NAND gate is required. This type is slower and doesnot accept LVTTL input levels but it has a higher drive strength. Althoughthe rated absolute maximum output current is the same for both types, theequivalent output impedance of this type is lower and thus can maintain thelow voltage at the transistor emitter more easily.

For many PLDs this would be a limiting factor. However, if the PLD hasmore I/O ports than the minimum requirement, several outputs could be usedtogether in order to increase the drive strength.

Another consideration in interfacing the high-side driver is that the base ofthe NPN-transistor is now tied to 5 V (HDE). When DSC reaches this value,it turns the transistor off. This voltage may not exceed the maximum outputlevel of the PLD. If necessary, this can be changed by modifying the supply andR9 of the circuit in Figure 4.7.

Another solution to both of these problems would be to replace the wholecircuitry with a gate driver IC. An added benefit is the more explicit control ofthe deadband. This would however require four signals to the driver circuitryper phase instead of the present two per phase plus the global ENL, which iscommon to all the phases.

4.5 Supervision

The VFD contains a supervision MCU which aids the main MCU in performinga couple of periodic controls to ensure that the system operates as intended.

20

4.5.1 Control state timing

One such check is that the pulse lengths of ENL, BCK and FWD are monitored.This is to verify that the samples are taken at the correct time and thus at thecorrect point of the hysteresis curve and not in or close to saturation.

4.5.2 Direction update

Periodically the MCU puts out a FWD pulse of excessive length to deliberatelyloop through the whole hysteresis curve and trigger the saturation detection.This is done to verify that the direction signal, DIR, toggles. As mentioned thisconsumes some extra power, hence it is not done for every sample.

4.5.3 Sum current

The sum of the currents in each phase of one motor should add up to zero. Thisproperty has earlier been used to determine the current of the third phase whileonly actually measuring two.

To increase redundancy and detect errors, the third phase measurement isnow also performed. If the calculated and measured values do not match, thisimplies that something is faulty and the system shall invoke a safe state.

21

0 100 200 300 400 500

0

1

2

3

4

5

Time [ns]

Voltage[V

]

Simulated voltages with resistive load

DSCP-gate –22N-gate

Output/5

Figure 4.8: Falling edge of DSC, signaling the gate driver circuitry to turn offthe low side and turn on the high side MOSFET.

0 100 200 300 400 500

0

1

2

3

4

5

Time [ns]

Voltage[V

]

Simulated voltages with resistive load

DSCP-gate –22N-gate

Output/5

Figure 4.9: Rising edge of DSC, turning off the high side and turning on thelow side.

22

5 Programmable logic devices

A popular choice when trying to increase flexibility and minimizing parts countin electronic systems it to integrate functionality into a central processing unit(CPU) or an MCU. These are generic and multi purpose and are easy towrite software to in order to create the desired functionality. Because of theirwidespread use, some have been more adapted towards certain ranges of useand incorporate hardware such as comparators or ADCs and digital-to-analogueconverters (DACs).

The big drawback is that all actions are performed sequentially. While thestate machine described here could be implemented in an MCU, it would takeseveral clock cycles to change state or output according to the current input.The reaction times can be improved by using interrupt branching but still onlyone interrupt service routine (ISR) can be executed at any one point in time, oneline of code at a time. For logic hardware the reaction times can theoretically bereduced to one clock cycle since all the inputs, outputs and intermediate logicwork in parallel [10].

PLDs are another type of customizable chips where the written code definesthe physical layout of the hardware rather than the actions taken in the softwareof a processor.

5.1 Architectures

PLDs come in a range of different sizes, from small ones replacing a few logicgates to chips that contain millions. The smallest ones are too simple to beuseful in this project but the medium to high capacity PLDs can be dividedinto the categories below.

5.1.1 Field Programmable Gate Array (FPGA)

This type of PLD was first intended for prototyping of application specific in-tegrated circuits (ASICs) at lower clock speeds during development. Nowadaysit is a common choice for high density PLDs and offers high flexibility withoutthe big overhead cost of producing an ASIC.

The main building block or logic element (LE) generally consists of a coupleof 3- or 4-input lookup tables (LUTs) and a D-type flip-flop. A 4-input LUTis basically a multiplexer with 16 inputs, all pre-programmed to a value. Theoutput can thus implement an arbitrary logic function of the four address inputs.These LEs are interconnected in a big configurable matrix.

FPGAs are common for large scale, data intensive logic functions such assignal processing or as a customizable CPU core.

The configuration is generally stored in a static random access memory(SRAM). This is a volatile memory type and needs to be loaded at startupfrom an external non-volatile memory which adds a bit of extra circuitry [11].

5.1.2 Complex Programmable Logic Device (CPLD)

For small to medium sized applications the use of a CPLD instead is rather com-mon. These consist of a number of macrocells (MCs) which are interconnectedsimilarly to the LEs of the FPGA.

23

The MC in itself has the structure of a small PLD which forms a sum-of-products logic output through a programmable interconnect array (PIA) ofgates. A CPLD has a lower number of MCs than an equivalent FPGA hasLEs but the MC supports wider inputs. As such it can often contain a biggersubset of the total functionality with less routing. Because of this CPLDs areconsidered more deterministic in terms of timing.

The configuration of a CPLD is stored in electrically erasable programmableread-only memory (EEPROM) which is non-volatile and retains its data whenpower is removed. CPLDs are often used for complex FSMs and counters.

5.1.3 Cross-over

The distinction between low density FPGAs and high density CPLDs is gettingblurred as manufacturers try to bridge the gap between the architectures andmake the selection easier in cases where the choice is not obvious. Some smallerFPGAs are equipped with on chip flash-based non-volatile configuration memorywhich is automatically loaded into the SRAM at power up. These devices aresometimes labelled as CPLDs even though their underlying architecture is basedon LUTs. Different vendors may sort the same device under different categoriessince they may be suitable in situations where CPLDs have traditionally beenused while they are structurally closer to FPGAs.

5.2 Functional requirements

Choosing an appropriate device for the application requires considering a coupleof aspects other than just the number of logic gates it can replace for optimalresults. The requirements for operation of programmable logic have a couple ofdifferences from discrete logic.

5.2.1 Synchronous logic

The discrete implementation is an asynchronous design without any clock signalgoverning state transitions. The flip-flop uses a clock input but that signalin itself is generated asynchronously from the outputs of other circuits. Thecombinational logic feeds back to its own inputs to retain the current state.When constructing asynchronous sequential logic, care must be taken to ensurecorrect behaviour at all times by using the following guideines [12]:

• Only one input signal at a time may control a state transition.

• Each input signal comination must lead to a stable state.

• Only one state variable may change at any one state transition to avoidrace conditions and the inputs must be hazard free.

While it is possible to create asynchronous designs with PLDs it is generallynot recommended [10]. Internal routing may cause varying signal delays result-ing in glitches and race conditions, i.e., different results depending on the timingof the input signals. These delays may vary depending on the individual chip,temperature and other operational conditions and thus generate intermittentfaults which are difficult to locate [13]. Another drawback is that even thoughsome synthesizing tools can implement asynchronous functionality they are not

24

good at optimizing or analysing them and the code needs to be more explicit.When using asynchronous input signals, the guidelines mentioned above forasynchronous circuits should be followed by the part of the synchronous systemusing these inputs, after synchronisation. The input pulse length should also belonger than the system clock period.

5.2.2 Timing

While the delays in asynchronous designs are determined by the propagationdelays tPD of the individual chips, for synchronous designs one has to alsoconsider the clock period tCLK and the clock to pad delay tCO, from a registerto the output. Knowing these values and trying to achieve the same reactiontimes as the discrete implementation, a lower bound of the clock frequency canbe calculated by (5.1).

For values of 35, 4.9 and 5.6 ns for tdiscrete, tPD and tCO respectively, thisyields a minimum clock frequency of 40.8 MHz to meet the maximum delayrequirement. It is worth noting that these values are given a bit differently indata sheets. Most CPLDs list the worst case propagation delay through oneMC while FPGAs often list the best case propagation delay through one LUT.The number of LUTs a signal has to propagate through is difficult to knowbeforehand so this calculation is a rough estimation. Synthesizing towards aspecific device generates a more accurate analysis even before the device isconfigured.

tPD + tCO + tCLK ≤ tdiscrete

fCLK ≥1

tdiscrete − tPD − tCO

(5.1)

This calculation is based on a Moore type machine where the output dependson the present state only. A Mealy type machine, where the input and the statedecide the output together, may react faster. The state transitions should stillbe synchronous for robust operation. If the signal has to propagate throughseveral registers, it will be slower than this calculation as several clock cyclesare needed.

Choosing a higher frequency is possible for most devices. Excessively highclock frequencies would however increase the number of flip-flops necessary fortiming counters and increase both power consumption and the risk of electro-magnetic interference (EMI) coupling into other parts of the circuit. Moreimportantly, it sets harder constraints on internal routing path speed and theclock source generation becomes more difficult.

Some FPGAs contain phase-locked loops (PLLs) enabling the clock fre-quency to be multiplied by a rational number achieving higher clock frequenciesinternally than the clock source. This is however normally limited to the largerversions.

5.2.3 Inputs and outputs

As mentioned in Section 4.4, the minimum number of inputs are ENL, BCKplus one SAT per phase and a clock source input. It is advantageous if thesetolerate 5 V inputs but more important is that they accept the 3.3 V logic levels

25

of the signals from the MCU. To start operation in a known state, it should alsobe possible to use HDE as an input.

Using the existing MOSFET-drivers and routing ENL directly from the MCUrequires two outputs, DSC+ and DSC–, per phase for operation. They need tobe able to sink the current through R2 in Figure 4.6. With a value of R2 = 390 Ω,HDE = 5 V and base-emitter voltage UBE = 0.7 V, this current is 11 mA. Thisassumes that the PLD can output 5 V. If not then the driver might need somemodification and the current may change.

If deadband control is implemented in the PLD using either a driver-IC ormodifying the existing driver then this doubles the number of outputs requiredper phase to enable control of each MOSFET. The drive strength requirementcan however be reduced at least for some of them.

For supervision, the signals ENL, BCK and FWD from the internal states aswell as the direction signal DIR of each phase also require outputs. This totalsto a minimum number of I/Os for the different version alternatives as listed inTable 5.1 This is a minimum and a higher number is desirable for flexibility.

Single drive Dual driveExisting drivers 18 30Individual control 24 42

Table 5.1: Minimum number of I/Os depending on motor and gate driver setup.

5.2.4 Power requirements

The power consumed by the PLD or discrete logic itself is low compared to thecircuitry it is controlling in this system. For many other uses of PLDs such asin portable devices, the power consumption is more critical.

In a digital system, power consumption is proportional to load capacitance,switching frequency and supply voltage squared [12]. For this reason the supplyvoltages of PLDs have continuously moved towards lower and lower levels. Thecore voltage is often as low as 1.2, 1.8, 2.5 or 3.3 V.

To minimize the need for supporting circuitry while incorporating PLDs intoan existing system it is best to try and match the logic and supply levels alreadyused in the system. There are PLDs which operate from a 5 V supply. Theseare however in most cases older generation devices which are no longer producedat high volumes and whose prices are higher. Devices operating from 3.3 V arethus the preferred option for this system.

5.3 Additional requirements

In addition to the functional requirements there are a few other things to takeinto account. These serve the purpose of guaranteeing the longevity and relia-bility of the product as well as complying with market regulations and customerrequirements.

5.3.1 RoHS

Directive on the restriction of the use of certain hazardous substances in elec-trical and electronic equipment (RoHS) is a European Union directive limiting

26

the use of certain chemicals in electronics destined for the European market.The most prevalent of these is lead which is used in solder and some componentpackages. Component suppliers today are very good at supplying informationon whether or not a device fulfils the requirements and if not then there areusually alternative versions available which comply with the directive.

5.3.2 Automotive classification

Inmotion Technologies strive to use components which have been thoroughlytested and meet the specifications set by The Automotive Electronics Council(AEC). This classification is divided into AEC-Q100 for integrated circuits,AEC-Q101 for discrete active components and AEC-Q200 for passives.

Components having these classifications are a bit more expensive and maybe harder to acquire in single units. For the prototyping done in this project, re-placing some components by equivalents without the classification was accepted,especially for the passive components. Ensuring that the targeted PLD meetsthe classification was a higher priority.

5.3.3 ESD and EMC

Electrostatic discharge (ESD) and electromagnetic compatibility (EMC) liesbeyond the scope of this thesis. However, the AEC-Q100 classification includessome ESD testing. This circuit is also unlikely to be the culprit of a failed EMCclassification of the intended products.

5.3.4 Package

Many modern PLDs use ball grid array (BGA) packages. This makes verycompact designs possible. However, tests have shown that their solder joints aremore prone to cracking compared to more traditional component legs, causingreliability issues [14].

At Inmotion Tehnologies they are therefore avoided if possible. In the in-tended product range, the size of these devices does not entail very hard con-straints as the other available packaging types are still small compared to thediscrete implementation in total.

5.3.5 Production lifetime

Describing the functionality in code eases the transition from one device toanother. Despite this it is desirable to be able to use the selected device fora long time. As technology improves and new products are introduced, othersbecome obsolete. Even though the chips are highly customizable, some pins arefixed position and a new chip model would have slightly different characteristicsrequiring much work for verification and classification in the case of a change.

It is difficult to estimate how long a specific device will be in production andavailable for purchase but choosing a device from a newer family reduces therisk of having to redevelop and test the product again in the near future.

The very newest devices might however not yet have been tested for automo-tive classification. For more matured products the higher production volumeswill also have managed to reduce the prices compared to the newest devices. Toensure a good trade off between these factors and still make sure the device does

27

not go obsolete in the near future, a sales representative for the manufacturerof one of the more interesting devices in other regards was contacted.

5.4 Pricing

It is of course desirable to produce the system at the lowest possible price whilestill meeting all the other requirements. The discrete implementation achievesa low price since its constituent components are generic and produced at a verylarge scale. A PLD based solution may have more expensive components but alower amount.

This can have economic benefits in terms of easier redevelopment, lowermounting cost, smaller PCB area and fewer PCB layers. In case the totalcomponent cost is slightly higher than the existing discrete implementation itmay due to these factors still result in a reduction of total cost. Even so, thegoal is to find a solution where the price of components is at the same or a lowerlevel than that of the discrete implementation.

5.5 Hardware Description Language

The configuration of a PLD is described in a HDL. The two main HDLs usedin the industry are Very high speed integrated circuit hardware descriptionlanguage (VHDL) and Verilog. The preference of one over the other is subjectiveand a widely debated topic but most development tools support the use of both.

One difference between the two is that while VHDL might be more verbose,it is arguably more consistent in some regards. They can however both generateslightly different results with different compilers, optimization goals and targetedhardware.

The suppliers of PLDs often have their own proprietary languages as wellas the possibility to design circuits using graphical tools in the developmentsoftware. The drawback of these two methods is that they are tied to thesupplier’s range of products whereas the two aforementioned are standardizedand can be implemented in hardware of different manufacturers. In this project,all code is written in VHDL.

5.5.1 Constraints

The core functionality is described in the HDL. A few more device specificparameters are written into constraint files. These are used to map the internalsignals to the physical pins of the device as well as set timing constraints foranalysis. These will require some changes when changing hardware but thechanges are few and quite simple in most development tools. The constraintsregarding timing can in most cases also be described in the de-facto standardsyntax of Synopsys design constraints (SDC) files.

5.5.2 Configuration

Most devices support programming through a Joint Test Action Group (JTAG)-header using a programming cable from the device vendor to interface theirdevelopment software and produce the bitstream. Some suppliers offer softwarefor producing this interface as an embedded solution. The ability to configure

28

the PLD from the MCU eliminates the need for a separate programming stepin production which could otherwise increase the production cost.

29

6 Clock generation

The two MCUs in the system have one crystal oscillator each operating at20 MHz. These are internally multiplied to 200 MHz in the MCUs using PLLs.

Depending on the physical proximity of the MCUs in relation to the FPGA,sending a high frequency clock signal through long traces or cables is likely tocause problems. It is possible to achieve this functionality but for robust oper-ation it sets harder constraints on the routing and possibly on the impedanceof the PCB material if differential pair signalling is deemed necessary.

High speed differential pair signals are not used in any other parts of thesystem so instead the specifications on the PCB material are quite loose toenable the production by different manufacturers and also to keep the pricelow. The purpose of this project is to simplify the design, while introducingsuch requirements would have the opposite effect. For these reasons it is likelyto be more suitable with a locally generated clock source.

6.1 Internal oscillator

Some FPGAs have internal clock oscillators. They are usually complementarymetal oxide semiconductor (CMOS) type oscillators and their frequency toler-ance is therefore much higher than a quartz or microelectromechanical system(MEMS) type. Even if the frequency stability for one individual FPGA mightbe adequate, the variations in between chips makes them less suitable for se-ries production applications where accurate timing is necessary. For instancethe Altera Max10 FPGA has an internal clock frequency running at 55 to 116MHz with a typical value of 82 MHz [15]. For use as a time base these largevariations would require individual testing and tweaking for every unit and beimpractical and costly. For another device, the Lattice MachXO, the internaloscillator operates between 18 and 26 MHz [16]. This is lower than the frequencyrequirement estimated in (5.1) and further motivates external clock generation.

The internal oscillator is useful if it is only a means of synchronising theinternal logic. If no actual time measurements are required and the delaysassociated with the frequency range are acceptable it could be useful. In thissystem, as discussed before, this is not the case.

6.2 Pierce oscillator

For applications requiring a stable and accurate clock source the Pierce crystaloscillator depicted in Figure 6.1 is the most common topology. It has a simplestructure with only a few low cost components and the timing element is apiezoelectric crystal that can be manufactured to very narrow tolerances.

In this circuit, Rs serves two purposes. It limits the drive strength which isnecessary especially for tuning fork crystals as they can be damaged if driven toohard. For frequencies lower than 8 MHz it also serves the purpose of increasingthe phase lag around the loop. For frequencies above 20 MHz it is often omittedas the resistance from the gate output in itself is enough to achieve this.

The function of Rf is to linearise the gate for use as an amplifier, chargingC1 and the input capacitance from the output. The value of this resistor is notcritical and is on the order of 1 MΩ. This resistor is in many cases includedinternally for the clock input of ICs.

30

Output

Rf

C1 C2

Rs

Figure 6.1: Pierce crystal oscillator.

The crystals are tuned for a specific load capacitance Cload. The choice ofC1 and C2 should be adjusted to meet this value. The load capacitance seen bythe crystal can be calculated using (6.1) [17].

Cout should only be included if the value of Rs is near zero Ohms as a highervalue will isolate this capacitance from the crystal.

Cload =(Cin + C1)(Cout + C2)

Cin + Cout + C1 + C2+ CPCB (6.1)

CPCB is the sum of stray capacitances from PCB traces and pads to theclosest ground or power plane. This is often estimated to a value of 2-3 pF orcalculated by using (6.2). With measurements of area A in square metres andthe board thickness d in metres, a value of 1120/127× 10−9 gives an estimateof the stray capacitance, CPCB , in Farads. For standard FR4 PCB the relativepermittivity εr is usually somewhere between 3 and 5, typically 4.5 [18].

CPCB =k × εr ×A

d(6.2)

The main drawback of constructing the clock oscillator from discrete compo-nents is that it requires testing to make sure it starts and maintains oscillationunder various operating conditions. Another limiting factor is that for robustperformance with a PLD gate as driver, the crystal should operate at its fun-damental frequency. Crystals oscillating above 50 MHz typically operate at thethird overtone and thus have less robust operation.

6.3 Oscillator integrated circuit

An alternative to constructing a Pierce crystal oscillator with one of the gatesof the PLD is to use an oscillator IC. These have everything included in onechip in a similar form factor as a discrete crystal. Stability and oscillation isguaranteed and no calculations or tests are required since the output is bufferedin the IC and hence not influenced by stray capacitances. The drawbacks are a

31

higher price per oscillator compared to a discrete solution and that it needs apower supply.

32

Part II

Practice

7 Implementation

There are many ways to implement the functionality of the existing system. Anaive approach would be to translate the existing discrete design into an HDLand load into the PLD. While this could work it will be far from an efficientsolution in terms of chip utilization and timing. Care needs to be taken whentranslating the asynchronous logic into a synchronous design.

To better utilise the available functionality of the PLD, the knowledge of theexisting system and internal dependencies were used to develop a new internalstructure while the behaviour as seen from the rest of the system is unchanged.

The functionality of the VHDL code can be broken down into parts similarto the different circuits of the discrete implementation. These combine into thefull functionality as displayed in Figure 7.1.

Controlstate

Saturationhandler

ENLBCK

HDE

SAT

Phaseoutputs

DSC+

DSC–

DIR

FWDENLs

BCKs

SATs

For each phase

FPGA

Figure 7.1: Functionality block diagram.

7.1 Internal function blocks

7.1.1 Control state

The control state is an FSM taking the inputs ENL and BCK to keep track ofwhere in the measurement cycle it is. The signal HDE is included to make surethe cycle starts in the correct state but also as a redundancy feature, interruptingthe pulse sequence if HDE goes low.

On each positive edge of the clock, the three input signals are evaluatedand the state vector is updated according to the state diagram in Figure 7.2.This state vector is passed on to be used as an input to all the other functionblocks. Compared to the state diagram in Figure 4.1 the saturation is moved toa separate function block enabling the states to be used globally for all phases.

33

offstart idle frwd back measHDE=1

ENL=1 BCK=1 BCK=0

ENL=0

HDE=0

Figure 7.2: Control state diagram.

7.1.2 Saturation handler

The saturation handler is another small FSM, albeit a simpler one, implementedfor each phase as shown in Figure 7.3. It takes the control state as input as wellas the SAT-signal for the phase in question and has only two states, Saturatedand Unsaturated. The function block outputs DIR and SATs (synchronised).

unsatstart sat

SAT = 0

New state:toggle DIR at end of ENL.

Figure 7.3: Saturation state diagram.

The FSM is initiated in the Unsaturated state. If SAT goes low, indicatingsaturation of the core, the current control state and the current direction arelogged. The state is changed from Unsaturated to Saturated on the followingclock pulse.

If SAT is high in the Saturated state and the current control state differsfrom the logged one, in which saturation occurred, then the state is reset toUnsaturated and the next output value of the signal DIR is updated to opposethe value when it saturated. When the measurement cycle is finished, i.e.,control state is in Idle or Off, the output DIR is updated to this value. Thesevalues are only new when exiting the Saturated state.

The reason for waiting with updating DIR is to maintain the same valuefor the states Forward and Back simplifying the logic for applying the correctoutput in Back after a saturating Forward. Neglecting to do so would resultin the Back -pulse having the same direction as Forward, driving the core intosaturation once again.

The saturation state latches in a similar way as the discrete design. If theinput signal SAT would be used directly to control the output, the MOSFETwould be activated as soon as the current in the coil drops and the comparatorgoes back high. This would create unwanted oscillations. To mitigate this thesaturated state is maintained until the control state has changed.

This FSM is implemented as a Moore type with the output only dependingon the current state. This will not make it optimal in terms of reaction time

34

but is simple and will minimize the area used since the state and the output areclosely coupled [12].

To reduce delay from comparator signal to output by one clock period, alogic AND-operation between the SAT input and the saturation state could beused to control the output rendering it a Mealy type FSM if necessary. Thisassumes the SAT input is synchronized to avoid problems with asynchronouslogic.

7.1.3 Phase outputs

The outputs from the control state block and the saturation handler are com-bined according to Table 7.1 to form the outputs DSC+ and DSC

−for each

phase. These two signals are fed out to the driver circuitry together with theglobal signal ENL to control the MOSFETs according to Table 4.3.

Control state Saturation state OutputOff

- 11Idle

ForwardUnsaturated DIR DIRSaturated 11

BackUnsaturated DIR DIRSaturated 11

Measure - 11

Table 7.1: Combinational output.

7.1.4 Supervision outputs

The states Enable, Forward and Back generated in the Control state-block aresent out in their synchronised form to be measured by the supervision MCU.This is also true for the DIR signal of each phase as generated by the saturationhandler.

7.2 Additional functionality - deadband control

The described functionality can be made to use very little space, possibly itcould fit into even simpler PLDs than those described in Section 5.1 such as aprogrammable array logic (PAL), equivalent to a single MC of a CPLD. Thegains of selecting one of those are however small if any. Their functionality andnumber of I/Os, and thus their versatility, is significantly reduced. Selectionis scarcer because of lower demand resulting in higher prices and difficultiesin meeting other requirements such as automotive grade. The developmentwould become more difficult while the area and cost of the printed circuit boardassembly (PCBA) would remain very similar.

To better utilise the available logic in the CPLD of FPGA, an extendedversion was created where some functions were modified or added to implementa controllable deadband. This has the possibility to improve switching perfor-mance compared to having a capacitor connected to the MOSFET gate whileusing hardware that is already paid for with the basic functionality described

35

above. Possibly it could open up for removing even more components than thelogic mentioned in Table 4.5 and the gate capacitors.

7.2.1 State transition timer

The control state block is left unchanged in the implemention with deadbandbut its state is sent directly to the state transition timer in Figure 7.4. Whenthe control state changes, a counter is started and the drive of the MOSFETsis inhibited by resetting a signal, Transition, going to the phase output block.

When the timer reaches a set value, this signal goes back high enabling theturn-on of the MOSFETs. First the P-channel, then the N-channel. The timeris implemented as a simple counter incremented on the rising edge of the clock.For a 50 MHz clock this gives a resolution of 20 ns.

on11

start

off00

P on10

New state P-timer finished

N-timer finished

Figure 7.4: State transition timer diagram.

The synchronous nature of the logic causes the reset of Transition to occurone clock period after the change of Control state. If these signals were to becombined directly to generate the output, one MOSFET pair corresponding tothe new state would be turned on for one clock cycle without any delay as theprevious pair is turned off.

It would only be on for one clock cycle before being turned off for the dead-band time but would run the risk of causing shoot-through in both half-bridgeswhen transitioning from Forward to Back, and in one half-bridge when transi-tioning from Back to Measure.

To mitigate this, the Control state is delayed by one period in this blockbefore being passed on. This keeps the two signals in sync while not affectingthe timing relative to the MCU more than 20 ns. This can be compared to theaccumulated propagation delay through the discrete circuit at a state transitionwhich has a typical value of 31.6 ns and a maximum of 68.5 ns.

7.2.2 Saturation timer

The saturation handler also requires some modifications to implement dead-band. An extra state, Counting, is added between the Unsaturated and theSaturated state as shown in Figure 7.5. At saturation detection, this state is en-tered and the four MOSFETs for that phase are turned off. After a set amountof time, the saturated state is entered and the two N-channel MOSFETs areturned on. This state is maintained until the Control state is changed. At that

36

point, Unsaturated is re-entered and the signal DIR is set to update at the endof the ENL-pulse.

unsatstart

count

sat

SAT = 0 Timer finished

New state:toggle DIR at end of ENL

Figure 7.5: Saturation timer state diagram.

Adding a timer for each phase uses up a lot more of the available registersin the PLD. Since the sampling frequency is 4 kHz and the maximum motorfrequency is 599 Hz, the shortest time between two consecutive zero-crossings ofthe motor phases is more than twice the sampling period. This could enable thedifferent phases of one motor to use one saturation timer as a shared resource.This would however create some overhead which could limit the benefits ofsuch an approach when the timers are relatively small in bit-length. Moreimportantly, the intentional simultaneous saturation of all phases as describedin Section 4.5.2 makes separate independent saturation timers necessary.

7.2.3 Phase outputs

The Phase output block is expanded to accommodate the increased amount ofcontrol signals from the other blocks, as can be seen in Table 7.2. This block isstill strictly combinatorial and only has internal, synchronized signals as inputs.It now has four outputs, one for each MOSFET, P+, N+, P–, N–.

7.3 Timing

In an MCU it is common to use one hardware timer for several tasks and inthe case of a timer compare match, an interrupt is generated and some taskis executed. The counter value at the interrupt can then be compared to therunning counter. This enables several routines to use the same counter which ispreferable as the MCU is more restricted on available timers than memory. Thesame concept could be used here too but, as saving large value numbers requiresa considerable amount of flip-flops and logic to control for timer wrap around,it does not have the same benefits in a PLD where memory and counters usethe same building blocks.

7.3.1 Clock source

For the initial tests the internal RC-timer was used as the clock source. To drivean external Pierce crystal oscillator circuit, the VHDL code below was used to

37

Control state Saturation state Direction Transition OutputOff - - - 0000Idle - - - 0000

ForwardUnsaturated

0 - 10011 - 0110

Counting - - 0000Finished - - 0101

BackUnsaturated

000 000010 001011 0110

100 000010 100011 1001

Counting - - 0000Finished - - 0101

Measure - -00 000010 000011 0101

Table 7.2: Combinational output.

act as a simple inverter as seen from the outside and as a clock signal CLK asseen from the inside.

library IEEE;

use IEEE.std_logic_1164.all;

entity crystaldrive is

port( Xin: in std_logic;

Xout, CLK: out std_logic);

end entity crystaldrive;

architecture RTL of crystaldrive is

begin

Xout <= not Xin;

CLK <= Xin;

end architecture RTL;

7.4 State encoding

Some considerations should be taken when choosing the state encoding for statemachines. Although this decision may be left to the compiler to choose as itsees fit, the different encodings can yield slightly different results. The threemost common encodings are as follows:

Ripple encoding is the natural binary numbering, rendering it very easy touse and interpret as well as to send on to other function blocks. A state machinewith n states uses ⌈log2(n)⌉ bits so a state machine with up to 16 states requiresa three bit state vector to store which state it is in.

38

Gray encoding is a modified pattern of the ripple encoding. This type ofencoding has a Hamming distance of one, i.e., only one bit in the state vectorchanges when going from one state to the next. This makes its transitions morerobust compared to ripple encoding where all the bits may change at one statetransition. This, however, assumes that the states change in a linear manner,going from one state to either the next or the previous in a linear sequence. Ifit is to loop around and go from the last to the initial state, the total number ofstates has to be a power of two. For state transitions that do not follow theserules, more than one bit in the state vector may change. Another limitationof this encoding is the potentially increased complexity in translating the statevector when interfacing other modules.

One-hot encoding uses one bit of the state vector for each state. The lengthof the state vector is equal to the number of states and only one bit is highor hot at a time. This reduces the amount of combinational logic required forstate transitions at the expense of more registers with quicker transitions as aresult. This is advantageous in FPGA which have many flip-flops relative to theamount of combinational logic [10]. It has a fixed Hamming distance of two.

7.4.1 Forming outputs

Another consideration is how to form the outputs from the state vector. Usingthe state vector directly as an output results in the fastest possible conversionfor a type Moore state machine and the smallest area use [10]. A drawback withthis approach is that the states have to be defined explicitly as the output datatype e.g. standard logic which is less flexible than defining them more implicitlyas type state. A change in state encoding requires updating the other moduleswhich use the state vector as an input and the compiler cannot optimize thestate encoding.

Another option is to have a separate process for forming the output from thestate vector. This increases the flexibility and enables the compiler to changestate encoding. In this case, the state representation should not be converteddirectly to form the output as a change made by the compiler can change thefunctionality.

Different solutions were tested both in choice of encoding and methods toform the output. Timing analysis shows a slight increase in conversion delaywhen using a separate process but nothing substantial.

7.5 Gate driver

In order to turn on the MOSFETs and also take them out of the linear regionwhere the losses are high, the gate to source voltage, UGS, needs to be higherthan the 3.3 V output of the PLD. The P-channel source is connected to thesupply rather than ground and requires a negative UGS to turn it on. Thecharging of the gate capacitance also requires higher current capabilities thanthat of the PLD output.

The N- and P-channel MOSFETs tolerate a maximum of ± 16 V and ± 20 Vof UGS respectively. A driver circuit that delivers the full supply voltage of0− 27 V to the gates would therefore damage them. There are however several

39

options to drive the power-MOSFET gates from the low voltage PLD outputwhile taking these restrictions into account.

7.5.1 Minimum change

The driver circuit could be left as it is in Figure 4.6. The exception being thatthe base voltage to the NPN-transistor has to be lowered to allow the 3.3Vsignal to turn it off and the resistor values of R1 and R2 changed accordingly.

As mentioned in Section 4.4 the drive strength PLD is of importance. TheMachXO has configurable drive strength with the ability to sink up to 16 mAor source up to 14 mA per I/O [16] which is enough to control this circuit.

The deadband is built into the circuit and is fixed at assembly. Only twosignals per H-bridge come from the PLD.

7.5.2 Dedicated driver chip

Driving an H-bridge or discrete MOSFETs from a low voltage, low current sourcesuch as an MCU is a common task and consequently, a plethora of dedicatedgate driver ICs exist, sometimes with a programmable deadband control builtin.

The more complex drivers are most often designed for pulse-width modula-tion (PWM) control of inductive loads with a single input signal per H-bridge.The idle state where all MOSFETs of the H-bridge are turned off is thereforenot available, hence these are less useful in this application where more controlis wanted while at the same time not requiring more processing from the MCU.

Simpler versions with a one-to-one relationship between inputs and outputsare more useful here and would give the PLD control over the individual MOS-FETs. Limiting factors for this application are the operating voltage, the outputvoltage swing and the ability to drive a P-channel MOSFET as well as the priceof the unit.

Many gate driver ICs are designed to drive one or two N-channel MOSFETswith a bootstrap configuration as this is a common design choice. Others weredeemed unsuitable since they cannot operate from the 27 V supply voltage orbecause the output swing is the full 27 V of the supply.

One device that was investigated a bit further was the FAN3278 fron ONsemiconductor. It operates from a nominal 8 − 27 V supply and has a voltagelimitation of 13 V on the outputs. One output is intended for a high side P-channel and one for a low side N-channel. The inputs accept LVTTL voltagelevels and each driver has an disable function similar to the HDE signal in thediscrete solution. This could be connected between the PLD an the MOSFETsaccording to Figure 7.6.

Although this is a fairly low price unit it still costs more than the discretecircuit. This, coupled with a maximum supply voltage rating of 30 V, only 3 Vabove nominal, puts an end to further investigation of this solution.

7.5.3 Modified discrete driver

Another approach is to use the existing design but modify it to accommodateindividual control of the MOSFETs and possibly remove a few components thatare no longer necessary, see Figure 7.7. By splitting the signal DSC close to

40

PLD

HDE

N

P

A

B

VDD

ENB

GND

ENA

27V

Coil

Meas

Figure 7.6: Connection of a dedicated driver chip between PLD and MOSFETs.

where it enters in Figure 4.6 the high and low side of the half bridge can becontrolled individually while maintaining the low cost of the current design.

With deadband controlled by the PLD the external capacitor connected tothe N-channel MOSFET can be removed. This reduces the transition delaywhen going from high to low from 260 to 130 ns according to simulations. Theinverse transition delay is reduced by a few nanoseconds, from 46 to 37 ns.

Without the external capacitance there is less need for the discharge MOS-FET T1. In an attempt to further simplify the circuit this was removed alongwith R7. The two NAND-gates can now be replaced by a NOT-gate in the samefamily, reducing the number of ICs per motor from three to one. This NOT-gateacts as a simple level shifter from 3.3 to 5 V.

The peak current flowing in and out of the MOSFET gate exceeds the ratingof both the logic gate and the 0603 package resistor connected to it. This isalso true for the existing circuit when going high. These peaks are however veryshort. The resistors used are rated for 0.1W continously but for repeated pulsesof length 1 µs they can withstand up to 20W.

41

P

N

HDE

Usupply

Coil

Meas

Figure 7.7: Modified gate driver circuit.

42

8 Simulation

Before starting the design of a prototype board with a PLD and a gate driver,both parts were simulated separately.

8.1 VHDL

Code development started in the Altera Quartus prime software targeting adevelopment board with a Max10 FPGA. This FPGA containing 50 000 logicelements vastly exceeds the requirements in terms of logic area but this stepwas useful in order to get a rough estimate of the number of LEs needed to holdthe application before choosing a PLD for the prototype. Having decided on aproduct family, development was continued in Lattice Diamond software.

Simulation was useful to test the functionality of the different modules aswell as sorting out a couple of bugs and glitches when integrating them, be-fore loading the configuration into hardware. The timing analysis performedshowed that, in the selected device, the internal delays in the application canbe constrained to 8.2 ns giving a maximum useful clock frequency of 120 MHz.There is however the possibility to use higher frequencies, for instance the MCUclock frequency of 200 MHz, in a limited part which could divide it down usinginternal flip-flops to create a clock source of 100 or 50 MHz to be used by therest of the circuit.

8.2 Gate driver

A simulation model in LTspice for the existing gate driver circuit was availablefrom Inmotion. It has a few simplifications such as the logic gates being idealexcept for their rise time. The third party model for the power-MOSFETs alsoproved to have problems with computational precision creating singularitieswhen an inductive load drives current through its body diode. For this reasonthe model was used with a resistive load. The model was otherwise a goodrepresentation of the circuit behaviour and was very useful when adapting thecircuit for 3.3 V, dual input signals.

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9 Prototype

Lattice MachXO Automotive family of FPGAs was chosen for the prototype.It is available in sizes from 256 to 2280 LEs and has integrated non-volatileconfiguration memory. As such it is often marketed as a CPLD. It can operatefrom a 3.3 V supply and is automotive grade.

Released in 2007 it is not the newest circuit on the market but that hasmanaged to reduce the price significantly. The Swedish sales representativefor Lattice products was contacted who guaranteed that it will be in volumeproduction for more than ten years and that other companies are still designingit into new products. The arrangement of a formal letter of intent, directly fromLattice, was also offered to support this claim.

9.1 Breakout board

The first tests were performed on a breakout board with an LCMXO2280Cwhich is the largest of the family. It differs from the intended FPGA in thatit lacks automotive classification, is in a BGA package and on a few other andpoints like a lower temperature rating. Being the biggest one in the family it isalso marginally slower than the smaller circuits. These things are not of greatimportance for initial tests, focusing on logic functionality.

This breakout board does not include a separate oscillator but instead usesthe internal oscillator of the FPGA. This operates at a lower frequency thanthe intended final application but the two larger chips of this family have oneor two PLLs making it possible to step up or down the operating frequency bya rational number. The clock input pins are also accessible for connecting anexternal clock source. Testing started with the internal oscillator and later, anexternal oscillator IC was used.

Asynchronous timing effects cannot be simulated properly, so testing func-tionality on a breakout board was an easy step to acquire some practical resultsbefore designing, ordering and assembling a custom PCB. With some minormodifications this board could also be used as a JTAG programmer, interfacingthe Lattice Diamond Software to other boards.

9.2 Custom PCB

A custom PCB was designed and assembled, as can be seen in Figure 9.1. It usesan LAMXO256C-TN100E which is a MachXO series Automotive grade FPGAwith 256 LEs and integrated non-volatile configuration memory housed in a 100-pin thin quad flat package (TQFP). The board also features the prototype gatedriver from Figure 7.7 for the control of up to two motors. Pads were includedboth for a discrete Pierce crystal oscillator and for an oscillator IC.

A bit of work went into ensuring good decoupling, especially for the FPGA.Strategies and help in estimating parameters were taken from [19] in combi-nation with [20]. Estimation was simplified by using the impedance versusfrequency tool at app.pdntool.com and the input/output buffer informationspecification (IBIS) model generated by the Lattice Diamond software.

The prototype board was designed to have all its components mounted onone side since that is a common cost savings measure for series production. Forquick and economical production of a small batch prototype, the PCB was a

44

Figure 9.1: Assembled prototype board.

dual layer board whereas the control boards in use today use eight layers andmount some surface mounted devices (SMDs) on the bottom side.

45

10 Test setup

Tests were performed in several steps. The logic functionality was developedand tested iteratively, using first the breadboard and later the prototype board,feeding it input signals and measuring the outputs. Later, the prototype boardwas connected to the control board of a VFD to replace the existing MSMcontrol circuitry.

10.1 Logic functionality

The logic functionality was tested on the breakout board and prototype boardas a standalone circuit, fed by a 3.3 V supply. The input signal HDE was toggledhigh or low with a simple switch. An Arduino nano clone was programmed tosend out the input signals ENL, BCK and SAT with ENL being high for 20 µsat a frequency of 4 kHz, BCK going high 10 µs into the ENL pulse for theduration of 5 µs and SAT appearing as a short pulse during the Forward orBack state. The 16 MHz clock of the arduino somewhat limits the minimumpulselength and timing between output changes but some variations in the SATsignal timing were tested.

The Arduino requires a 5 V supply to operate and this is also the outputsignal level. To increase noise immunity compared to a simple voltage divider,a CMOS buffer circuit was used to step down the 5 V pulses from the microcon-troller to 3.3 V. Unfortunately the rise time of the buffer circuit was measuredto 70 ns rendering this setup suboptimal for timing measurements but it didprove useful to test functionality in a more general sense.

10.2 Interfacing a drive

The circuit was tested interfacing a control board of a VFD. The one used forthese tests was an older version than what is currently in production. The maindifference worth considering in this project compared to the newer ones is thatcurrent measurements are only performed on two of the motor phases, U and W.The current in phase V is calculated only. There is also no supervision MCU.

Another consideration is that deadband is achieved without a capacitor inthe low side MOSFET-driver. This capacitor was a later addition to reduce therisk of shoot-through. Some resistors in this circuit have other values but thecircuit has the same topology as depicted in Figure 4.6 excluding C1 and R6.

The first round of tests were performed without any modifications to thedrive, apart from setting up test points, to serve as a baseline for comparisons.For the second round of tests, the FPGA on the prototype board was usedto replace the logic between the MCU and the gate driver circuitry. Outputsignals from the FPGA were fed to where the signal DSC normally enters thegate driver circuitry. After that, tests were done with the new modified gatedrivers on the prototype board with deadband controlled by the FPGA.

10.2.1 Control board modifications

A few modifications were needed on the control board to make it work with thenew circuit and its lower voltage. Comparator outputs, normally entering thecircuits in Figure 4.4, were tied together with one pull-up resistor per phase to

46

3.3 V instead of two separate to 5 V. This means that SATU+ and SATU−now

form SATU together, which goes low when phase U saturates in either directionand is used as an input to the FPGA.

For the circuit in Figure 4.7, creating the signal HDE, R9 and the transistoremitter were tied to the 3.3 V supply instead of 5 V. R10 was changed accordinglyto give the same characteristics but at the lower signal level.

In the gate driver circuit, Figure 4.6, R1 and R2 were changed to work withthe new lower voltage of HDE and DSC from the FPGA. When testing theprototype gate drivers, the on board gate drivers where bypassed completely.

In this older version of the drive, the logic gates were distributed a bitdifferently between different ICs than they are in the current products so someof them remained on the board partially unused. The inputs of these logic gatesneeded to be tied to either ground or supply voltage to keep them in a stablestate. Other ICs could be removed entirely.

10.2.2 State transitions

To analyse signal propagation through the circuit, the delay from the edges ofsignal inputs ENL and BCK to the corresponding changes in output signalsDSC were measured with an oscilloscope. The delays were also measured fromthe inputs to the supervision outputs of the FPGA as they are formed from theinternal representation of the inputs.

10.2.3 Measurement accuracy

To compare current measurement accuracy, current was driven through themeasurement coils from an external power supply and measurements were readfrom the MCU by connecting to it over controller area network (CAN).

The current conducting cable was wrapped ten times through both mea-surement coils instead of the usual setup where the motor phase current passesonly once through one of the cores. This was done to simulate a ten times big-ger current. This way measurements could be done in the range ± 70 A eventhough the supply used was limited to 7 A. Although this is only a small partof the intended full range of ± 1150 A, it gives good insight on measurementperformance for a comparison of the two implementations.

A 5 mH choke was added in series with this primary winding to increase itsinductance. The inductance is necessary to reduce the currents induced in theprimary winding from the switching in the secondary which is the basis of thistype of current measurement. In a normal vehicle setup the inductance of theload, i.e., the motor, is sufficient to serve this purpose.

As a reference when setting the primary current, a Hall-effect sensor basedcurrent clamp connected to a multimeter was used.

The measurement readout is the raw ADC value from the MCU. This mea-surement comes from a differential operational amplifier measuring the voltageover the two shunts in the H-bridge, see Figure 2.2. It has an offset to handleboth positive and negative currents and the resulting ADC-value follows thecurrent I according to (10.1). To get back the measured current from the readADC-value, equation (10.2) can be used.

47

n number of measurements 2N turns ratio 100/1R shunt resistance 0.2/3 ΩAOP operational amplifier gain 33/34Uo Measurement offset voltage 1.5 VUr ADC reference voltage (max measurement) 3 Vb ADC bit-length 12

ADCvalue =

⌊(

Uo −InR

NAOP

)2b

Ur

⌋

− 1 (10.1)

I =

(

Ur − Uo −(ADCvalue + 1)Ur

2b

)N

AOPnR(10.2)

10.2.4 Saturation detection

To test the detection of core saturation, the current source for the primarywindings was changed from the DC power supply to 50 Hz mains frequencycoming from an isolation transformer. This was stepped down through a variableautotransformer and limited by power resistors to give 2.5 A.

10.2.5 Power consumption

To evaluate the power consumption of the prototype, currents drawn from thethree important supply voltages were measured.

27 V This power rail drives the current through the measurement transformersecondary windings. It is also used in the high side gate driver circuit. All cur-rent measurement components using this supply are separated from the powersupply module by a common LC filer. A 0.1 Ω shunt resistor was introducedin series after the filter and the voltage over it was used to measure the currentdrawn by the current measurement circuitry from this supply.

The current consumption is expected to increase with motor frequency, mo-tor current and saturation detection delay.

5 V Most of the discrete logic uses 5 V supply. In the existing circuit, a5.6 Ω, 1% tolerance resistor separates the current measurement supply from the5 V supply used by the rest of the control board. It acts as an RC low-passfilter together with a capacitor. The voltage drop over this resistor was used tomeasure the current consumption.

3.3 V No separate 3.3 V supply existed for the current measurement in theunmodified drive. However, only one IC in the current measurement controlcircuitry uses the 3.3 V supply: the FWD pulse generation in Figure 4.2. ThisIC experiences only a few transitions every measurement cycle and as such itscurrent consumption is assumed to be negligible.

For the prototype board on the other hand, this is the supply used to powerthe FPGA. The current is supplied from the LDO on the control board, througha 0.1 Ω shunt resistor to be able to measure the current.

48

This does not account for the pull-up resistors of the comparators which,in the unmodified drive, were tied to the 5 V supply mentioned above andwere changed to the 3.3 V supply. They draw around 1 mA during saturationdetection. This pulse length may change with the reaction time of the logicbut is very short and the power consumption is insignificant compared to the27 V supply feeding current through a saturated measurement transformer. Thepower dissipated in the pull-up resistors is also reduced proportional to the lowersupply voltage.

10.2.6 Deadband timing

To evaluate the extended functionality with deadband control, measurementswere also taken on the signals to the gate drivers as well as on the H-brideconnection to the coil terminals, without load.

49

11 Test results

The logic functionality testing and rewriting of the VHDL code was very muchan iterative process given the limited prior experience in FPGA programming.At first, the synchronisation of the input signals was forgotten causing some un-expected effects with intermittent missed or erroneous state transitions, demon-strating the importance of input signal synchronisation.

After some time testing with only the arduino inputs, the prototype boardwas successfully connected to a drive, controlling its current measurements.Figure 11.1 shows the inputs FWD, and BCK as well as the DSC outputs con-trolling one half bridge each for one phase in the unmodified drive. Figure 11.2shows the same signals when controlled by the FPGA. On this large scale thesignals look very similar except for the output signal levels being reduced from5 to 3.3 V and some ringing caused by the increased inductance in the intercon-necting cables.

The code for the prototype board was written for three-phase measurementbut could be used for the two phases of the drive without modifications to thecode and the unconnected SAT input of phase V internally pulled high.

11.1 Response times

When looking closer at the transitions, it is clear that the delays increase whenusing the FPGA compared to the discrete implementation. The delays cal-culated previously for the discrete implementation were based on the worstcase propagation times for the individual gates while the typical delay is muchshorter. Measured delays from input to output signal edges were typically 15 nsor less, shorter than the FPGA clock period of 20 ns. Figure 11.3 shows thedelay from rising edge of ENL to the corresponding falling edge of one of theDSC signals in the unmodified drive.

The signal propagation through the FPGA is consistently 26 – 46 ns for thedifferent state transitions, i.e., 6 ns plus one to two clock periods, dependingon when the rising edge of the input occurs relative to the clock. Figure 11.4shows a number of sweeps for the falling edge of DSC following the rising edgeof ENL.

The internal representation of the input signals and the internal states canbe measured through the supervision outputs. Figure 11.5 shows the delay fromthe input signal ENL to the output signal ENLs. These signals experience thesame delays.

Figures 11.6 and 11.7 show the saturation signal from the comparator to-gether with the rising edge of DSC from the discrete logic and the FPGA re-spectively. The edges of the SAT signal from the comparators are not as sharpas those coming from logic gates. The actual transition voltage for an inputgoing low is 0.8 V or less which is why the delay depicted is a few nanosecondslonger than that of the state transitions.

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1: ENL from MCU

3: DSC+ from discrete logic

2: BCK from MCU

4: DSC- from discrete logic

Figure 11.1: Overview of state inputs and outputs to gate drivers in an unmodi-fied drive. Horizontal scale is displayed in the H field in the upper left (timebasehere 2 µs per division). Vertical scale (voltage from channel reference point onthe left) is displayed for each channel in the lower left.

1: ENL from MCU

3: DSC+ from FPGA

2: BCK from MCU

4: DSC– from FPGA

Figure 11.2: Overview of state inputs and outputs to gate drivers when con-trolled by the FPGA.

51

1: ENL from MCU. 2: DSC from discrete logic.

Figure 11.3: Delay from rising edge of ENL to falling edge of DSC.

1: ENL from MCU. 2: DSC from FPGA.

Figure 11.4: Delay from rising edge of ENL to falling edge of DSC on prototypeboard.

52

1: ENL from MCU. 2: ENLs from FPGA.

Figure 11.5: Delay from rising edge of ENL input to its corresponding supervi-sion output.

53

1: SAT from comparator. 2: DSC from discrete logic.

Figure 11.6: Saturation signal and DSC transition delay in an unmodified drive.

1: SAT from comparator. 2: DSC from FPGA.

Figure 11.7: Saturation signal and DSC transition delay from the FPGA.

54

11.2 Measurement accuracy

To compare measurement accuracy, measurements were taken at different cur-rent levels from -70 to 70 A in 10 A increments. The current in the primarywinding was measured with a current clamp and multimeter and the power sup-ply adjusted accordingly. Actual current level was ± 7 A, but the ten windingsimitate a greater range.

2000 samples were taken at each step (0.5 s). The average of each set ofsamples is shown plotted against the reference measurement from the currentclamp in Figure 11.8. The measurements in both the discrete and the FPGAimplementation seem to have good linearity in this range but are difficult todistinguish.

−60 −40 −20 0 20 40 60

−60

−40

−20

0

20

40

60

Reference measurement [A]

MSM

measurement[A

]

Discrete UDiscrete WPLD UPLD W

Figure 11.8: Averaged measurement results.

Figure 11.9 instead shows how much the averaged measurements deviatefrom the current clamp measurement, with sign. There is a big step in theerror around zero. Most likely this is not an effect of the measurement methodbut rather symptomatic of incorrect zeroing of the current clamp used for thereference measurement. For each measurement, the current level was set and ameasurement taken in one direction, then the connections to the power supplywere interchanged and another measurement was taken of the same amplitudebut opposed sign. Setting the zero level slightly to low for the reference measure-ment would make the positive and the zero current MSM measurement slightlyhigh and the negative current measurement slightly low.

Another factor rendering this setup suboptimal for evaluating the true ac-curacy of the method is that the winding of the primary differs from a singlebus bar passing through once which will affect the measurements.

The measurements are however consistent between the two implementationsand as such, the error does not seem to be a result of which implementation isused.

55

−60 −40 −20 0 20 40 60

−0.5

−0.25

0

0.25

0.5

0.75

1

Reference measurement [A]

Meanerror[A

]

Discrete UDiscrete WPLD UPLD W

Figure 11.9: Comparison between the error in averaged measurement results.

Looking at the standard deviation in the sets of measurements, Figure 11.10,and the worst outlier in each set, Figure 11.11, the two implementations alsobehave very similarly. While the worst error of 5.66 A for the discrete imple-mentation at 60 A might seem big, it represents an error of 10 least significantbits (LSBs) or 7.3 mV on the ADC input which is not an unreasonable noiselevel when operating without enclosure and considering the aforementioned er-ror sources. The ADC also introduces non-linearities in the measurement witha possible error of up to 7 LSBs.

11.3 Power consumption

Current consumption from each power supply was measured at the differentmotor current levels using the shunt resistors mentioned in Section 10.2.5. Theresults are shown in Figures 11.12 through 11.14. To visualize the total powerconsumed by the current measurement, Figure 11.15 shows the same currentsmultiplied by the nominal voltage of the supply rails where they originate. The3.3 V supply is excluded for the unmodified drive with the discrete logic imple-mentation.

The big increase in power consumption at zero motor current is an effectof the current measurements operational mode. There is no primary currentdriving the transformer into saturation between each measurement cycle. In-stead, the current driven through the secondary coil is the only thing affectingthe operating point in the hysteresis curve. The difference in pulse lengths be-tween forward and back and the magnetic remanence will move the operatingpoint in the forward direction. Around every four measurement cycles, the corewill reach saturation and change direction for the next measurement. Hence,the result is equivalent to a low level primary current changing direction at 1kHz and the power consumption from the 27 V supply is much higher than for

56

−60 −40 −20 0 20 40 60

0

0.25

0.5

0.75

1

1.25

Reference measurement [A]

Standard

deviation[A

]

Discrete UDiscrete WPLD UPLD W

Figure 11.10: Comparison between standard deviation in each set of samples.

−60 −40 −20 0 20 40 600

0.57

1.13

1.7

2.26

2.83

3.4

3.96

4.53

5.09

5.66

6.23

Reference measurement [A]

Difference

[A]

Discrete UDiscrete WPLD UPLD W

Figure 11.11: Comparison between the maximum error in each set of samples.

57

−60 −40 −20 0 20 40 60

20

30

40

50

Reference measurement [A]

Supply

current[m

A]

Discrete DCDiscrete ACPLD DCPLD AC

Figure 11.12: Current from 27 V supply.

−60 −40 −20 0 20 40 60

0

1

2

3

4

5

6

Reference measurement [A]

Supply

current[m

A]

Discrete DC

Discrete AC (50 Hz)PLD DC

PLD AC (50 Hz)

Figure 11.13: Current from 5 V supply.

58

−60 −40 −20 0 20 40 60

15

16

17

18

19

20

Reference measurement [A]

Supply

current[m

A]

Discrete DC

Discrete AC (50 Hz)

Figure 11.14: Current from 3.3 V supply.

−80 −60 −40 −20 0 20 40 60 80

0.6

0.8

1

1.2

1.4

Reference measurement [A]

Supplied

pow

er[W

]

Discrete DCDiscrete ACPLD DCPLD AC

Figure 11.15: Total power calculated by multiplying the nominal voltage at eachpower rail by its current as used by the current measurement circuitry.

59

instance when measuring 25 A at 50 Hz, which is also shown in the graphs.

11.4 Deadband timing

Initial tests, using the Arduino to generate inputs and measuring the FPGAoutputs worked well. Deadband timing was on point as specified and both theoutput signals to each gate driver and the DIR outputs worked as expected whena saturation signal was introduced at different points in time. When connectingthe prototype board to the drive however, several problems were encountered.

First of all, the pinout for one of the transistors used in the high side driverwas erroneously defined in the computer aided design (CAD) software causingmalfunctions and damaged power MOSFETs. After having replaced those andrewired new high side driver transistors, there were problems with how theboard reacted on saturation.

Due to time constraints and since deadband timing was not a project objec-tive from the start, the version with FPGA controlled deadband was not fullycompleted. By disconnecting the measurement transformers from the powerMOSFETs, the behaviour of the FPGA setup could be visualized without theinfluence of the faulty saturation functionality.

Figure 11.16 shows an overview of the gate voltages in one half-bride togetherwith the voltage at the coil terminal in the unmodified drive. Figure 11.17 showsthe same when deadband is controlled by the FPGA and uses the modified gatedriver circuitry.

The deadband was set to 200 and 260 ns when driving the coil terminal highand low respectively. This is longer than the analogue deadband measured inthe discrete implementation but it is safer to err on the longer side. With themodified gate drivers, this might still not have been enough.

The reduced drive strength from removing the MOSFET in the low sidedriver is clearly a problem, with increased fall times as a result, compare Fig-ures 11.18 and 11.19. Even though the capacitor is removed from the drivercircuitry, the gate capacitance still has a big effect on switching times. Theslow turn-on of the N-channel MOSFET, which is used as part of the analoguedeadband, is still noticeable, see Figures 11.20 and 11.21. Another effect is thatthe switching of one MOSFET clearly affects the other.

60

1: DSC from discrete logic

3: N-channel gate voltage

2: P-channel gate voltage

4: Voltage at coil terminal

Figure 11.16: Gate and coil voltages in the unmodified drive.

1: BCKs from FPGA

3: N-channel gate voltage

2: P-channel gate voltage

4: Voltage at coil terminal

Figure 11.17: Gate and coil voltages with FPGA controlled deadband and mod-ified gate drivers.

61

1: DSC from discrete logic

3: N-channel gate voltage

2: P-channel gate voltage

4: Voltage at coil terminal

Figure 11.18: Coil voltage going high in the unmodified drive.

1: BCKs from FPGA

3: N-channel gate voltage

2: P-channel gate voltage

4: Voltage at coil terminal

Figure 11.19: Coil voltage going high with FPGA controlled deadband.

62

1: DSC from discrete logic

3: N-channel gate voltage

2: P-channel gate voltage

4: Voltage at coil terminal

Figure 11.20: Coil voltage going low in the unmodified drive.

1: BCKs from FPGA

3: N-channel gate voltage

2: P-channel gate voltage

4: Voltage at coil terminal

Figure 11.21: Coil voltage going low with FPGA controlled deadband.

63

Part III

Evaluation

12 Evaluation

12.1 Performance

12.1.1 Logic

Tests with the basic implementation were successful with equal or better re-sults than the discrete implementation both in terms of measurement accuracyand power consumption. The difference is however too small compared to theerror margin in the characterization measurements to establish that one im-plementation is an improvement over the other. It is however clear that theircharacteristics are very similar.

The reaction times are increased with the FPGA implementation but notenough to increase current consumption noticeably. The propagation time isstill shorter than the fall time of the saturation detection comparators. Powerconsumption is however shifted towards the 3.3 V supply.

12.1.2 Gate drive

The modified gate drive was not fully tested due to the problems encounteredwith the deadband version of the logic. The tests without load in terms oftransformer coils however show that the simplifications done were excessive.The removal of the MOSFET in the low side drivers and the resulting reductionin switching speed somewhat defeats the purpose of adding deadband control.This simplification attempt took too large a step at once.

A better approach to implement deadband control would have been to simplysplit up the DSC signal into a high side and a low side control. This could achievesome simplification since it renders one of the NAND-gates in the low side driverredundant. The MOSFET used in the driver circuitry has a significantly smallergate capacitance and lower threshold voltage than the power MOSFETs andshould be able to be driven by the FPGA output directly. The three quadNAND-gate ICs in the gate driver circuitry could therefore likely be replacedby one hex inverter IC as in the modified circuit. This was however not tested.

Another possible approach to maintain quick switching edges is to use thesame topology as for the high side driver connected to the 5 V supply.

12.2 Cost

To evaluate the cost of the different implementations, the lowest prices for theindividual components in each case were taken from Digi-key, Mouser, Farnell,Arrow and Future Electronics. For discrete components, which are purchased atlarger quantities, the prices at 100.000 units were taken. For integrated circuits,the price quotes at 1000-2500 units were used.

To estimate the cost of mounting the components on the PCBA, a cost modelbeing developed internally at Inmotion was used. This takes into account thecomponent package type and the type of package it is supplied in (tape & reel,

64

Part Type Components Cost Mounting Total cost

LogicDiscrete

Single 40 14.52 11.28 25.80Dual 76 28.48 21.45 49.93

FPGASingle 16 17.40 5.44 22.84Dual 19 17.44 5.80 23.24

ClockCrystal 5 2.83 0.68 3.51

Oscillator 1 8.39 0.2 8.59

Gatedrive

DiscreteHigh 42 5.00 5.88 10.58Low 36 4.52 6.57 11.09

ModifiedHigh 36 4.92 4.86 9.78Low 8 0.7 1.59 2.29

Integrated Both 12 27.53 5.22 32.75

Table 12.1: Cost estimation in SEK for different implementations. Successfultests were performed with FPGA logic, crystal clock and discrete gate drivers.This would implicate a cost increase of 0.55 SEK for the single drive and a costreduction of 23.19 SEK for the dual.

tray etc.). The prices vary with the size of the batch, the number of placementsin each batch, the number of different types of components, and the productioncountry. The values used here are a rough estimate for production in Swedenwith 50.000 component placements per batch.

Table 12.1 sums up the cost estimates for both purchase and mounting. Thenumbers for the gate drive circuitry are for a single, three phase drive since theprice in these calculations would scale linearly to a dual, six phase drive.

While these cost estimates are rough, they show that the total price for themore generic components used in the discrete implementation is lower despitethe larger amount. The price of the FPGA is much higher and constitutes almost90% of the component cost for the FPGA versions. The rest are supportingcomponents like decoupling capacitors. For the dual version however, the costis almost the same for the FPGA version while the discrete implementationnearly doubles and exceeds the cost of the FPGA version.

When taking the mounting cost into account, the cost of the FPGA versionis almost as low as the discrete, depending on the choice of clock source. Thediscrete logic used today does not require a clock source.

No integrated gate driver solution matching all requirements was found.Through the cost estimation for the one coming closest, it is clear that theincreased price for that particular one is not weighed up by a reduction inmounting cost.

12.3 Area

Comparing the PCB area used by the different implementations is not com-pletely trivial. The prototype uses a two layer PCB with all componentsmounted on one side. For bulk decoupling capacitance it has a pair of throughhole tantalum capacitors. Although the component layout was focused on goodelectrical characteristics, the ability to be soldered by hand was more importantthan compactness.

The current measurement logic of the existing drives on the other hand uses

65

only surface mount components, some of which are mounted on the bottom sideof the eight layer PCB, enabling a much more compact design.

These differences were taken into account, especially the possibility to placedecoupling capacitors on the bottom side underneath the FPGA, when studyingthe Gerber files for the prototype and the existing product PCBs.

From this, it is reasonable to be able to decrease the area used by the logicfrom 9-10 cm2 for the single motor drive to less than 5 cm2. If the NAND-gatesin the gate driver circuitry were to be replaced by one inverter IC as mentionedabove in Section 12.1.2, this would open up an additional 1.5 cm2. Much of therouting between components would be simplified in an FPGA solution since itis handled inside the IC although is still needs to interface other parts on thePCB.

12.4 Safety considerations

In a system like this, functional safety is of utmost importance. The motorcurrent measurement is a crucial part of this and care should be taken not tointroduce any risk of dangerous failures.

12.4.1 Metastability and race conditions

During initial tests, it became very apparent how problems with unexpectedbehaviour can arise from asynchronous inputs to a synchronous PLD.

When selecting device, the setup and hold times were not studied in depth.At first, the erratic behaviour was thought to be caused by setup time violationcausing metastability. Judging only by the setup time, another FPGA seemed tohave a big advantage. The Altera MAX10, which also fulfills the requirementsin Section 5.2, has a negative setup time. This device is newer but was notchosen since it costs five times more and the only non BGA package is a bigger144 pin TQFP instead of a 100 pin. The 2000 LE of the smallest chip in thefamily is also excessive for the task at hand.

However, the time frame where metastability can occur is between the setuptime and the hold time. For the MachXO, setup time is 1.8 ns and hold time is-0.3 ns. This means that data input must be stable between 1.8 – 0.3 ns beforethe clock edge. If the data changes during these 1.5 ns the output of this LE maygo into metastability with uncertain and slow results. For MAX10, the setuptime is -0.75 ns but the hold time is 1.18 ns rendering the forbidden time frameshorter at 0.43 ns, this time after the clock edge, but not zero. A forbidden timeframe cannot be completely avoided and with inputs having edges controlled byother timing elements than the PLD clock, transitions during this time willoccur.

Fortunately, when sorting out input synchronization and changing to morerobust state encodings, the asynchronous inputs and different clock domainswere no longer a problem. The prototype worked, at least in the simple imple-mentation without deadband control.

This implies that the real problem was not the metastability itself but ratherthe handling of the inputs where it may occur. The state encodings in the firstversions were not free from race conditions.

Analysing state encodings and transitions should have been a higher priorityearlier in the design process. The five states in the state machine worked since

66

the off state was coded as 100 and the other states cycled though 000, 001, 011,010 and back to 000. When HDE has gone high after start-up, control statetransitions have a Hamming distance of one and are very robust, unless ENLgoes low during Back or HDE goes low. The saturation handler in the simpleversion has only two states and can be coded with one single bit.

For the larger state machines, extra states should have been introduced toenable gray encoding and ensuring correct transitions at the expense of addeddelays. Another hindsight observation is that the different deadband times forthe P- and N-channel MOSFETs were superfluous.

12.4.2 Clock oscillation

The likelihood of the clock stopping during operation is fairly small. However,the consequence of such a scenario if it were to happen during forward or backis that the FPGA would fail to react on a saturation signal, destroying theMOSFETs. To mitigate this, some sort of watchdog timer could be used pullingdown HDE and thereby disabling the high side gate drivers, if not toggled orreset frequently enough.

There is much unused logic in the FPGA with utilization as low as 14 %for the three-phase version tested here and and 38 % for the current deadbandimplementation. Some of this unused logic could easily be employed to reset awatchdog of some sort. Some external hardware, which does not depend on theFPGA clock, would however be required.

Another option is to use the same clock as one of the MCUs. This transfersthe problem of guaranteeing clock oscillation to the MCUs whose clock sourcesare already supervised by internal and external watchdogs. The difficulty withthis solution, as mentioned before, is that it puts high requirements on therouting and constrains the design. To avoid affecting the oscillation of thiscrystal the signal cannot be taken directly from the crystal but would need tobe sent out by the MCU, using up some of its capacity.

A benefit to this option on the other hand, besides that no new hardwareis required, is that state transitions become more deterministic since they arelimited to a few instances during each period of the FPGA clock reducing therisk for problems with metastability. The edges of the saturation signals willhowever still occur along the whole period.

Timing analysis from compiling the tested VHDL code shows that the testedsetups can operate to just above 120 MHz. This is lower than the operatingfrequency of the MCU which is 200 MHz. The crystals however oscillate at 20MHz and are stepped up using internal PLLs. This might open up for sendingout an intermediate frequency. If not, the 200 MHz can still be divided in halfonce or twice down to 100 or 50 MHz to use as a clock source for the rest ofthe FPGA. Timing analysis showed this to be feasible but it was not tested inpractice.

Still, the watchdogs for the MCUs in their current product will not turn offthe current measurement gate drivers. They will force the unit into a safe statebut the MOSFETs might still break. This is true for the tested setup withoutexternal watchdogs as well. Pulse lengths of ENLs and BCKs are still supervisedand so is the toggling of the DIR signals. This is not quick enough to save theMOSFETs but will put the system in a safe state in case of a malfunction.

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12.4.3 Redundancy

Redundancy is important in safety critical systems, making sure that a fault isdetectable and does not result in any dangerous situation. The discrete imple-mentation with its separate ICs has a form of redundancy built into it. If onecomponent fails, the sum of currents will not be close to zero and the failureis detected. This is no longer a viable method viable to diagnose the currentmeasurement logic when it is in one single chip. A failed FPGA would result inall current measurements being zero. For the same reason it might be an ideanot to use one single IC for the logic gates in the low side driver circuitry.

Fortunately there are other means of detecting a fault. The sum currentmay not be able to detect a total failure of the logic but it will still detecta failure of the analogue measurement if the rest of the current measurementcircuitry is functional. The supervision of pulse lengths supervises both theFPGA and the MCU generating them. The toggling of DIR after a prolongedFWD pulse supervises both the FPGA and the gate drivers. These checks arealready in place and should be kept if changing the logic implementation to aprogrammable one. Together they constitute the necessary means of detectinga faulty current measurement module. The PLD implementation can also eas-ily interface these supervision functions without requiring big changes in thathardware or software.

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13 Summary

In this thesis, the functionality and control of a specialized current measurementmethod used in high power automotive applications was analysed and recreatedwith a PLD. The possibility and the need for changing other parts of the sys-tem when changing logic implementation was also analysed and to some extenttested.

Although the prototype in this first round of tests was far from perfect, itdid work, with similar or better performance than the discrete implementation.Reaction times on the nano second scale did not have a noticeable effect onpower consumption. The tests gave much insight on the workings of the systemand on working with programmable logic in practice as well as what to improveupon.

A version with programmable deadband compensation was also developedusing the same hardware. Although a fully functioning version was not quiteachieved, it was shown to be plausible given some extra development time,increasing flexibility in the design of gate drivers if completed.

13.1 Conclusions

The main consideration when moving to programmable logic is the change fromasynchronous to synchronous. A thorough analysis of input signals, states andoutput signals is required if the PLD shall interface asynchronous inputs. It isimportant that the encodings are free from race conditions to guarantee robustperformance.

This is the main flaw discovered in the configurations tested in this thesis.This was somewhat sorted out and it was made to work but a rework with thisin mind when designing the structure from the ground up is suggested. Statemachines with an odd number of states were ill advised since it renders statetransitions with larger Hamming distance necessary. Unused state encodingscould have been used as duplicate, intermediate states. This would increasethe minimum time within a state but could ensure safer transitions. Otheroptimizations can also be done such as using the same deadband time for theP- and N-channel MOSFETs, reducing complexity without really affecting per-formance.

While the part in itself is automotive grade, the use here with asynchronousinputs needs further analysis and testing. Simulation alone is not enough tofully evaluate performance with more than one clock domain. While the needto delay states as mentioned in Section 7.2.1 was caught in code simulation, theissues with asynchronous inputs were not discovered until performing tests onactual hardware.

When choosing a suitable device for the application, the main obstacleswere finding a device of suitable size with a 3.3 or 5 V supply and preferablyautomotive classification. With the quick development of the PLD market,obsolescence is a significant risk and the trend is towards increased capacityand operational frequencies at lower and lower supply voltages.

The device chosen and tested here does fulfil the requirements to a reasonableprice and will be in high volume production for at least ten more years. This mayor may not be enough to introduce it into a system in development dependingon the intended lifespan of the product. While this type of devices are highly

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flexible due to their configurable nature and standard footprints, some of thepins such as supply and programming pins are fixed, which can complicate afuture change of device or second sourcing.

The automotive industry is generally cautious about introducing new com-ponents and solutions where there are older and proven technologies that work.In this particular system, which has a lot of self checks with built in redundancy,an implementation in programmable logic is still very much possible. The lossof redundancy when placing much of the logic in one single IC is covered byother hardware and software safety mechanisms. This opens up for saving PCBspace and simplifying CAD work without increasing component cost. It doeshowever have a couple of caveats when operation is critical which should be keptin mind when configuring it.

13.2 Future work

Apart from the suggested rework of states and encodings a few topics for futurework on the subject are suggested.

13.2.1 Clock source

Despite the longer delays in the synchronized programmable logic version of thecircuit, power consumption increase on the 27 V rail was not seen. Perhaps theoperational frequency of 50 MHz was unnecessarily high.

If programmable deadband is not used, the constraints on timing accuracymay also be alleviated. Tests should be performed using the internal oscillatorof the PLD. If performance is acceptable, this option reduces the cost beneaththe discrete implementation even for the single drive.

13.2.2 Added functionality

A deeper analysis on whether or not programmable deadband and a possibilityfor sharper switching edges is something that is actually sought after shouldbe done. Sharper switching edges are good in terms of efficiency but may beunwanted in terms of EMC. Deadband does increase complexity considerably.There may also be other functionality that can be incorporated in the unusedparts of the FPGA if programmable deadband is not desired.

13.2.3 Programming

More investigation into the possibilities of configuring the device in productionshould be done.

13.2.4 Reliability

Comparison of failure in time (FIT) values for the components of the differentimplementations could help evaluate if the tested prototype constitutes a higheror lower risk of malfunctioning. Analysis of the PLD behaviour during systemboot-up is also a suggested.

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[14] Per-Erik Tegehall. Kravspecificering och verifiering av miljöskydd och livs-längd av lödfogar till komponenter, September 2016. Smartare Elektron-iksystems SUMMIT.

[15] Intel Corporation. MAX 10 FPGA Device Datasheet, 2017.

[16] Lattice Semiconductor Corporation. LA-MachXO Automotive Family DataSheet, 2007.

[17] Ramon Cerda. Pierce-Gate Crystal Oscillator, an introduction. CrystekCorporation, March 2008.

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