ABCD: Booleanizing Continuous Systems for Analog/Mixed...
Transcript of ABCD: Booleanizing Continuous Systems for Analog/Mixed...
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 1/19
ABCD: Booleanizing Continuous Systems for Analog/Mixed-Signal
Design, Simulation, and Verification
Aadithya V. Karthik,Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko,
Robert Brayton, and Jaijeet Roychowdhury
EECS Dept., The University of California, Berkeley
TAU 2014, Santa Cruz
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 2/19
Surrounded by Digital Logic
Example: SERDES
Analogparts
PLL
CDR I/O
The Problem: AMS Verification
• Want to verify complete system– e.g., eye opening height > 1V?
• Proof or counter-example needed
>1V
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 3/19
Our approach: “Booleanize” the analog parts
Best verification tools = all Boolean, no continuous
Digital componentsVerification tools accept
Analog components
Challenge: Analog models Digital models+Continuous Boolean
(don't mix)(don't mix)
SAR-ADC Boolean T/Happroximation Boolean
comparatorapproximation
Boolean DACapproximation
ALLBOOLEAN
Formal verification, high-speed simulation, test pattern generation, ...
ABCD: Booleanapproximation
… for the full combined system!
Fast
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 4/19
ABCD: Boolean, but Accurate• What is “accurate Booleanization”?
discretizedckt. signals
disc.i/p
Boolean Logic
disc.time
disc. o/p
Boolean state
More bits, better accuracy
010
110
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 5/19
Prior work: ABCD-L (DAC 2013)
LinearLinear Analog Circuit
Purely Boolean Model
ABCD-L
Linearize
Bit Sequence
Example: Channel + Equalizer
Works only for linear systems!
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 6/19
Introducing ABCD-NL
Non-LinearAnalog Circuit
Purely Boolean Model
ABCD-NL
How ABCD-NL works1
Results: Charge pump, ADC, DAC, etc.2
End user applications3
High-speed simulation, formal verification, test pattern generation, etc. for non-linear AMS ckts.
Rest of this talk
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 7/19
ABCD-NL Models are FSMs
Non-LinearAnalog Circuit
Purely Boolean Model
ABCD-NLFSM
• Finite number of states
• Arcs denoting state transitions– Each arc: ip/op pair
• Purely Boolean form
1100 0010
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 8/19
1
Key idea: DC, TRAN FSM states
(DC input → DC output)
Non-Linear Analog Circuit
DC Eventually settles and never changes
• DC FSM states w/ loops
• Multiple such DC states – Capture different DCOPs
• DCOPs don't change instantly
• TRAN FSM states– Between each pair of DC states
• Purely Boolean Model
TRAN01
Starts at DC0 and eventually settles at DC1
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 9/19
Booleanizing a Charge Pump (1/3)
Do SPICE simulations1Discretize Vup, Vdown using 1 bit each, Vout using 5 bits
Exactly 1 high at any time
UP highDOWN low
UP lowDOWN high
Both high Both low
Active
Dormant
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 10/19
Booleanizing a Charge Pump (2/3)
Analyze SPICE waveforms2
Build “Analog Transition Table”
TRAN path DC3 to DC2: up (down) goes 1→0 (0→1)
Total time 20.63ns, o/p starts @ 31, becomes 30 @ 213.6ps, ….
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 11/19
Booleanizing a Charge Pump (3/3)
Analog Transition Table → Boolean Model3
<ipbv> <cstbv> <opbv> <nstbv>
• i/p: 2-bit encoding
• o/p: 5-bit encoding– 32 levels in [0, Vdd]
• FSM state: 19 bits– Lots of don't cares (75%)
Registers
disc.i/p
Combinational Logic
disc.time
disc. o/p
Boolean state
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 12/19
ABCD-NL: The 3-Step Algorithm
Do SPICE simulations1
Analyze SPICE waveforms2
Build “Analog Transition Table”
Analog Transition Table → Boolean Model3
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 13/19
Simulating the Boolean Model
Map back to analog
Simulate FSM(Fast, Table-lookup)
Discretize into FSM symbols
i/p waveform
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 14/19
Charge Pump: Long PRBS
Non-linear analog dynamics accurately captured over long time-frame
~10x Speedup, even in Python
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 15/19
Circuits Successfully Booleanized
Charge pump
Delay line
EqualizerPower grid
SAR-ADC
I/O signaling system
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 16/19
“Booleanize”(manually)
Safety vs Liveness
AMS Verification: The Flow
Boolean Modelvia ABCD-NL
AMS System to be verified
Property to be verified
“Booleanize”(manually)
Input Constraints
ABC
Proof or Counterexample
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 17/19
Example: Verifying a Signaling System
What is the max bitrate that can be sustained?
Ans: 2.56Gbps
ABC
Specification
ABCD model
verification engine(Bob Brayton's group)
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Aadithya V. Karthik ([email protected]) Mar 2014, TAU, Santa Cruz 18/19
Summary
• AMS modelling, verification a challenge: 20% bugs
• Our approach: Booleanize AMS Components– ABCD-L: for linear AMS systems– ABCD-NL: for non-linear systems
• Applied to A/D and D/A converters, delay lines, charge pumps, equalizers, filters, on-chip power grids, etc.
• Accurate and Scalable
• Applications– High-speed simulation– Formal verification (in conjunction with ABC)