A1 Dirks Paper

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Applying Synopsys Physical Guidance methodology to

address complex 28nm design challenges

Jrgen Dirks

LSIMunich, Germany

www.lsi.com

ABSTRACT

With ever shrinking geometries in latest technology nodes the cell placement is a critical factorthat affects routing, thus a non-optimal placement and routing negatively impacts timing closure

and power consumption. A methodology to overcome these issues is the Synopsys Physical

Guidance (SPG) flow, which was added to the physical design tool suite to get close correlationbetween floor plan aware synthesis in Design Compiler and layout in IC Compiler.

After a brief introduction to the Synopsys Physical Guidance methodology the present paperoutlines the usage within flows applied to real-life designs. An SPG design flow is presented

which covers the use of different tools for synthesis, test insertion and layout, showing the flexi-bility allowing to incorporate other 3

rdparty tools. Already within the synthesis environment

aspects like general routablility improvements are highlighted. Solutions to specific congestion

issues as well as power consumption reduction are shown and results compared to non-SPG syn-thesis and layout flows.


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SNUG 2013 2 Applying Synopsys Physical Guidance methodo

Table of Contents

1. Introduction .......................................................................................................................... 3

2. SPGfeatures and capabilites ............................................................................................. 3

2.1 Standard SPG Flow ............................................................................................................... 3

2.2 Physical Guidance ASCII handoff ........................................................................................ 4

3. Design specifics and challenges ............................................................................................ 5

4. SPG in the flow .................................................................................................................... 6

5. Results .................................................................................................................................. 8

6.

Conclusions ........................................................................................................................ 10

7. References .......................................................................................................................... 10

Table of Figures

Figure 1: Standard SPG flow with DC and ICC. ............................................................................ 4

Figure 2: SPG flow with 3rd

party DFT using ASCII. .................................................................... 5

Figure 3: Top level floorplan of design under investigation. .......................................................... 6

Figure 4: SPG flow used in the present design. .............................................................................. 7

Figure 5: Congestion maps in DC-G and in ICC. ........................................................................... 9

Table of Tables

Table 1: Comparing power values with and without SPG. ............................................................. 9


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1. Introduction

After providing a brief overview about features and advantages of the Synopsys Physical Guid-

ance methodology this paper describes the usage of the flow in real-life designs. The chosen ex-

amples faced different challenges in the area of routing congestion, block size requirements and

most important power consumption.

2. SPGfeatures and capabilities

Before SPG there was no method to send the placement done by Design Compiler (DC) in

Topographical Mode to the backend. Starting with the release 2010.03 Synopsys provided thePhysical Guidance flow that allows to forward the placement to IC Compiler (ICC). The SPG

methodology is activated by the command compile_ultra spg.The transfer of the placement

to ICC is normally done via the binary netlist format .ddc. This file format also contains design

constraints, incl. derating factors and scenarios, but no variable definitions. Besides using .ddc

there is another way to transfer the data using a Verilog netlist together with std cell placement

information (DEF or Tcl format). Taking the original placement allows for better correlation andsaves runtime in ICC, because the initial placement step can be skipped. Time savings are signif-

icant if the placeable instances are numbered in millions. Along with SPG, improvements in QoR

were introduced, including the areas of high fanout net synthesis and timing optimization. Onemore interesting feature is the incremental port placement, in case their locations are not deter-

mined in the floorplan. Although the topographical mode is part of DC-Ultra, SPG is part of the

add-on license DC-Graphical, which also allows congestion analysis and optimization. Startingwith the release 2012.06 congestion analysis and optimization is automatically executed within

the SPG flow (-spgoption). Other features of DC-Graphical are the ICC-DP link and MCMM

(multi-corner, multi-mode) optimization which is not part of our evaluation.

2.1 Standard SPG Flow

A typical script for Design Compiler:read_verilog ...

source constraints.tcl

extract_physical_constraints top.def

compile_ultra scan spg

insert_dft

compile_ultra scan spg -incremental

change_names rules verilog hier

write format ddc hier out top.ddc

A typical script for IC Compiler afterwards:read_ddc top.ddc

read_def top.def

restore_spg_placement

place_opt spg


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In ICC the top-level DEF file is read, which does not contain the std cell placement. The std cell

placement information is stored in the .ddc file. The command restore_spg_placementis only

used to be able to view the placement before the next optimization steps (place_opt spg).

Figure 1: Standard SPG flow with DC and ICC.

2.2 Physical Guidance ASCII handoff

This method is suitable when test logic is inserted using 3rd

party DFT tools. As shown in figure2

the flow contains an additional incremental compile in DC after test insertion is complete. Anetlist containing the test logic, a scandef file, and the constraints are handed over to DCT for an

incremental run. In order to perform an incremental SPG compile, the std cell placement infor-

mation of the first compile is required, too. But because the test tools typically do not handle

DEF files, the ICC-DP link is used instead. This link starts ICC from within DC, and then allowsusing thewrite_defcommand to create a standard cell placement dump in DEF format.

DC is placing and optimizing the newly added test logic during a compile_ultra incrstep.

After the incremental compile an updated standard cell placement dump needs to be created, this

time including the test logic.All files (netlist, placement dump and scandef) can be handed over to ICC in ASCII format.


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SPG flow with 3rd

party DFT using ASCII

Figure 2: SPG flow with 3rd

party DFT using ASCII.

3. Design specifics and challenges

The design described in the present paper comprises a complexity of 140 million NAND2-gates

prior to test insertion and layout. The datapath logic in this design shows a width of several 1000

bits, and performs intensive algorithmic functions. One big challenge with this type of designs isrouting congestion.

In order to allow handling of the design with reasonable turn-around times and to achieve pre-dictable results in the different phases of the development process, the chip is divided into 28

hard macrossome of them instantiated multiple times. This numerous blocks with different

design content, allowed us to explore the effectiveness of the SPG methodology.The major focus for the present design is power consumption. Due to unusually high switching

activities, a main frequency of 500MHz and the overall complexity, it is quite challenging to stay


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close to the target budget; therefore every possible step to reduce the power consumption needs

to be taken into account.

A side effect of the high switching power is that a huge amount of decoupling capacitance

(DCAP) on the die is required to keep the voltage drop within a require range. Another aspect of

block size is the effect of long wires due to distance and the corresponding net capacitance whichincreases the power consumption of the blocks which have low utilization and cells are spreadtoo far apart. This means that every piece of extra area gain during hard macro design closure is

helpful.

The top level floorplan as currently used is shown in figure3.

Figure 3: Top level floorplan of design under investigation.

4. SPG in the flow

For the design used as example in the present paper the following steps had to be done:

1. Synthesis using Design Compiler

2. Test insertion using a mix of different in-house and 3rd

party tools

3. Place and route using Synopsys IC Compiler


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Figure 4: SPG flow used in the present design.

It means that the Synopsys tool suite is left at one point and re-entered at a later point. This ap-

proach is supported by providing ASCII based handover capabilities within the Synopsys Physi-

cal Guidance environment. One concern was that test related database changes like the connec-tion of SCAN chains, the addition of a local SCAN compressor or the insertion of memory BIST

logic would not be covered by the SPG flow and therefore would cause place and route issues

within ICC. But it was found that through an incremental placement step the tools took care of

the new test cells, and place and route finished without major differences compared to pre-testruns. The required size of hard macro floorplans post-test was determined by a few trial runs of

representative blocks prior to test insertion and then adding a certain percentage of growth. Such

a value of course depends on design content (e.g. RAMs).

There are different possible ways to exercise the incremental placement step. One method is to

read the test inserted netlist into Design Compiler and perform acompile incremental

step after providing the original placement information and adjusting the timing constraints (see

Figure 2). Another way is to directly move into ICC with the post-test database, provide theoriginal placement information and updated timing constraints and then perform a

place_eco_cells -unplaced_cellscommand. In the present design the latter approach was

chosen and the functional cell placement as it comes out of Design Compiler was even frozen notto disturb any of the good results.

For hard macro closure according to our chosen methodology there is another step required

which is the pre-placement of IO registers right next to the ports. Inside Design Compiler thisapproach has limitations so it had to be done after a first compile step, using the commandmagnet_placement.


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Figure 5: Congestion maps in DC-G and in ICC.

The comparison of power results with and without using SPG is shown in Table1. It has to be

mentioned that in the runs without SPG there was significant effort spent to reduce power by

other means (e.g. special handling of high fanout nets or clock skewing for specific timing

paths). Such steps were not performed in the SPG runs. This dedicated work on specific itemsalso explains why in the 2 listed cases power consumption came out slightly higher than after a

pure SPG flow

Table 1: Comparing power values with and without SPG.

Power w/o

SPG (W)

Power with

SPG (W)

Main content Size re-duction

Comments

HM1 1.41 1.39 FFT

HM2 2.85 2.82 Multiply, FFT

HM3 2.55 2.46 Multiply, FFT 11%

HM4 1.83 1.46 Multiply

HM5 2.55 2.65 Arithmetic Power increase with SPG

HM6 1.89 1.82 Data managing 8%

HM7 2.24 2.20 Arithmetic


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SNUG 2013 10 Applying Synopsys Physical Guidance method

6. Conclusions

The Synopsys Physical Guidance flow can help with various optimization aspects. These rangefrom routability within given floorplan constraints to area and power reduction. The amount of

improvements depends on the content of the design under consideration.

Although we deviated from the recommended Synopsys flow the correlation seen was still verygood in terms of routability and timing.

A major advantage in engagement models using different design groups for synthesis versus lay-

out comes with the fact that placement based results correlate well from start to end so early

assessment within the synthesis environment is possible with the given flow.

As an outlook the use of SPG flow in conjunction with other optimization capabilities like Des-

ignWare minPower should be examined.

7. Acknowledgements

I want to thank the LSI Front-End and Back-End teams for their effort spent and Thomas Haase

from Renesas for his valuable feedback during paper reviews. Special thanks go to the localSynopsys support team, Rolf Ferner and Frank Schlegel, for their support to create to this paper.

8. References

[1] Design Compiler User Guide 2012.06, June 2012

[2] Design Compiler and IC Compiler Physical Guidance TechnologySolvNet Article 031198, November 2012

[3] Advanced Design Partitioning with IC Compiler Leveraging Physical Synthesis

SNUG Boston 2012

[4] Improving Productivity of Synthesis and P&R with Synopsys Physical Guidance (SPG) Technology

SNUG Austin 2011

[5] Accelerating Design Closure with Synthesis Physical Guidance (SPG) Flow - ST-EricssonSNUG France 2011
http://www.synopsys.com/news/pubs/snug/2012/austin/fa1_paper_randall.pdfhttp://www.synopsys.com/news/pubs/snug/2012/austin/fa1_paper_randall.pdfhttp://www.synopsys.com/news/pubs/snug/austin2011/pc2_samineni_paper.pdfhttp://www.synopsys.com/news/pubs/snug/austin2011/pc2_samineni_paper.pdfhttps://www.synopsys.com/news/pubs/snug/france2011/b1_najmeddine_paper.pdfhttps://www.synopsys.com/news/pubs/snug/france2011/b1_najmeddine_paper.pdfhttps://www.synopsys.com/news/pubs/snug/france2011/b1_najmeddine_paper.pdfhttp://www.synopsys.com/news/pubs/snug/austin2011/pc2_samineni_paper.pdfhttp://www.synopsys.com/news/pubs/snug/2012/austin/fa1_paper_randall.pdf

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