1

A Verilog-A Compact Model

for Negative Capacitance FET Version 1.0.0

Muhammad Abdul Wahab and Muhammad Ashraful Alam

Purdue University

West Lafayette, IN 47907

Last Updated: Oct 02, 2015

Table of Contents

1. Introduction ...................................................................................................................................... 2

2. Terminal Voltages and Parameters List ...................................................................................... 2

2.1. Terminal Voltages .................................................................................................................. 3

2.2. Parameters List ....................................................................................................................... 4

3. Model System and Equations ....................................................................................................... 4

4. Device Characteristics ................................................................................................................... 6

5. Summary ......................................................................................................................................... 9

References .............................................................................................................................................. 9

Appendix ................................................................................................................................................ 11

A. Transient performance ............................................................................................................ 11

B. Parameters of Conventional MOSFET ................................................................................. 12

C. HSPICE toolkit ...................................................................................................................... 12

D. Simulating HSPICE netlist .................................................................................................. 12

E. Checklist for model analysis ................................................................................................... 12

2

1. Introduction

Continuous downscaling of the physical dimensions of MOSFET has helped to increase the

transistor density, and improved the performance of the integrated circuit (IC). It has been

difficult however to reduce the supply voltage (VDD) significantly below 1V without sacrificing the

ON current and the ON/OFF ratio, making it difficult to reduce the power density [1], [2]. The

increasing thermal resistance of the novel transistors (FINFET, SOI-FET, or Gate-all-around

(GAA) FET has further acerbated the problem. Indeed, temperature rise due to self–heating

(Δ𝑇 = 𝑃 × 𝑅𝑇𝐻) affects the reliability of the transistors [3], [4]. Therefore, any scheme to scale

down the bias voltage has the potential to reduce power consumption and self-heating

significantly. One of the options to reduce VDD involves improving the sub-threshold slope (S) of

a transistor by overcoming Boltzmann limit (S=60 mV/dec). Negative capacitance (NC) dielectric

such as ferroelectric (FE) material improves S through amplification of gate bias [5]–[12] in a

NC-FET (Fig. 1(a))). In this work, we develop a verilog-A compact model of a generic NC-FET

[11], [12]. This manual discusses the theoretical model, the circuit representation, and results

through illustrative examples of the NC-FET.

2. Terminal Voltages and Parameters List

Fig. 1 (a) The schematic diagram describes the geometry of the NC-FET. (b) Symbolic representation of the NMOS NC-FET. (c) The NC dielectric is represented as a dependent voltage source (VFE) for HSPICE simulation. The NC-FET is represented by two series-connected components, i.e., the NC dielectric and the MOSFET.

Fig. 2 (a) Ferroelectric acts as an additional gate dielectric capacitor with the conventional

MOSFET. (b) All the parasitic components: source resistance (RS), drain resistance (RD), gate-

S D

G(NC)

B

FE

OXG(MOS)

BDS

G (NC)

(a) (b)

VFE

BS D

NMOS

G (NC)(c)

G (MOS)

BDS

G (NC)

B

G (NC)

DSRS

RDS’ D’

G (MOS)CFE

COV COV

(a) (b)

CFE

G (MOS)

3

source overlap and fringing capacitance (COV) and gate-drain overlap and fringing capacitance

(COV) are included in the analysis.

2.1. Terminal Voltages

The NC-FET has two components: (i) NC dielectric and (ii) the conventional MOSFET.

(i) NC dielectric: The NC dielectric is treated as an external capacitor connected in

series to the gate of the conventional MOSFET. For the DC analysis, the inclusion of

a capacitor in the gate terminal as an external element cannot provide meaningful

results. Therefore, in HSPICE simulation, NC dielectric element is represented as a

dependent voltage source which is a function of gate charge. The inclusion of the NC

dielectric as a voltage source enables circuit simulation. Using the same concept

multiple layers of NC dielectric as dielectric stack can be considered in the model.

(ii) Conventional MOSFET: The second element is a conventional MOSFET transistor

with drain, gate, source, and body terminals. This model and method work for any

structure (planar, double gate, FinFET, SOI FET, GAA-FET, etc) and model

(MVS/BSIM4/BSIM-CMG/etc) of the MOSFET so long it is supported by the circuit

simulator.

In addition to the standard elements, we introduce a dummy node to both the NC dielectric and

the Conventional MOSFET. Therefore, the NC dielectric is now represented by 3 terminals and

the MOSFET by 5 terminals. The dummy node (as a voltage terminal) exchanges information

regarding the gate charge between the two elements. HSPICE solves the circuit of the NC-FET

self-consistently to compute the unknown variables (voltages, currents, etc). The introduction of

the dummy node for the MOSFET requires access to the source code. The modified source

code of BSIM4 and MVS are provided along with the source code of NC dielectric.

The nodes and corresponding node voltages of the NC dielectric and conventional MOSFET are

defined as follows:

NC dielectric:

Node Description Voltage

ncp Electrode with positive bias V(ncp)

ncn Electrode with negative (or zero bias) V(ncn)

qg_as_v Dummy node to input the gate charge V(qg_as_v)

Conventional MOSFET (MVS/BSIM/etc):

Node Description Voltage

drain Drain voltage V(drain)

gate Gate voltage V(gate)

source Source voltage V(source)

bulk Bulk voltage V(bulk)

4

qg_as_v Dummy node to output the gate charge V(qg_as_v)

2.2. Parameters List

Parameters used in the negative capacitance FET model are listed below. Table also lists the

physical meaning of each parameter.

Math

Symbol

Verilog-A

Symbol

Description Default Unit

𝛼𝐹𝐸 alpha Alpha coefficient of the

ferroelectric

−1.8 × 1011

𝑐𝑚/𝐹

𝛽𝐹𝐸 beta Beta coefficient of the

ferroelectric

5.8 × 1022

𝑐𝑚5/𝐹/𝐶𝑜𝑢𝑙2

𝑡𝐹𝐸 tFE Thickness of the ferroelectric

dielectric

10 × 10−7 𝑐𝑚

For details regarding the physical interpretation of the model parameters, see Ref. [6]–[9].

3. Model System and Equations

We develop the model of the NC-FET [11], [12] by integrating the BSIM4/MVS model [13] of the

conventional short channel MOSFET with the Landau theory of negative capacitor [5]. The

subthreshold swing of a MOSFET is defined as

𝑆 =𝑑𝑉𝐺𝑆

𝑑𝑙𝑜𝑔10(𝐼𝐷)= (

𝑑𝑉𝐺𝑆

𝑑𝜓𝑆) (

𝑑𝜓𝑆

𝑑𝑙𝑜𝑔10(𝐼𝐷)) = 𝑚 × 𝑝

(1)

where, VGS is the applied gate bias, for NC-FET it is VG(NC)-S. ID is the drain current, 𝜓𝑆 is the

surface potential. The body-factor m can be obtained from the voltage divider rule assuming the

gate-source and gate-drain overlap capacitances (COV) have negligible effect on gate charge

(QG).

𝑚 = (𝑑𝑉𝐺𝑆

𝑑𝜓𝑆) = (1 + 𝐶𝑆 (

1

𝐶𝑂𝑋+

1

𝐶𝐹𝐸))

(2)

Landau model for the negative capacitor: The Gibb’s free energy of a ferroelectric material is

represented by a two well energy landscape, as follows,

𝑈 = 𝛼𝐹𝐸𝑄𝐺2 + 𝛽𝐹𝐸𝑄𝐺

4 −𝑉𝐹𝐸

𝑡𝐹𝐸𝑄𝐺 .

(3)

5

The potential (VFE) - charge (QG) relation of the ferroelectric material is represented from eq (3)

as

𝑉𝐹𝐸 = 2𝛼𝐹𝐸𝑡𝐹𝐸𝑄𝐺 + 4𝛽𝐹𝐸𝑡𝐹𝐸𝑄𝐺3 (4)

From eq (4) we can write the capacitance (CFE) - charge (QG) relation of the ferroelectric

material as

𝐶𝐹𝐸 =1

2𝛼𝐹𝐸𝑡𝐹𝐸 + 12𝛽𝐹𝐸𝑡𝐹𝐸𝑄𝐺2

(5)

In this work, negative capacitance dielectric and conventional MOSFET are represented as two

different components. The I-V and C-V of the NC-FET are computed through charge and

potential balance in HSPICE. We represented the ferroelectric dielectric as a dependent voltage

source which is a function of QG. To account this dependency we modified the available verilog-

A models of MVS/BSIM4.

6

4. Device Characteristics

To illustrate the model of the NC-FET, we simulate the performance of the conventional

MOSFET (NCFET with tFE=0 nm) and the behavior of the NC dielectric capacitor in Fig. 3. Then

we evaluated the characteristics of the NMOS NC-FET, PMOS NC-FET, NC-FET CMOS

inverter in Figs. 4, 5, and 6, respectively. The improved performance of the NC-FET sustains for

different gate lengths (Fig. 7). The transient performance of the NC-FET CMOS inverter is

evaluated in Fig. 8 (in Appendix).

Fig. 3 (a) C-V characteristics of the conventional MOSFET. At VGS=0 V, gate capacitance is

dominated by the gate-source (COV) and gate-drain (COV) overlap and parasitic capacitances. (b)

Polarization (P) vs applied bias (VFE) of the ferroelectric dielectric P(VDF-TrFE).

𝛼𝐹𝐸 and 𝛽𝐹𝐸 coefficients of the ferroelectric dielectric are extracted through fitting of eq (4) with

experiment (from Ref. [10], [14]). (c) Energy landscape for different applied bias (VFE) (eq (3)),

-1.5 -1 -0.5 0 0.5 1 1.5

-0.35-0.25-0.15-0.050.050.150.250.35

P [C/cm2]

U [J/c

m3]

0 0.2 0.4 0.6 0.8 10

1

2

3

4

VG(MOS)

[V]

CG

[F

/cm

2]

CGSOV+CGDOV+CD

CGSOV+CGDOV+COX

VFE=0 to 0.20 V(3 steps)

LG=32 nmVD=1 V

ConventionalMOSFET

FE

(a)

(c)

(b)

-1 -0.5 0 0.5 1

-1.2-0.9-0.6-0.3

00.30.60.91.2

VFE

[V]

P [C

/cm

2]

Sim.

Exp.

-0.6 -0.4 -0.2 0 0.2 0.4 0.6-1.5-1.2-0.9-0.6-0.3

00.30.60.91.21.5

VFE

[V]

P [C

/cm

2]

-10 -5 0 5 10-1.5-1.2-0.9-0.6-0.3

00.30.60.91.21.5

P [C

/cm

2]

CFE

[F/cm2]

tFE=60 nm

tFE=10 nm

7

polarization (P) vs applied bias (VFE) (eq 4), and polarization (P) vs capacitance (CFE) (eq 5) of

the ferroelectric dielectric.

Fig. 4 (a) ID-VGS and (b) Gate charge (QG) vs VGS characteristics of the NMOS NC-FET for

different tFE using BSIM4 and Landau theory. (c) Different potential components of the NC-FET:

applied gate bias (VG(NC)), voltage across the ferroelectric dielectric (VFE), and voltage in the

intermediate node G(MOS), VG(MOS). (d) Subthreshold slope (S) vs VGS for different tFE. (e) QG vs

VFE profile from the circuit simulation (red) and from eq (4) (blue).

0 0.2 0.4 0.6 0.8 110

-2

10-1

100

101

102

103

104

VG(NC)

[V]

I D [A

/m

]

-0.3 -0.2 -0.1 0 0.1 0.2 0.3

-1.2-0.9-0.6-0.3

00.30.60.91.2

VFE

[V]

QG

[C

/cm

2]

0 0.2 0.4 0.6 0.8 1-0.2

0

0.2

0.4

0.6

0.8

1

VG(NC)

[V]

V [

V]

0 0.1 0.2 0.3 0.40

30

60

90

120

150

180

VG(NC)

[V]

S [m

V/d

ec]

0 0.2 0.4 0.6 0.8 1

-1.2-0.9-0.6-0.3

00.30.60.91.2

VG(NC)

[V]

QG

[C

/cm

2]

Device

Material

VG(NC)

VD= 1V

tFE=10 nmtFE=13 nm

tFE=10 nmtFE=13 nm

tFE=10 nmtFE=13 nmtFE=13 nm

tFE=13 nmVG(MOS)

VFE

LG= 32 nm P(VDF-TrFE)

(a) (b)

(c) (d) (e)

BSIM4

8

Fig. 5 (a) Symbolic representation of the PMOS NC-FET. (b) ID-VGS and (c) Gate charge (QG) vs

VGS characteristics of the PMOS NC-FET for different tFE using BSIM4 and Landau theory. (d)

Different potential components of the NC-FET: applied gate bias (VG(NC)), voltage across the

ferroelectric dielectric (VFE), and voltage in the intermediate node G(MOS), VG(MOS). (e)

Subthreshold slope (S) vs VGS for different tFE.

Fig. 6 (a) Symbolic representation of the NC-FET CMOS inverter. (b) Performance comparison

of the different CMOS inverters. With the incorporation of NC dielectric, NMOS (black arrow)

and PMOS (magenta arrow) are turning-on at lower effective threshold voltage compared to

conventional counterpart.

-0.4 -0.3 -0.2 -0.1 0

30

60

90

120

150

180

VG(NC)

[V]S

[m

V/d

ec]

-1 -0.8 -0.6 -0.4 -0.2 0

-1.2-0.9-0.6-0.3

00.30.60.91.2

VG(NC)

[V]

QG

[C

/cm

2]

-1 -0.8 -0.6 -0.4 -0.2 0-1

-0.8

-0.6

-0.4

-0.2

0

0.2

VG(NC)

[V]

V [

V]

-1 -0.8 -0.6 -0.4 -0.2 010

-2

10-1

100

101

102

103

104

VG(NC)

[V]

I D [A

/m

]

VD= 1V

tFE=10 nmtFE=10 nm

tFE=10 nm

tFE=10 nm

LG= 32 nm

VG(NC)

VG(MOS)

VFE

G (

NC

)

DB

S (b) (c)

(d) (e)

(a)

BSIM4 P(VDF-TrFE)

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Vin

[V]

Vou

t [V

]

Vin Vout

VDD

MOSFETNC-FET

tFE=10 nm

LG= 32 nm(a) (b)

9

Fig. 7 ID vs VGS characteristics of the NMOS NC-FET from (a) BSIM4 and Landau theory and (b)

MVS and Landau theory for 45 nm technology node. Subthreshold slope (S) vs VGS of the

NMOS NC-FET from (a) BSIM4 and Landau theory and (b) MVS and Landau theory for 45 nm

technology node.

5. Summary

The manual describes the electrical model of the NC-FET by integrating MVS/BSIM4 model with

Landau theory. Future work involves improving the physics of the model and inclusion of the

transient response of the ferroelectric material. Please contact Muhammad A. Wahab

(mwahab@purdue.edu) regarding any questions/comments about the negative capacitance

FET compact model.

References

[1] “International Technology Roadmap for Semiconductors.” [Online]. Available: http://www.itrs.net/.

0 0.2 0.4 0.6 0.8 110

-2

10-1

100

101

102

103

104

VG(NC)

[V]

I D [A

/m

]

0 0.1 0.2 0.3 0.40

30

60

90

120

150

180

VG(NC)

[V]

S [m

V/d

ec]

0 0.2 0.4 0.6 0.8 110

-2

10-1

100

101

102

103

104

VG(NC)

[V]

I D [A

/m

]

tFE=10 nmtFE=13 nm

tFE=10 nmtFE=13 nm

VD= 1VLG= 45 nm

tFE=10 nmtFE=13 nm

tFE=10 nmtFE=13 nm

BSIM4 MVS

P(VDF-TrFE)

(a) (b)

(c) (d)

0 0.1 0.2 0.3 0.40

30

60

90

120

150

180

VG(NC)

[V]

S [m

V/d

ec]

10

[2] “Predictive Technology Model (PTM).” [Online]. Available: http://ptm.asu.edu/latest.html.

[3] S. H. Shin, M. Masuduzzaman, M. A. Wahab, K. Maize, J. J. Gu, M. Si, A. Shakouri, P. D. Ye, and M. A. Alam, “Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs,” in 2014 IEEE International Electron Devices Meeting, pp. 20.3.1–20.3.4, December 15-17, 2014, San Francisco CA, USA.

[4] M. A. Wahab, S. Shin, and M. A. Alam, “3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature,” IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3595–3604, Nov. 2015.

[5] S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices.,” Nano Lett., vol. 8, no. 2, pp. 405–10, Feb. 2008.

[6] A. Jain and M. A. Alam, “Stability Constraints Define the Minimum Subthreshold Swing of a Negative Capacitance Field-Effect Transistor,” IEEE Trans. Electron Devices, vol. 61, no. 7, pp. 2235–2242, Jul. 2014.

[7] A. Jain and M. A. Alam, “Proposal of a Hysteresis-Free Zero Subthreshold Swing Field-Effect Transistor,” IEEE Trans. Electron Devices, vol. 61, no. 10, pp. 3546–3552, Oct. 2014.

[8] A. Jain and M. A. Alam, “Prospects of Hysteresis-Free Abrupt Switching (0 mV/decade) in Landau Switches,” IEEE Trans. Electron Devices, vol. 60, no. 12, pp. 4269–4276, Dec. 2013.

[9] K. Karda, A. Jain, C. Mouli, and M. A. Alam, “An anti-ferroelectric gated Landau transistor to achieve sub-60 mV/dec switching at low voltage and high speed,” Appl. Phys. Lett., vol. 106, no. 16, p. 163501, Apr. 2015.

[10] Y. Li, Y. Lian, K. Yao, and G. S. Samudra, “Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory,” Solid. State. Electron., vol. 114, pp. 17–22, Dec. 2015.

[11] M. A. Wahab and M. A. Alam, “Compact Model of Short-Channel Negative Capacitance (NC)-FET with BSIM4/MVS and Landau Theory,” in NEEDS Annual Meeting and Workshop, May 11-12, 2015, Cambridge, MA, USA.

[12] M. A. Alam, P. Dak, M. A. Wahab, and X. Sun, “Physics-Based Compact Models for Insulated-Gate Field-Effect Biosensors, Landau Transistors, and Thin-Film Solar Cells,” in IEEE Custom Integrated Circuits Conference (CICC), September 28-30, 2015, San Jose, CA, USA.

[13] S. Rakheja and D. Antoniadis, “MVS Nanotransistor Model (Silicon),” nanoHUB.

[14] G. Salvatore, A. Rusu, and A. Ionescu, “Analytical model for predicting subthreshold slope improvement versus negative swing of S-shape polarization in a ferroelectric FET.,” in In: MIXDES, 2012, pp. 55–59.

11

Appendix

A. Transient performance

Fig. 8 Our developed NC-FET model can be used for transient simulation of CMOS circuits.

Results of the transient simulation of the NCFET CMOS inverter of Fig. 6(a). (a) Input gate

pulse (Vin) vs time (t). (b) Inverter output (Vout) vs t. (c) Zoomed version of a cycle from (b)

highlights the effect of the negative capacitor on performance of NC-FET inverter. Slow

response of the ferroelectric material is neglected in the transient simulation. In practical device

material response can be a limiting factor and therefore, must be accounted. Also, the

representation of the negative capacitor as dependent source cannot account the transient

behavior accurately.

tFE=10 nmLG= 32 nm(a)

(b)

0 5 10 15 20 25 30 35

-0.5

0

0.5

1

1.5

t [ps]

Vo

ut [

V]

6 8 10 12

-0.5

0

0.5

1

1.5

t [ps]

Vo

ut [

V]

0 5 10 15 20 25 30 350

0.5

1

t [ps]

Vin [

V]

(c)

MOSFETNCFET

CMOS Inverter

12

B. Parameters of Conventional MOSFET

Conventional MOSFET parameters are directly collected or extracted from the predictive

technology model ( http://ptm.asu.edu/ ). A sample set of parameters for NMOS device is

provided below as an illustration.

Math Symbol Description 𝐿𝐺 = 45 𝑛𝑚

(Default value)

𝐿𝐺 = 32 𝑛𝑚

(Default value)

Unit

𝑊 Channel width 1 1 𝜇𝑚

𝐸𝑂𝑇 Effective oxide thickness 0.9 0.75 𝑛𝑚

휀𝑂𝑋 Oxide dielectric constant 3.9 3.9

휀0 Free space permittivity F/cm

𝑁𝑠𝑢𝑏 Substrate doping density 6.5×1018

8.7×1018

𝑐𝑚−3

𝑉𝑇0 Threshold voltage 0.3423 0.3558

𝜇 Carrier mobility 295 238 𝑐𝑚2/𝑉𝑆

𝑣𝑥0 Saturation velocity 1.595×10

7 1.821×10

7 𝑐𝑚/𝑆

𝑅𝑆 = 𝑅𝐷 Source/Drain resistance 52.5 40 Ω − 𝜇𝑚

𝐶𝐺𝑆𝑂𝑉 = 𝐶𝐺𝐷𝑂𝑉 Source/Drain overlap

capacitance

2.1×1012

2×1012

F/cm

𝑛 Subthreshold coefficient 1.15 1.15

𝛿 DIBL factor 0.0332 0.0424 𝑉/𝑉

𝛽 1.8 1.8

𝛼 3.5 3.5

𝛾 0.1 0.1 √𝑉

C. HSPICE toolkit

In order to analyze the HSPICE output data, HSPICE toolkit available in Matlab is used. This

can be downloaded from http://www.cppsim.com/InstallFiles/hspice_toolbox.tar.gz . Make sure

to add it in the Matlab path. You can use the following Matlab command to add this to the

default path: addpath(location_of_hspice_toolbox_folder).

D. Simulating HSPICE netlist

HSPICE code can be run on file “filename.sp” using following command: hspice filename.sp

E. Checklist for model analysis

1. Install the HSPICE toolkit to enable data extraction from HSPICE files.

2. Download the complete package in folder NCFET. Compile the following HSPICE files

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_nmos_bsim4_Lg32nm\ncfet_nmos.sp

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_pmos_bsim4_Lg32nm\ncfet_pmos.sp

13

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_inverter_bsim4_Lg32nm\ncfet_inverter.sp

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_inverter_tran_bsim4_Lg32nm\ncfet_inverter.sp

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_nmos_mvs_Lg45nm\ncfet_nmos.sp

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_pmos_mvs_Lg45nm\ncfet_pmos.sp

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_inverter_mvs_Lg45nm\ncfet_inverter.sp

NCFET\Negative Capacitance FET Model 1.0.0 HSPICE

Netlists\ncfet_nmos_bsim4_Lg45nm\ncfet_nmos.sp

…………………………………

3. Compilation of the files will generate the filename.sw0 and filename.tr0 files for dc and transient simulations respectively. These files can be analyzed using the perform_analysis.m file.

4. Go to the folder containing the “perform_analysis.m” file and run it.