A Utility-Interfaced Phase-Modulated High-Frequency Isolated Dual LCL DC/AC Converter

1008 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 2, FEBRUARY 2012

A Utility-Interfaced Phase-ModulatedHigh-Frequency Isolated Dual

LCL DC/AC ConverterXiaodong Li, Member, IEEE, and Ashoka K. S. Bhat, Fellow, IEEE

Abstract—This paper presents a phase-modulated high-frequency isolated dc/ac converter as the grid interface in adistributed generation system. The converter includes two full-bridge HF LCL-type resonant inverters working at fixed dutycycle. The power control is realized by means of the phase-shiftbetween the two bridges. Using the LCL-type resonant tank,zero-voltage-switching is achieved for all switches for the wholepower range. With the phase-shift modulated sinusoidally, a full-wave rectified output current synchronized with the utility lineis obtained, which is unfolded and fed to the single-phase utilityline. The analysis is verified with computer simulation results.Experimental data based on a 500-W prototype circuit is includedfor validation purpose.

Index Terms—DC/AC power conversion, high-frequency trans-former, resonant power conversion, utility interconnection.

I. INTRODUCTION

W ITH increasing concern about possible energy crisisand environmental issues, use of renewable energy is

gaining more attention. In practice, to effectively utilize theenergy generated by alternate energy sources, power convertersplay a key part in all renewable energy generation systems. Theoutputs of photovoltaic panel and fuel cell stack are variabledc, while the outputs of most wind generation systems arevariable ac. To incorporate different types of renewable energygeneration systems into the grid system, a dc bus is commonlyused as shown in Fig. 1 [1], [2]. The varying dc output ofphotovoltaic panels [3]–[8] and fuel cell stacks are connectedwith a common dc bus via dc/dc converters. Small-scale windgenerators, most of which are permanent-magnet synchronousgenerator (PMSG) [9]–[15], can be connected with the dc busthrough ac/dc converters. Energy storage equipment is alsorequired to help with the regulation of the dc bus voltage. Theexistence of a dc bus in the grid system also meets the trendof the rapidly developing HVDC transmission techniques [16].The dc bus voltage is kept nearly a constant and can be inter-

Manuscript received December 3, 2010; revised March 30, 2011; acceptedMay 15, 2011. Date of publication May 27, 2011; date of current versionOctober 18, 2011. This work was supported by a research grant from the NaturalSciences and Engineering Research Council (NSERC) of Canada.

X. Li is with the Faculty of Information Technology, Macau University ofScience and Technology, Macau SAR, China (e-mail: [email protected]).

A. K. S. Bhat is with the Department of Electrical and Computer En-gineering, University of Victoria, Victoria, BC V8W 3P6, Canada (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2158044

Fig. 1. Grid-connected distributed power generation system.

faced with the commercial ac grid by means of dc/ac converters.The commonly used dc/ac grid-connected converter is the hard-switched PWM voltage source inverter (VSI) [14], [15], [17]–[20] that requires a dc link front-end with voltage level higherthan the peak value of grid line voltage. In such systems, linefrequency transformer has to be used when electrical isolationis required between the dc bus and the utility line. It is wellknown that high-frequency (HF) power conversion has manyadvantages, which include small size and light weight, reducedcost and fast dynamic response. A small HF transformer ispreferred for the purpose of both safety and voltage leveltransformation to match the dc bus voltage with the utilityvoltage. Also, transformer isolation becomes a requirementin complex energy systems, for example, “Integrated EnergySystem” [21]. Soft switching techniques should be introducedto minimize switching losses and reduce EMI resulting fromHF switching operation. The proposed dc/ac converter can alsobe used in interfacing energy sources directly to the utility linewhen isolation is a requirement.

Among the several HF dc/ac configurations for grid connec-tion proposed for photovoltaic application [22]–[31], there aretwo major possibilities. The first one is a HF dc/dc converterfollowed by a regular VSI mentioned earlier. The second op-tion is a sinusoidal modulated HF dc/dc converter followedby a line-connected-inverter (LCI) [22]–[30]. The front-endconverter creates a rectified sinusoidal output current that issynchronized with the utility line voltage, which is then un-folded by the following LCI stage. The highly efficient LCIis switching at zero-crossing points of the utility line voltage.Use of resonant converters for photovoltaic to utility interfaceapplication has been proposed in [22], [23], [28]–[30]. Use ofdual series resonant converter (SRC) was proposed by Pitel [28]and in this configuration, two phase-shifted half (or full) bridgeSRCs were operated with fixed-frequency. The power is shared

0278-0046/$26.00 © 2011 IEEE

LI AND BHAT: PHASE-MODULATED HIGH-FREQUENCY ISOLATED DUAL LCL DC/AC CONVERTER 1009

Fig. 2. HF isolated dual-bridge LCL resonant converter to interface a dc source Vs with a single-phase utility line.

by two half or full bridges so that the power transfer capabilityis improved. With the phase-shift modulated sinusoidally, arectified sinusoidal current can be generated at the output low-pass filter, which is then unfolded by a LCI to feed into thesingle phase grid. The switches in one bridge turn on with zero-voltage-switching (ZVS), while the switches in the other bridgework in ZCS which requires lossy RC snubbers.

In [32], the authors have proposed an improved version ofthis converter shown in Fig. 2, in which two full-bridge (FB)LCL-type SRCs are connected in parallel at the input sideto improve the switching characteristics. In this paper, moredetails of the converter are presented. Steady-state equivalentcircuits during HF intervals are given. More simulation andexperimental results are presented. Discussion of efficiency andloss estimation is added too. In Fig. 2, the input dc voltage isassumed to be kept approximately constant. It is shown thatboth bridges are operating with ZVS with lossless capacitivesnubbers. If the fixed-frequency ZVS PWM bridge or LCL-typeresonant converter with inductive output filter [33] is used, thenduty cycle loss will reduce the system efficiency. A “Π” typelow-pass filter is used here with small component values. Forthe dc/dc converter side, the filter shows similar performance asa single large capacitive filter, while it is possible to modulatethe dc link current sinusoidally. Section II presents the steadystate operation of the dual-bridge LCL converter. A detailedanalysis using the Fourier series approach [34], [35] is given inSection III. Based on the analysis, design curves are obtained.In Section IV, a 500-W converter design example is given.Verification of converter performance has been done throughboth computer simulation and experiments in Section V usinga converter switching at 100 kHz.

II. PRINCIPLE OF THE DUAL-BRIDGE LCLRESONANT CONVERTER

The proposed topology shown in Fig. 2 includes two LCLresonant converters linked with a LCI through a low-pass filter.Two HF LCL inverters are connected in parallel to the input

dc source Vs. The secondary sides of two HF transformers areconnected in series and this HF output voltage vrec−in obtainedis then rectified into dc by a HF diode rectifier. The low-passfilter removes HF components of output current. There is aphase-shift 2θ between the two inverter bridges to control theoutput power. If θ is zero, the secondary voltages of two trans-formers are added together to give maximum output power. If θis π/2, the secondary voltages of two transformers cancel eachother and give zero output. When 0 < θ < π/2, different outputpower level can be achieved. The phase-shift angle is modulatedsinusoidally so that the diode rectifier output current is shapedinto a rectified sine wave (i.e., succession of 60-Hz half-sinewaves). It can be unfolded into a sinusoidal current by a LCIto feed into the grid. Due to the two-bridge type structure, theinput current is shared by two bridges and high power level canbe achieved. The output voltages vAB and vCD of the two HFinverters are always square waves with 50% duty ratios at anyload level so that the volt-sec balance of the two transformersare guaranteed. In each bridge, the transition conditions ofeach leg are the same so that the energy circulation intervalof conventional phase-shift control is avoided. Thus, the inputcurrent will be in continuous mode and the input filter sizewill be small. Though the topology looks complex, the controlfor both dc/dc conversion and grid-interface are quite simplecompared with commonly-used PWM control. PWM controlscheme also has switching losses since switches are hard-switched limiting the switching frequency. Additionally, thetwo full-bridge inverters shown in Fig. 2 can be implementedwith half-bridge inverters too. Then the number of switcheswill be reduced by four. However, the transformer turns ratioshould be twice to keep the same voltage gain since the inputvoltage is only half of Vs. It should be noted that although thedc/ac converter proposed has three stages, the rectifier stageand LCI stage on the secondary-side are highly efficient whilethe resonant inverter on the primary-side is also efficient dueto ZVS. Since the function of LCI is only to unfold the dclink current on alternate half-cycles of line frequency, switchinglosses are negligible. The HF transformer allows the matching


Fig. 3. Steady-state waveforms of the dual LCL resonant converter in one HFcycle.

of dc bus voltage to the line voltage even if there is a largedifference between the two.

To understand the operation details of the dual LCL SRC,the steady-state operation waveforms of the dc/dc stage with acertain value of phase-shift are presented in Fig. 3. It is seenthat there are 10 intervals of operation in one switching period.Devices conducting during different intervals are also markedin Fig. 3. The effects of snubbers and dead-gaps are neglected.Fig. 4 shows the steady-state equivalent circuits for the first fiveintervals. The operation of each interval is explained next.

Fig. 4. Steady-state equivalent circuits for the first five intervals (interval 1 tointerval 5) in a HF cycle of the dual bridge LCL converter as shown in Fig. 3.

Since the secondary sides of two transformers are connectedin series, the primary currents of two HF transformers are sametoo, which are the sum of the resonant current and the parallelinductor current. Right before interval 1, the conducting devices


are assumed to be s2, s4, s6, s8, db, dd. The two resonant cur-rents is1, is2 are negative. A full switching period begins withthe turn-off of switches s2, s4 in the leading bridge.

Interval 1: Though s2, s4 are turned off forcibly, the switchingloss is minimized to almost zero with the help of capacitivesnubbers. The negative resonant current is1 will not changesuddenly and will be smoothly transferred to d1, d3. Thegating signals of the switches s1, s3 in the leading bridgecan be applied now. Since vAB is positive and vCD isnegative, the polarities of two secondary-side voltagesare opposite and the secondary-side current i2, which isnegative now, tends to decrease in amplitude. This intervalends when i2 goes zero.

Interval 2: When i2 becomes zero, diodes db, dd are turnedoff with zero current. All diodes in the HF rectifier arereverse-biased and will not conduct. On the primary side ofeach HF transformer, the series (LC) tank and the parallelinductor form a new series resonance circuit with theresonance frequency of fLCL = 1/(2π

√(Ls + Lp)Cs).

This interval completes when the gating signals of s6, s8are removed. This interval is absent for zero phase shift.

Interval 3: With the help of capacitive snubbers, the negative is2shifts from s6, s8 to d5, d7 smoothly. The gating signalsof the switches s5, s7 can be given now. d1, d3 continueto conduct. Now, two secondary voltages have same po-larities and are added together. Diodes da, dc are forward-biased and turned on with zero current. The secondary-sidecurrent i2 starts to increase.

Interval 4: This interval begins with zero-crossing of is1. Withthe gating signals of s1, s3 already applied, is1 naturallychanges polarity and starts to flow in s1, s3. The switchess1, s3 are turned on with zero voltage since their anti-parallel diodes d1, d3 conduct prior to this. The parallelinductor current ip1 changes polarity during this interval.

Interval 5: This interval beginning with zero-crossing of is2 issimilar to the last interval. is2 naturally changes polarityand shifts from d5, d7 to s5, s7. Zero-voltage turn-on ofthe switches s5, s7 is realized due to conduction of d5, d7before this. The parallel inductor current ip2 changes po-larity during this interval.

Interval 6 to 10: These five intervals are same as Interval 1 to 5except that the devices conducting are symmetric. So thosecan be understood easily with help of Figs. 3 and 4 and willnot be explained in detail.

The working condition described above is for a certain valueof phase-shift only. With different values of phase-shift, thesequence of the intervals might be different and the number ofintervals may change too. However, the ZVS operation of allswitches is still guaranteed. For example, the tank current is1may change polarity from negative to positive before the turn-off of s6, s8 if the phase-shift is quite small, which will notchange the zero-voltage turn-on of s1, s3. If the phase shift isquite large, the tank current is2 might decrease from positive tonegative and then go positive again before i2 decreases to zero,which will not affect the zero-voltage turn-on of s5, s7.

Fig. 5. nth harmonic phasor equivalent circuit.

III. STEADY STATE ANALYSIS USING FOURIER SERIES

In this section, the steady state analysis of the dual-bridgeLCL converter is presented using the Fourier series approach.All voltage and current waveforms are represented by theirFourier series. To simplify the analysis, all switches, inductors,capacitors and transformers are assumed to be ideal. The effectof snubbers is neglected. The output voltage of the dioderectifier is a succession of 60-Hz half-sine waves which can beregarded as constant during a HF switching period, because theswitching frequency is much higher than 120 Hz, which is thefrequency of ac component in the idc (Fig. 2).

All parameters have been transferred to the primary side,which are denoted by the superscript “′”. For convenience, allequations presented are normalized with the following basevalues:

VB = Vs, ZB =√

Ls

Cs, IB =

VB

ZB, fB = fr =

12π

√LsCs

(1)

where Vs is input dc voltage and fr is series resonance fre-quency. Converter voltage gain is defined as: M = V ′

o/Vs,V ′

o = (nt)(Vo), where nt is the transformer primary-to-secondary turns ratio. The normalized switching frequency isgiven by: F = ωs/ωr = fs/fr and fs is switching frequency.All normalized values are denoted by subscript “0” and thenth harmonic component is denoted by subscript “n”. Then allnormalized nth harmonics reactances are given by

XLsn = nωsLs, XLsn0 = nF (2a)

XCsn = − 1/(nωsCs), XCsn0 = −1/(nF ) (2b)

Xsn = XLsn + XCsn, Xsn0 = nF − 1/(nF ) (2c)

Xpn = nωsLp, Xpn0 = nFK, K = Lp/Ls. (2d)

The nth harmonic equivalent circuit used for analysis isshown in Fig. 5. The two voltage sources on the left are square-wave outputs of two inverters. The third voltage source v′

20 isthe rectifier input voltage reflected to the primary side of the HFtransformer, which is actually equal to the algebraic sum of thetwo voltages across the parallel inductors during all intervalsand its amplitude is equal to +V ′

o or −V ′o, where V ′

o is theoutput voltage referred to the primary-side (except in interval2 when rectifier diodes are not conducting). This voltage (v′

20)is a square wave at zero phase-shift (interval 2 is absent) and isnearly a square wave (except in interval 2) at non-zero phase-shift. To simplify the analysis, v′

20 is assumed to be a square


wave of amplitude V ′o. From the design point of view, zero

phase-shift is the important mode and this assumption gives agood design. The nth harmonic components of three normalizedsquare-wave voltage sources in phasor domain are given by

V ABn0 =4

nπ∠(nθ − 90◦) p.u. (3a)

V CDn0 =4

nπ∠(−nθ − 90◦) p.u. (3b)

V′2n0 =

4M

nπ∠(−nα − 90◦) p.u. (3c)

where α is the phase angle of rectifier input voltage v2, i.e.,vrect−in in Fig. 2.

With the help of Fig. 5, the expressions for nth harmoniccurrents and voltages in phasor domain are derived. With thephasor results converted to time domain, the instantaneousexpressions of all voltages and currents in time domain can beevaluated by adding the first n harmonics using the principle ofsuperposition.

The normalized diode rectifier input current reflected to theprimary-side in time domain is obtained as

i′20(t) =∞∑

n=1,3,5...

2M cos n(ωst − α)(Xsn0 + Xpn0)nπXsn0Xpn0

−∞∑

n=1,3,5...

4 cos(nθ) cos(nωst)nπXsn0

. (4)

Following the same procedure, the two resonant currents, twoparallel inductor currents and two resonant capacitor voltages intime domain can be obtained.

The two parallel inductor currents in time domain arederived as

ip10(t) =∞∑

n=1,3,5...

[4 sin(nθ) sin(nωst)nπ(Xsn0 + Xpn0)

−2M cos n(ωst − α)nπXpn0

](5)

ip20(t) =∞∑

n=1,3,5...

[−4 sin(nθ) sin(nωst)nπ(Xsn0 + Xpn0)

−2M cos n(ωst − α)nπXpn0

]. (6)

The two resonant tank currents in time domain can beshown as

is10(t)=∞∑

n=1,3,5...

2M cos n(ωst−α)−4 cos(nθ) cos(nωst)nπXsn0

+∞∑

n=1,3,5...

4 sin(nθ) sin(nωst)nπ(Xsn0 + Xpn0)

(7)

is20(t)=∞∑

n=1,3,5...

2M cos n(ωst−α)−4 cos(nθ) cos(nωst)nπXsn0

+∞∑

n=1,3,5...

−4 sin(nθ) sin(nωst)nπ(Xsn0+Xpn0)

. (8)

The two resonant capacitor voltages in time domain areshown as

vc10(t) =∞∑

n=1,3,5...

4 cos(nθ) sin(nωst)−2M sinn(ωst−α)nπXsn0

× XCsn0

+∞∑

n=1,3,5...

4XCsn0 sin(nθ) cos(nωst)nπ(Xsn0 + Xpn0)

(9)

vc20(t) =∞∑

n=1,3,5...

4 cos(nθ) sin(nωst)−2M sinn(ωst−α)nπXsn0

× XCsn0

+∞∑

n=1,3,5...

−4XCsn0 sin(nθ) cos(nωst)nπ(Xsn0+Xpn0)

. (10)

By means of (4), the average output current J can beobtained as

J =8π2

∞∑n=1,3,5...

cos(nθ) sin(nα)n2Xsn0

. (11)

When making use of all the equations derived above todesign a converter for given specifications, the only unknownparameter is α. Therefore, it is necessary to find the angle α toevaluate other design parameters. Since the diode bridge currentreaches zero at ωst = α, the phase angle of rectifier outputvoltage can be found from (4) by letting ωst = α

0 =∞∑

n=1,3,5...

[2M(Xsn0 + Xpn0)

nπXsn0Xpn0− 4 cos(nθ) cos(nα)

nπXsn0

].

(12)

The above equation can be solved numerically usingNewton-Raphson method. The initial guess value of α1 can beobtained from (12) with only fundamental component

cos α1 =M

2

(1 +

Xs10

Xp10

)sec θ. (13)

In the circuit shown in Fig. 2, the parallel inductance isconnected on the primary side and the leakage and magnetizinginductances are neglected. If the parallel inductance is movedto the secondary, the leakage inductance can be used as part ofresonant inductance, and the effect of magnetizing inductancecan be included [33]–[35].

IV. DESIGN

A design example is given to illustrate the design procedurethat uses the Fourier series analysis presented in Section III.The specifications of the converter to be designed are given inTable I.

Since the output voltage and current are both sinusoidal andin phase, the converter is designed at the peak power of 1 kWto deliver an average power of 500 W. Also, the design shouldbe done at the input voltage Vs = 200 V and highest output


TABLE ICONVERTER SPECIFICATIONS FOR ILLUSTRATION

Fig. 6. Design curves with K = 10 for different normalized switching fre-quency F : (a) Tank kVA per kW of output power and (b) normalized averageoutput current J , versus converter gain M .

voltage Vo = Vp = 294 V to deliver a peak power of 1 kW at aphase-shift angle θ = 0◦.

Several design curves are drawn for the purpose of design.Plots of tank kVA per kW of output power with respect toconverter gain M at K = Lp/Ls = 10 for different normalizedswitching frequency F are drawn in Fig. 6(a). Fig. 6(b) showsthe relationship between the normalized average output currentJ with converter gain M for various values of F . Plots ofcomponents stress at full load for the 1-kW design exampleare given in Fig. 7. Fig. 7(a) shows the change of tank rmscurrent, which directly decides the rating of main switches, withrespect to converter gain M at K = 10 for different F . Theplots are then redrawn at F = 1.1 for different K in Fig. 7(b).The plots of resonant capacitor peak voltage (Vcp) with respectto converter gain M at K = 10 for different F are drawn inFig. 7(c).

Since the plots are drawn for the design point with zerophase-shift to deliver full power, the voltages and currents intwo bridges are same. As the converter is supposed to operateabove resonance or lagging power factor (PF ) mode to achieveZVS, F should be larger than 1. It is seen from Fig. 7(a), asmaller F brings low rms tank current. To allow for some ZVSmargin, F is chosen at 1.1.

From Figs. 6(a), 7(a) and (c), value of M > 1.8 can reducethe tank kVA per kW of output power, tank rms current and

Fig. 7. Component stress at full load for a 1-kW converter, Vin = 200 V,Vo = 294 V. (a) Tank rms current versus converter gain M with K = 10 fordifferent F ; (b) Tank rms current versus converter gain M with F = 1.1 fordifferent K; (c) The resonant capacitor peak voltage versus converter gain Mwith K = 10 for different F .

capacitor peak voltage with F = 1.1. Here, M is chosen as 1.94since the tank rms current takes the minimum in Fig. 7(a) whileVCp is almost at minimum value [Fig. 7(c)].

The inductor ratio K = Lp/Ls should be small enough toprovide ZVS for switches and reduce tank kVA per kW ofoutput power [32]. However, it cannot be too small; otherwisethe tank rms current would be high as seen from Fig. 7(b).

Normalized average output current J should be chosen ap-propriately to minimize the rms resonant current and kVA ratingof tank per kW of output power. The approximate optimumoperating point is chosen as: M = 1.94, J = 0.3185, F = 1.1,K = 10. Using (1) and the definitions of M and J , the valuesof tank components are calculated as

Ls =MV 2

BJF

2πfsPo= 43.28 μH; Cs =

PoF

2πfsMV 2BJ

= 70.8 nF.

(14)

The primary-side reflected output voltage is V ′o = Vs × M =

200 × 1.94 = 388 V. The HF transformer turns ratio is nt :1 = V ′

o : Vo = 1.32 : 1. With K = 10, the parallel inductanceis Lp = K × Ls = 432.8 μH. The tank rms current and tankcapacitor peak voltage at design point are found to be 2.96 Aand 94 V, respectively. Due to the existence of the parallel


Fig. 8. Simulation results of dc/dc converter at different phase-shift θ:vAB , vCD , HF rectifier input voltage (vrec−in) and current (i2) for (a) 0◦;(b) 30◦.

inductances, the peak/rms tank currents at the peak power pointare not the worst values. It is found that those values wouldincrease at first and then decrease to almost zero with the phase-shift changing from zero to 90◦. So when selecting components,a reasonable margin of voltage and current ratings should begiven.

V. SIMULATION AND EXPERIMENTAL RESULTS

To verify the analysis, PSIM simulation has been done on theconverter designed in Section IV initially as a dc/dc converterwith different values of θ. The operations of the converterworking in the dc/dc mode with resistive load at phase-shiftangles of θ = 0◦ and θ = 30◦, are shown in Fig. 8(a) and (b),respectively. At zero phase-shift or the peak load of 1 kW,the two bridges have exactly same conditions [Fig. 8(a)]. Withthe increase of phase-shift, output voltage and power decreasetogether. The ZVS operation is maintained for all switches aspredicted independent of the phase-shift, which can be seenfrom the relationship between vAB , vCD and tank currentsis1, is2 (Fig. 8). The peak voltage across the output HF rectifierdiodes is same as the output voltage as evident from the rectifierinput voltage (vrec_in). As predicted, rectifier input currentcan become discontinuous. It is observed that the peak andrms currents in the parallel inductors do not change too muchfollowing the phase-shift.

The PSIM simulation results for close-loop operation of thedc/ac converter connected with a 208-V single-phase utilitydelivering an average power of Po = 500 W are shown in

Fig. 9. Simulation waveforms of the dc/ac converter interfaced with utilityline with close-loop control for Po = 500 W: (a) line voltage vo and currentio, rectifier input voltage vrec−in, rectifier input current i2, and dc link currentidc; (b) spectra of vrec−in and i2; (c) expanded vrec−in and i2 with near zerophase-shift (top) and with near 30◦ phase-shift (bottom).

Fig. 9. As predicted, the HF rectifier input voltage is modulatedand dc link current idc is a rectified sine-wave [Fig. 9(a)]. Itcan be seen that the line current (unfolded version of idc) is inphase with line voltage with low distortion. Frequency spectraof HF rectifier input current and voltage given in Fig. 9(b)shows that the predominant fundamental harmonic componentis around 100 kHz. Expanded views of HF rectifier input currentand voltage waveforms at different points of line cycle are alsoshown in Fig. 9(c).

An experimental converter with same design is built andtested in the lab. The values of reactive components used inthe experiment are listed in Table II. A DSP board (eZd-spS320F2812) with a clock frequency of 150 MHz is used togenerate phase-shifted PWM gating signals and for closed-loop


TABLE IIVALUES OF COMPONENTS USED IN EXPERIMENT

control. The error between the sampled actual dc-link cur-rent and its reference is calculated in DSP. A PI controlleris used to process the error and generate proper phase-shift.The parameters of the PI controller are tuned up manually insoftware. To design the controller accurately, a small-signalmodel of the whole converter needs to be created at first,which might be done in future work. There are two standardindependent timers in the DSP which are able to generate twotriangular carrier waveforms. However, it is difficult to setand adjust the phase-shift between the two triangular carrierwaveforms precisely. Alternatively, in our setup, with only onetriangular carrier waveform used, the two phase-shifted PWMare generated by changing the compared values every HF halfperiod. This algorithm is able to generate a phase-shift asprecise as one clock period (6.67 ns). The switch used in theHF inverter stage is warp speed IGBT—G4PC40UD and theswitching frequency is chosen at 100 kHz. HF rectifier diodesused were MUR1560 and IGBTs used for the LCI stage wereIXGH10N100A. HF transformers were built using ferrite HFmagnetic cores (core material PC40) ETD49-Z manufacturedby TDK. These cores were wound using Litz wire with 28turns on primary and 22 turns on the secondary to reduce thecopper losses. Peak flux density level was kept approximatelyat 0.084 T and calculated total core loss is less than 3 W.The approximately measured total leakage inductance on theprimary side is 7 μH and the magnetizing inductance is 4 mH.Leakage inductance is used as part of resonant inductance andLp is placed on secondary-sides (values used are approximately320 μH each and when transferred to primary side, equivalentLp including magnetizing inductance is approximately 458 μH,slightly higher than the design value). The low-pass filter isused to filter out HF switching harmonics while keeping thefluctuating dc link current [that looks like a rectified waveformobtained from 60-Hz sine-wave, idc shown in Fig. 9(a)] whichinclude dc and other components with different frequencies. ABessel filter with maximally flat group delay is suitable for thisapplication. The filter component values are initially obtainedfrom normalized Bessel Filter table and then adjusted to letthe dc-link current fluctuate [36]. A cutoff frequency at 16 kHzis achieved with Cf1 = 100 nF, Lf = 667 μH, Cf2 = 10 nF.A photograph of the layout of experimental setup is shown inFig. 10.

Without the LCI, the converter is first tested in dc/dc op-eration mode with a resistive load of equivalent resistanceRo = 86.34 Ω for different values of θ in open-loop control.Some results obtained are shown in Figs. 11–15. At peak loadof 1 kW with output voltage at 294 V, the working conditionsof two bridges are the same. It is seen (Fig. 11) that the tankcurrent lags the HF inverter output voltage which indicatesZVS operation of all switches. The sinusoidal tank capacitor

Fig. 10. Photograph of the 500-W (1-kW peak) experimental converter builtin the lab.

Fig. 11. Experimental results of dc/dc converter at θ = 0◦, time scale:2 μs/div. (a) HF inverter output voltage vAB or vCD (100 V/div) and tankcurrent is1 or is2 (2 A/div); (b) tank capacitor voltage vc1 or vc2 (top,100 V/div) and parallel inductor current ip1 or ip2 (bottom, 1 A/div);(c) rectifier input voltage vrec−in (100 V/div) and input current i2 (2 A/div).

voltage shows a peak value of 98.8 V. The parallel inductorcurrent takes a triangular form with a peak value of 1.2 A.It can be seen from Fig. 11(c) that the rectifier input voltageis approximately a square-wave and is almost in phase withcurrent as expected at zero phase-shift. With 30◦ phase-shiftoperation shown in Figs. 12 and 13, the conditions in the twobridges are different. It is seen in Fig. 12 that the tank currentsin the two bridges are different. However, the ZVS operationin two bridges is still maintained. With non-zero phase-shift,ZVS margin of the leading bridge is widened and the ZVSin the lagging bridge is ensured with the help of the parallelinductor current as shown in Fig. 12. With non-zero phase-shift,as predicted, the diode rectifier input current shows two smallzero current intervals in each period, while the diode rectifierinput voltage is nearly a square-wave with some oscillationsduring zero-current interval [Fig. 12(c)]. The tank voltage andparallel inductor current at a phase-shift of 30◦ are shown inFig. 13. The ZVS conditions at increased phase-shift angles of60◦ and 75◦ are presented in Figs. 14 and 15, respectively. Itcan be observed that the voltage transition in the leading bridgeoccurs at the peak tank current, while the voltage transition


Fig. 12. Experimental results of dc/dc converter at θ = 30◦, time scale:2 μs/div. ZVS condition for two bridges: (a) HF inverter output voltage vAB

(100 V/div) and tank current is1 (2 A/div) of leading bridge; (b) HF inverteroutput voltage vCD (100 V/div) and tank current is2 (2 A/div) of laggingbridge; (c) rectifier input voltage vrec−in (200 V/div) and input current i2(5 A/div).

Fig. 13. Experimental results of dc/dc converter at θ = 30◦, time scale:2 μs/div. (a) Tank capacitor voltage vc1 (100 V/div) and parallel induc-tor current ip1 (1 A/div) of leading bridge; (b) tank capacitor voltage vc2

(100 V/div) and parallel inductor current ip2 (1 A/div) of lagging bridge.


(200 V/div) and tank current is1 (5 A/div) of leading bridge; (b) HF inverteroutput voltage vCD (200 V/div) and tank current is2 (2.5 A/div) of laggingbridge.

in the lagging bridge happens at the second peak value oftank current that results from the parallel inductor. It can beconcluded that ZVS operation of all the switches in both thebridges could be maintained even at larger phase-shifts. Therelationship between the converter voltage gain M and phase-shift angle θ obtained from theoretical calculations, simulationsand experiments are compared in Fig. 16.


(200 V/div) and tank current is1 (2 A/div) of leading bridge; (b) HF inverteroutput voltage vCD (200 V/div) and tank current is2 (2 A/div) of laggingbridge.

Fig. 16. Plots of the LCL dc/dc converter voltage gain M versus the phase-shift θ obtained from theoretical calculations, simulations, and experiments.

Fig. 17. Experimental results of dc/ac converter with close-loop control withresistive load (Ro = 86.34 Ω). (a) Output voltage (200 V/div) and current(2 A/div), time scale: 5 ms/div; (b) output current (2 A/div, 5 ms/div) and itsFFT spectrum in amplitude (400 mA/div, 100 Hz/div).

The converter is then tested in dc/ac operation with resistiveload at an average power Po = 500 W, which is controlled inclose-loop manner with the DSP. The output voltage and currentat full load are given in Fig. 17 along with the FFT spectrum ofoutput current in amplitude. The THD of the output current is4.2%, which is lower than the 5% requirement.

Finally, the converter is interfaced with a 208-V, 60-Hzsingle-phase utility line. The line voltage, line current and itsharmonic spectra are shown in Fig. 18(a) with Po = 500 W.Fig. 18(b) shows the same waveforms for half load, Po =250 W. It can be observed that the line voltage and current arein phase. The THD of line current measured from the FFT spec-trum are 9.49% and 9.2%, respectively. It should be noted thatthe line voltage in our lab has some distortion that has causedhigher distortion in line current and also since the line voltagewas used as the reference. In Fig. 19, the envelopes for HFresonant tank current, resonant capacitor voltage, input voltage


Fig. 18. Experimental results of dc/ac converter with close-loop controlinterfaced with 208-V single-phase grid, time scale: 5 ms/div frequency scale:100 Hz/div. (a) Po = 500 W, Line voltage vL (100 V/div), current iL(3.5 A/div) and its FFT (400 mA/div, 100 Hz/div); (b) Po = 250 W, linevoltage vL (100 V/div), current iL (3.5 A/div) and its FFT (200 mA/div,100 Hz/div).

Fig. 19. Experimental results of dc/ac converter with close-loop controlinterfaced with 208-V single-phase grid delivering Po = 500 W, time scale:2 ms/div. (a) Tank current is1 (top, 4 A/div) and capacitor voltage vc1 (bottom,100 V/div) in leading bridge; (b) tank current is2 (top, 4 A/div) and capacitorvoltage vc2 (bottom, 100 V/div) in lagging bridge; (c) input voltage vrec−in

(top, 300 V/div) and current i2 (bottom, 8 A/div) of diode rectifier.

and current of the HF diode rectifier in one line frequency cycleare given. It can be seen how those voltage and currents changefollowing the variation of phase shift. The efficiency for thetwo load levels is measured to be 90% and 83%, respectively.Using the data sheets for the devices and magnetic cores usedtogether with some measurements and simulation, break downof various estimated losses for the experimental converter at fullload and 20% load are given in Table III. Calculated efficiencyis slightly more than the measured value. Main source of thelosses is in semiconductors (mainly conduction losses), whichcontribute 60% of total loss (about 6% of rated power) at ratedload as shown in Table III. The total loss of two transformersand other is estimated at 40% of total loss (about 3% of ratedpower). Fig. 20 shows the plot of measured efficiency versuspercent of load current for the complete experimental converter(Fig. 2). The experimental converter designed and built in our

TABLE IIIESTIMATED APPROXIMATE LOSSES OF THE DC/AC EXPERIMENTAL

CONVERTER CONNECTED WITH THE GRID

Fig. 20. Measured efficiency of the dc/ac utility interfaced HF converter(Fig. 2) versus load current (in percent).

TABLE IVCOMPARISON OF SOME PARAMETERS OF THE DUAL-BRIDGE LCL SRC

FOR DC/DC OPERATION IN OPEN-LOOP CONTROL

academic environment is not optimized for efficiency and isonly used to prove the proposed concept. Still the efficiencyis comparable to the line frequency transformer isolated dc/acconverters reported in the market for wind energy and pho-tovoltaic applications (for example, WINDY BOY 1200 andSUNNY BOY 1200) [37]. The proposed converter will havereduced weight and size due to HF transformer isolation. Inaddition, if the input dc bus voltage is higher (say 400 V insteadof 200 V that we used in the example), efficiency can be highersince switching losses are very small due to soft-switching andconduction losses are the predominant losses (that will decreasefor the same output power).

Some comparisons between simulation and experiment re-sults are summarized in Table IV (for dc/dc converter opera-tion), Table V (dc/ac operation with R-load) and Table VI (dc/acoperation interfaced with the utility line). It is observed thatmost of the values obtained from simulations and experimentsare reasonably close to each other.


TABLE VCOMPARISON OF SOME PARAMETERS OF THE DUAL-BRIDGE LCL SRC

FOR DC/AC OPERATION WITH R-LOAD IN CLOSE-LOOP CONTROL

TABLE VICOMPARISON OF LINE CURRENT HARMONICS (IN rms) OF THE DUAL

LCL SRC FOR DC/AC OPERATION INTERFACING WITH A 208-VSINGLE-PHASE GRID IN CLOSE-LOOP CONTROL

VI. CONCLUSION

In this paper, a phase-modulated dual-LCL HF isolated dc/acutility connected converter is proposed for grid connectionin a distributed power generation system. A rectified sinewave dc link current (synchronized with the utility line) isgenerated through phase modulation between two LCL-typeresonant inverter bridges, which is then unfolded to feed intothe utility line. Duty-cycle loss does not exist with a low-pass filter used instead of a single large inductive filer. Theenergy circulation state for conventional fixed-frequency phase-shift control is eliminated, and full range ZVS operation forall switches is realized. It is featured with high power densitywith the two-bridge structure so that it has potential to be usedin applications with higher power. Three identical interleavedmodules could be used to interface with a 3-phase grid [11]–[13]. More future work has to be done to verify the three-phaseinterfacing scheme experimentally. With increasing penetrationrate of wind generation or hybrid distributed generation systemsincluding different renewable energy sources with differentvoltage levels, HF isolated converters can provide promisinghelp in voltage level match, the stability and safety for the utilitysystem.

Compared with the phased-modulated LC-type SRC [28]that has ZVS on the leading bridge and ZCS on the laggingbridge [28], [38]; the dual-bridge LCL dc/ac converter realizedfull range of ZVS for both bridges. Thus only capacitivesnubbers are needed. Also, the tank capacitor peak voltageis lower than that in SRC as the inherit feature of LCL-typeconverter. The magnetizing inductance of the HF transformercan be utilized as part of resonant tank when the parallelinductor is placed on the secondary side as mentioned before.The disadvantage is the use of parallel inductor, which resultsin extra size and cost. Also, the current in the parallel inductordoes not change much even at low load condition. Fortunately,current carried by the parallel inductor is small while aidingin wide range ZVS operation. With a proper design of HFtransformer, it is possible to integrate the parallel inductor withthe transformer. Due to developments in HF switching devices,

it is expected that HF switching device modules will be avail-able that will reduce the complexity of construction. With thedevelopment of new magnetic materials, HF transformers andresonant inductors with lower losses can be built. Furthermore,to improve the efficiency of the proposed converter, more effortis required on how to reduce the number of switches to reducethe conduction losses. Also, more work is to be done to studythe transient performance (including small signal analysis)of the proposed converter.

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Xiaodong Li (S’02–M’09) received the B.Eng. de-gree in electrical engineering from Shanghai JiaoTong University, Shanghai, China, in 1994 and theM.A.Sc. and Ph.D. degrees in electrical engineer-ing from the University of Victoria, Victoria, BC,Canada, in 2004 and 2009, respectively.

From 1994 to 2002, he worked in HongWanDiesel Power Co., Zhuhai, China, as an ElectricalEngineer where he conducted maintenance of dieselpower generation system. He joined the Faculty ofInformation Technology, Macau University of Sci-

ence and Technology, Macau SAR, China, in 2009, where he is an AssistantProfessor. His research interests include high frequency power converter, andfault diagnosis of motor drive.

Dr. Li is the recipient of the 2007 IEEE PES Best Paper Prize.

Ashoka K. S. Bhat (S’82–M’85–SM’87–F’98) ob-tained the B.Sc. degree in physics and math fromMysore University, Mysore, India, in 1972. He re-ceived the B.E. degree in electrical technology andelectronics and the M.E. degree in electrical en-gineering, both with distinction, from the IndianInstitute of Science, Bangalore, in 1975 and 1977,respectively. He also received the M.A.Sc. and Ph.D.degrees in electrical engineering from the Universityof Toronto, Toronto, ON, Canada, in 1982 and 1985,respectively.

From 1977 to 1981, he worked as a Scientist in the Power Electronics Groupof the National Aeronautical Laboratory, Bangalore, India, and was responsiblefor the completion of a number of research and development projects. Afterworking as a postdoctoral fellow for a short time, he joined the Departmentof Electrical and Computer Engineering, University of Victoria, Victoria, BC,Canada, in 1985, where he is currently a Professor of Electrical Engineering andis engaged in teaching and conducting research in the area of power electronics.He was responsible for the development of the Electromechanical EnergyConversion and Power Electronics courses and laboratories in the Departmentof Electrical Engineering at the University of Victoria.

Dr. Bhat received the “Excellence in Teaching Award” from the Faculty ofEngineering during the year 2008 and the “Wighton Fellowship” for the year2010. He is a Fellow of the Institution of Electronics and TelecommunicationEngineers (India), and a registered Professional Engineer in the province ofBritish Columbia, Canada.

A Utility-Interfaced Phase-Modulated High-Frequency Isolated Dual LCL DC/AC Converter

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