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Low Voltage Analog Circuit Design Techniques:

A Tutorial

Edgar Sánchez-Sinencio http://amsc.tamu.edu/

Texas A&M University

Analog and Mixed-Signal Center

IEEE Dallas CAS Workshop 2000 March 27, 2000

Low voltage (LV) power supply circuit design techniques are addressed in this tutorial. In particular:

(i) Introduction;

(ii) Transistor models capable to provide performance and power consumption tradeoffs;

(iii) Low voltage implementation techniques, such as floating gates and bulk driven;

(iv) Basic building blocks not involving cascode structures, and

(v) LV circuit implementations examples.

Low Voltage Analog Circuit Design Techniques: Roadmap

Analog and Mixed-Signal Center, TAMU

Motivation

• What are the challenges in designing low voltage circuits ?

- To operate with power supplies smaller than 3.3 volts

- To design circuits with the same performance or better

than circuits designed for larger power supplies

- To perform with technologies smaller than 0.5 micron

-To come with new design alternatives,

The need for analog circuits in modern mixed-signal VLSI chips for multimedia, perception, control, instrumentation medical electronics and telecommunication is very high.


- Designers can not use conventional cascode structures, and other conventional design methodologies.

- Circuits should have the same performance or better than circuits designed for larger power supplies

- Circuit performance with technologies smaller than 0.5um must be better than circuits for larger technologies.

-Third-generation communication applications require circuits ( and systems) with improved dynamic range over a much wider bandwidth.

- New building blocks and system must be designed to satisfy the needs of portable, lighter and faster equipment

( continues)


• Why are we concerned in designing low voltage circuits ?

Issues about low power supply voltage

Mister 5 volts IC Mister 0.8 volts IC

VTH

VTH

Scaling down size technology andsupply voltage does not scale linearly the “ VTH hat ”

• Threshold and VDSAT do not scale down linearly with power supply nor with smaller size technologies.

• Let us consider an illustrative example of a cascode and a simple inverting amplifiers, assume transistors MC and MS carry the same current IL, VT= 0.75V and VDS(SAT)=0.2V

• Keeping the same output voltage swing for both circuits involve the tradeoffs shown in the plot of transistor sizes and GBW vs. Power Supply Voltage

• How to determine how much bias current is needed for certain application ?

• When a designer operates transistors in saturation, what does it mean VDS > VDS(SAT) ?

• Can a circuit have their transistors operating in the transitionregion ? What transistor model equation can be employed ?

One Equation-All Regions Transistor Model

• Features of ACM model:– physics-based model,– universal and continuous expression for any inversion,– independent of technology, temperature, geometry and gate voltage,– same model for analysis, characterization and design.

• Main design equations: (design parameters: I, gm, if)

2

11 f

mt

i

ngI ++

=φ

( )1122 2

−+= ft

T iL

fπ

µφ

11

1

−+=

ftox

m

iCg

LW

φµ

( ) 411 +−+≅ f

t

DSAT iV

φ

−

=

12ng

IC

gLW

mttox

m

φφµ

I drain current in transistorgm transconductance in saturationn slope factorφt thermal voltageif inversion level of the transistor defined as

, where is the normalization current.

if << 1 weak inversion,

if >> 1 strong inversion.

sf IIi =L

WnCI t

oxs 2

2φµ=

L

WCnI

I

Ii

toxS

S

Df

2

2φµ ′=

=

ID: saturation current

IS: normalization current

n: slope factor

φ t m

D d

ng

I i=

+ +

2

1 1

10-2 10-1 100 101 102 10310-2

10-1

0

410

( ) theory (n=1.35)

( ) simulation

(o o o o o o) experiment

φ t m

D

g

I

i

10

WI MI SI

Normalized Current Transconductance-to-Current Ratio


The intrinsic cutoff frequency

( )

22

112

Lf

iff

to

foT

π

µφ=

−+≅

10-2 10-1 100 101 102 103 10410-2

10-1

100

101

102

103

id

f

fT

o

Drain-to-source saturation voltage

( ) 411 +−+≅ ft

DSsat iV

φ

10-2

10-1

100

101

102

103

10410

0

101

102

103

id

WI MI SI WI MI SI

VDSsat

tφ


Correlation Between Junction Capacitance (CJ) and Frequency Response

Parasitic capacitance α GBW/fT

CJ CJ W LDIF= ′ ⋅ ⋅

T

DIF

ox f

GBW

L

L

C

JC2

CL

CJ′

′≅LDIF

W

CJ

WLCL

C

GBW

fox T≅

′2

Correlation Between Area and Frequency Response


+VO

-

CL

IBIAS=IC

+VI

-

CL +VO

-

IBIAS=ID

+VI

-

tC

m 1

I

g

φ=

( )

++φ=

dtD

m

i11n21

Ig

tvo

VAA

φ−=

( )

++φ−=

dtvo i11n

2VAA

t

CI

CL21

GBWφπ

= ( )

++φπ=

dt

D

i11n

2I

CL2

1GBW

πτ≅

2

1fT ( )1i12

2

1f dT −+

πτ≅

≅φ t

CEsatV6 to 8 ( ) 41i1

Vd

t

DSsat +−+=φ

BIPOLAR MOS

Transconductance-to-current-ratio

(gm/ID)

DC Gain(Avo)

Gain-BandwidthProduct (GBW)

Intrinsic CutoffFrequency (fT)

Minimum OutputVoltage (VO)

DC Circuit

Low voltage (LV) power supply circuit design techniques are addressed in this tutorial. In particular:

(i) Introduction;

(ii) Transistor models capable to provide performance and power consumption tradeoffs;

(iii) Low voltage implementation techniques, such as floating gates, self-cascode, low voltage current-mirrors and bulk driven;

(iv) Basic building blocks not involving cascode structures, and

(v) LV circuit implementations examples.

Low Voltage Analog Circuit Design Techniques: Roadmap


(a) Layout (b) Schematic Symbol (c) Equivalent Circuit

Poly I

Poly II

N Diffusion

Metal

VG1

VG2

VG3

S D

VG1

VG2

VGn

CG1

CG2

CGn

CFGB

CFGS

CFGD

VG1VG2

VGn

Floating Gate Transistors

The floating gate voltage VF ,assuming that the initial charge QF in the floating gate is zero,,is described by:

VF = w0V0 + w1V1+ w2V2 + ….. + wnVn

Where wi = Ci/CTOT

CTOT = C0 + C1 + C2 +….+ Cn

Floating Gate MOS TransistorsCG (control Gate)

Poly - I

Poly - II

DS

CO = Cgs + Cgb + Cgd

Assuming Cg >> Cgd,Cgb, an approximate IDS can be obtained:

IDS=Koeff [( VCGS-VT,eff)VDS-CT VDS2/2Cg] ohmic

IDS =Kseff ( VCGS-VT,eff)2 saturation

Cg

Where: VT,eff =VTCO - QFG/Cg

Koeff = Kp(Cg/CT)(W/L), Kseff =Kp(Cg/CT)2(W/L),

CT= CO + Cg

What is the effect of the FG on the transconductance and the output conductance, in the saturation region ?

gm = ( 2K2eff IDS)2 = Cg gcm/CT

go = gco + Cgd gm/Cg

Where gcm and gco are the conventional transconductance and the output conductance of the conventional MOS transistor.

Thus, the FGT has a smaller transconductance and a larger output conductance than conventionalMOS transistor


What is a Self-Cascode Composite Transistor?

M2

M1W/L

m W/LG

D

S

X

(a) Self-Cascode Composite NMOS Transistor (b) Equivalent Simple Transistor

In practical cases, for optimal operation the W/L ratio of M2 should be larger than that of M1, i.e. m>1. The 2-transistor structure can be treated as a composite transistor, which hasa much larger effective channel length (thus lower output conductance).

D

G

S

The lower transistor M1 is equivalent to a resistor, but this resistor is input dependent..The effective transconductance of the composite transistor is approximatelyequal to the transconctance of M1: gm-eff =gm2/m=gm1

Equivalent Transistor Parameter

( )221 2 TXGS VVVi −−=

βXXTGS VVVVi

−−=

2

111 β

For the composite transistor work in saturation region, we know M2 shouldin saturation and M1 is in linear region. Thus, we can write equations for these two transistors as:

Solving we can obtain:1i

( )2

12

122 2

1TGS VVi −

+=

ββ

ββ

From (3), we have12

12

ββ

βββ

+=eq

If 12 ββ ⋅= m 21 11

1βββ

+=

+=

mmm

eq

1ββ =∞>−meq

Comments on VDSATBecause transistor M1 always operates in linear region while the toptransistor operates in saturation or linear region. Voltage between the sourceand drain terminal of M1 is so small that there is no discernable VDSAT

difference in both the composite and simple transistors. Thus,self-cascodestructure can be used in low voltage applications.

The operating voltage of a regular cascode circuit is much higher than that of a single transistor. This characteristic makes regular cascode circuit not suitablefor low voltage applications.

12212 MDMDSATMDSMDSATeqDSAT RIVVVV +=+= −−−−

( )L

WVVC

R

TGSOX

M

−

=

µ

11where

References1. C. Galup-Montoro, etc., “Series-Parallel Association of FET’s for

High Gain and High Frequency Applications”, IEEE JSSC, Sept. 1994

2. D. Ceuster, etc., “Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors”, Electronics Letters, Feb. 1996

3. P. Furth, H. Om’mani, “A 500-nW Floating-Gate Amplifier with Programmable Gain”, IEEE 1999

4. I. Fujimori, T. Sugimoto, “A 1.5V, 4.1mW Dual-Channel Audio Delta-Sigma D/A Converter”, IEEE JSSC, Dec. 1998

5. Personal note from Dr. Ugur Cilingiroglu

6. Yunchu Li, examples and SPICE tables

7. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, “An MOS transistor model for analog circuit design”, IEEE J. Solid-State Circuits, vol. 33, No. 10, pp 1510-

1519, Oct. 1998

Iin

MmM1

Mc

Iout

Vcas

M2IoutVref

Aact

Iin

M1 M2

IoutIin Vref

M1Mm

Mc

Potential LV Current-Mirrors

Goals: To reduce the input impedance and to increase the output Goals: To reduce the input impedance and to increase the output impedance,impedance,while keeping the voltage operationwhile keeping the voltage operation

IoutVrefIin

Mc

MmM1

M2

Vmirror

IoutIin

M1 M3

M2 M4X

Iout

M1 M3

IB IB

M2Vcas

Iin

Iout

Iin

M1 M3

IB IB

M2 M4

M5

Vshift

IoutIin

M1 M2

IoutIin

M1 M2

VddIB1

M3 M4

IB2

Iout

M1 M2

Iin

ROB

AFB

LV CURRENT-SOURCE

A conceptual Schematic of the low voltage current source. (a) Current source representation(b) Architecture

ddV

X Y

Z

A− +

1M2M

IBI

S0R

B0R

(a)

I S0R

xV

(b)

Analog and Mixed-Signal Center (AMSC) TAMU

How can we obtain a large impedance and low head room for the tail current used in a differential pair ?

)g/gA)gg/(gA1(2o

)oB1oo1mos

2o2mooB1o1mog

gg/(Ag1R

−++

++=

where ( )2mg1mg ( )2o1o gg, are the transconductance and output conductance of ( )21 MM ,

respectively. oA is the DC gain of the error amplifier “A” and ( )oBoB Rg is the output

conductance (resistance) of the reference current source BI . Assuming that 1mg 2mg= and

1og 2og= , equation (1) can be simplified as:

oBos RR −≈

Note that the resistance is negative and is equal to the resistance of the reference source .BI

4o3o

4mos gg

gR −≈

(1)

(2)

(3)


ddV

X

Y

Z1M2M

oIS0R

4M

3M

bV

BI DI

V

Current Ref. Error Amplifier A

ssV

Full implementation of the LV current source.


ddV

X Y

Z

A− +

1M2M

IBI

S0R

B0R

(a)

Measured output current of the simple (curve A) and LV (Curve B) current source.


Bulk-Driven MOS Transistor Characteristics

• ID vs. VBS or VGS of bulk-driven and conventional gate-driven MOS transistors

Dra

in C

urre

nt

Gate-Source or Bulk-Source Voltage

-3V -1.5V 0V 1.5V 3V0mA

2mA

4mA

6mA

8mA

Bulk-Source Driven

Gate-Source Driven

ID

1.5V

VGS VBS

Overhead of Bulk-Driven MOS Transistors

The bulk-driven amplifier is more suitable for low voltage operation. Please notice that the maximum allowable voltage at Vx is VDIODE.

M1

Ib1

Vin

Vout

M1

Ib1

Vin

M2

Ib2

M2

Ib2

Vin

Vout

VbVb

Vx Vy

Vdd Vdd

-Vss -Vss

SRVX, Swing range

of Vx

Swing range of Vy

Vdsat,M1

Vdsat,Ib1 Vdsat,Ib1

VGS,M2

SRVX=Vsup-Vdsat,Ib1-Vdsat,M1

SRVY=Vsup-Vdsat,Ib1-VGS,M2

= Vsup-Vdsat,Ib1-Vdsat,M2-VT

(a) (b)

Advantages of Bulk-Driven MOS Transistors

• The depletion characteristic allows zero, negative, and even small positive values of bias voltage to achieve the desired dc current. This can lead to larger input common mode voltage range and voltage swing that could not otherwise be achieved at low power supply voltages. ( Please refer the following example in this section and bulk-driven differential pair discussed in following sections )

• We can use the conventional gate to modulate the bulk-driven MOS transistor.

• Example

Assume for the low voltage amplifiers, power supply voltage is

Vsup = Vdd+|Vss|<VDIODE+Vdsat ,

where VDIODE is the forward Si diode cut-in voltage.

The voltage swing of Vx ( Figure a, the amplifier with bulk-driven MOS FETs ) has only 2Vdsat’s decrease over Vsup. In such a low voltage, the conventional gate-driven amplifier ( Figure b ) fails to operate or may be greatly limited in voltage swing.

Disadvantages of Bulk-Driven MOS Transistors

• The transconductance of a bulk-driven MOS FET is substantially smaller than a conventional gate-driven MOS transistor. This may result in lower GBW and worse frequency response, but better linearity and smaller power supply requirements.

• For a conventional gate-driven MOSFET, the frequency response capacity is described by its transitional frequency, fT,

• For the bulk-driven MOSFET, fT is given by

where is the ratio of gmb to gm and typically has a value in the range of 0.2 to 0.4.

gs

mdrivengateT C

gf

π2, =−

)(2)(2,bsubbs

m

bsubbs

mbdrivenbulkT CC

g

CC

gf

+=

+=−

π

η

π

η

Disadvantages of Bulk-Driven MOS Transistors ( cont’d )

• For typical saturated strong inversion MOSFET operation, the following approximation stands,

• Another disadvantage of bulk-driven MOSFETs is that the polarity of the bulk-driven MOSFETs is process related. For an P well CMOS process, we only have N channel bulk-driven MOSFETs available, and for N well CMOS process, only P channel MOSFETs. This limits its application. We can not use bulk-driven MOS transistors in some circuit structures which requires both N and P MOSFETs.

drivengateTdrivenbulkT ff −− ≈ ,, 8.3η

Disadvantages of Bulk-Driven MOS Transistors ( cont’d )

• MOS transistors can be laid out in the same well, thus their characteristics will match better. Bulk driven transistors are in differential wells, it is inconvenient to design some circuits which require tight matching between transistors. For bulk-driven MOSFETs, it is not easy to utilize some layout techniques such as interdigitized and common centroid layout to make good matching.

• Potentials to turn on the parasitic BJT transistors which may result in latch-up problem

• The equivalent noise of a bulk-driven MOS amplifier is larger than a conventional gate-driven MOS amplifier.

Example of OTAs using different approaches:Example of OTAs using different approaches:Conventional, Conventional, Current DividerCurrent Divider--Source DegenerationSource Degeneration

((CDCD--SDSD), ), Floating GateFloating Gate, and , and Bulk DrivenBulk Driven

Vi+Vi-

Vout

M1 M2

M3 M4M5 M6

VSS

M7 M8

VDD

ISS

M9 M10

VSS

DDESIGNESIGN A A -- RREFERENCEEFERENCE OTAOTA

VVOUTOUT = G= GMMRROUTOUTVVININ

RROUT OUT = = 8.3 Mohms8.3 Mohms

VVININ

RRBIASBIAS

VVBIASBIAS

VVOFFSETOFFSET

IIOUTOUT

IIBIASBIAS

GGMM

1.2 AMI TechnologyVdd=-Vss= 1.35V

EXPERIMENTAL TEST SETUPEXPERIMENTAL TEST SETUP

DDESIGNESIGN A A -- RREFERENCEEFERENCE OTAOTA

Input Ch1 160mVpp @ 1 HzInput Ch1 160mVpp @ 1 HzOutput Ch2 18mVppOutput Ch2 18mVpp THD ~ THD ~ --28dBm ~ 3.9% @160mVpp, 1Hz28dBm ~ 3.9% @160mVpp, 1Hz

DESIGN B - CURRENT DIVISION OTA and Source Degeneration

ISS

Vi+

Vi-

ISS

Vout

VDD

VSS

M1MM1 M2 MM2

M3

M14 M15

M16

M17 M18 M5 M7M6M8

M4M9

M10

M11

M12

VSS

VDD

DDESIGNESIGN B B -- CCURRENTURRENT DDIVISION and IVISION and SD OTASD OTA

Input Ch1 214mVpp @ 1 HzInput Ch1 214mVpp @ 1 HzOutput Ch2 16mVppOutput Ch2 16mVpp THD ~ THD ~ --30dBm ~ 3.2% @214mVpp, 1Hz30dBm ~ 3.2% @214mVpp, 1Hz

DESIGN C - FLOATING GATE OTA, plus SD and CD

Vi- Vi+

ISS

Vb

VDD

VSS

VSS

M1 M2MM1 MM2

M3 M4M5 M6

M7M8M9 M10

Vout

DDESIGNESIGN C C -- FFLOATINGLOATING GGATEATE OTAOTA

Input Ch1 214mVpp @ 1 HzInput Ch1 214mVpp @ 1 HzOutput Ch2 15.2mVppOutput Ch2 15.2mVpp THD ~ THD ~ --34dBm ~ 2% @214mVpp, 1Hz34dBm ~ 2% @214mVpp, 1Hz

DESIGN D - BULK DRIVEN OTA, PLUS CD AND SD

Vi- Vi+

ISS

VG

VDD

VSS

VSS

M1 M2MM1 MM2

M3 M4M5 M6

M7M8M9 M10

Vout

DDESIGNESIGN D D -- BBULK ULK DDRIVENRIVEN OTAOTA

Input Ch1 214mVpp @ 1 HzInput Ch1 214mVpp @ 1 HzOutput Ch2 15.2mVppOutput Ch2 15.2mVpp THD ~ THD ~ --39dBm ~ 1.1% @214mVpp, 1Hz39dBm ~ 1.1% @214mVpp, 1Hz

SIMULATION VS EXPERIMENTAL RESULTS

SIMULATED RESULTS EXPERIMENTAL RESULTS

PAR \ DES A B C D A B C DGM (nA/V) 11.6 11.55 11.51 11.24 10.5 9.3 8.7 8.8∆ϕ @ 1Hz(°)

0.1 0.098 0.047 0.025 <1 <1 <1 <1

Offset (mV) 0.07 0.027 -0.086 0.045 -1.8 -1.9 -1.5 0.647THD (%) 1@162

mVpp1@240mVpp

1@330mVpp

1@900mVpp

3.9@160mVpp

5.6@242mVpp

3.2@330mVpp

5.9@900mVpp

THD (%) @214mVpp

- - - - 3.9 3.2 2 1.1

IBIAS(nA) 2 100 200 500 4 120 230 560VDD = |VSS|(V)

1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35

BIAS (V) N/A N/A -1.35 -1.35 N/A N/A -1.35 -1.35

1.2 micron CMOS Technology

Rail-to-Rail Op Amps

• There are two basic configurations for Op Amp applications:(a) inverting configuration, and,

(b) non-inverting configuration.

R2

R1

VinVout

(a) Inverting Configuration

VoutVin

R1 R2

VoutVin

(b) Non-Inverting Configuration

(c) Voltage Follower( a special case of non-

inverting configuration )

Analog and Mixed-Signal Center,TAMU

Why Rail-to-Rail Differential Input Stage?

• The input and output swings of inverting and non-inverting configurations

Configuration Input common modevoltage swing

Output voltage swing

Inverting ≈ 0 Rail-to-railNon-inverting R1/(R1+R2) * Vsup Rail-to-rail

Voltage follower Rail-to-rail Rail-to-rail

• From the table, we see that for inverting configuration, rail-to-rail input common mode range is not needed. But for non-inverting configuration, some input common mode voltage swing is required, especially for a voltage follower which usually works as an output buffer, we need a rail-to-rail input common mode voltage range! To make an Op Amp work under any circumstance, a differential input with rail-to-rail common mode range is needed.

Analog and Mixed-Signal Center,TAMU

How to Obtain a Rail-to-Rail Input Common Mode Range?

• We know that usually the input stage of an op amp consists of a differential pair. There are two types of differential pairs.

Ib1

To the next stage

To the next stage

Vi+

Vi+

Vi-

Vi-

(a) P-type differential input stage

(b) N-type differential input stage

• First, let us observe how a differential pair works with different input common mode voltage– P-type input differential pair

To the next stage

Vi+Vi-

Input Common Mode Voltage

-Vss Vdd

Itailgm

Vdsat,Ib

VGS,M1,2

VCMR

Vdd

-Vss

Ib

Vicm

M1 M2

Input common mode voltage range

VdsatVGS VCMR ( Common Mode Range )

Where VGS=Vdsat+VT

– N-type differential input stage

Input Common Mode Voltage

-Vss Vdd

Itailgm

Ib

To the next stage

Vi+ Vi-

Vdsat

VGS

VCMR

Vdd

-Vss

Input common mode voltage range

VdsatVGS VCMR ( Common Mode Range )

• Why not connect these two pairs in parallel and try to get a full rail-to-rail range?

Again, how to Obtain a Rail-to-Rail Input Common Mode Range?

Simple N-P complementary input stageAlmost all of the rail-to-rail input stages are doing in this way by some variations! But how well does it work?

Vi+ Vi-

M1 M3 M4 M2

Mb1Mb2

IN

IPIb

Mb3Mb4

Cur

rent

Su

mm

atio

n an

d su

bseq

uent

sta

gesThere should be an

overlap between VCMR,P and VCMR,N , so the minimum power supply voltage requirement is( 4Vdsat+VTN+VTP )

VC

MR

,P

Vdd

-Vss

VdsatVGS VCMR

VC

MR

,N

P Pair N Pair

VSUP ≥≥ 4Vdsat+VTN+VTP

• If

and

IN=IP=ITAIL

then gmN=gmP=gm= .

Region I. When Vicm is close to the negative rail, only P-channel pair operates.The N channel pair is off because its VGS is less than VT. The total transconductance of the differential pair is given by gmT= gmP=gm.

Region II. When Vicm is in the middle range, both of the P and N pairs operate. The total transconductance is given by gmT = gmN+gmP=2gm.

Region III. When Vicm is close to the positive rail, only N-channel pair operates. The total transconductance is given by gmT = gmN=gm.

Common Mode Voltage-Vss Vdd

gm

Gm, the sum of gmN and gmP

gmNgmP

PPNN L

WKP

L

WKPK )(

2

1)(

2

1==

The total transconductance of the input stage varies from gm to 2gm, the variation is 100% !

Region IRegion II

Region III

• Transconductance vs. Vicm

TAILKI2

Observations on transconductance performance for the entire region.-

CM

RR

(dB)

Vio

(mV

)

0

2

4

VI,CM(V)0 0.5 1.0-1.0 -0.5

60

70

80

906

CMRR

Vio

How does the CMRR varies with the input common-mode signal ?

Rail-to-Rail Techniques: Summary and Comparison

Case Principle ∆gm Slew Rate CMRR Advantage LimitationsN/A for weakinversion

1 constII PN =+ [1][2][6

]40% if in stronginversion

Constant 56dB@10Hz,52dB@100KHz,measured in [2]

Small gmvariation ( 6% ) inweak inversionoperation

Only work well in weak inversion, cannot used in high speed application

2 constII PN =+ [3]

[16]

-12% +6% (simulated in thispresentation )

2 timesvariation

80 dB / 53 dB( measured in [3] )

Depends on quadratic characteristics ofMOSFETs, which is not exactlyfollowed for short channel transistors insub-micron processes

3 4 times IN or IP whenonly one pair operates[3][4][6]

+15% systematic gmvariation

2 times variation 70dB / 43 dB( measured in [4] )

Somewhat simple 1) Same with case 2, but we canchange 4 to other numbers to havesmaller gm variation for shortchannel transistors

2) Systematic gm deviation of 15%even for ideal MOSFETs withquadratic characteristics

4 Current switch, backuppairs [5]

+20% systematic gmvariation

Constant N/A Constant slew rate Systematic gm deviation of 20% evenfor ideal MOSFETs with quadraticcharacteristics

5 6-pair structure, backpairs [7]

+20% systematic gmvariation ( analytical),±10% ( measured in[7] )

Constant N/A Constant slew rate Same with Case 4

6 Max/min selection [8][9] 7% ( simulated [9] )5% ( stronginversion, measured[8] )20% ( weakinversion, measured[8] )

Constant N/A Somewhat complex

7 Electronic zener [10] 8% ( measured ) 80 dB / 43 dB( measured in [10] )

Same with Case 2

8 Level shift [11] ±4% after tuning13% before tuning( measured )

≥80 dB ( DC )( measured in [11] )

Simple Gm variation sensitive to VT variationand power supply voltage change

VB

Vi+ Vi-

IB

Io+ Io-

(a)

M1 M2

IB

VB

Vi+ Vi-ViFG+

ViFG-

Io+ Io-

C1

C2 C2'

C1'

(b)

M1 M2IB

Io+ Io-

Vi-

Vi+

VB

(c) Bulk Driven DP

Another Potential Solutions for Rail-to-Rail Amplifiers

Floating Gate DP

M2

M1

M4M3

vI+ vI-

V1

V2 V4

V3vSHIFT

vSHIFT

vSHIFT

vSHIFT

By using dynamic level shift, the rail-to-rail Amplifier can be obtained.

One more Rail-to-Rail Op Amp Technique

R10 R11

R8 R9

Q8 Q9

Q11

Q10Q2

Q1

Q4Q3

vI+ vI-

To

next

sta

ge

VB2

RL1

RL3

RL2

RL4

IL1IL2

IL3 IL4

V1

V2 V4

V3

N-P complementary input stagewith dynamic level shift

Current summation

0.2 0.4 0.6 0.8 1.0

VI,CM (V)

VI,CM

V1 and V3

V2 and V4

V1~V4 andVSHIFT (V)

0.4

0.2

0.6

0.8

1.0

VSHIFT

Q8

Q10Q2

Q1

Q4Q3

vI+ vI-

RL1

RL3

RL2

RL4

IL1 IL2

IL3 IL4

V1

V2 V4

V3

M2

M1

M4M3

vI+ vI-

RL1

RL3

RL2

RL4

N-P complementary input stagewith dynamic level shift

Current summation

vI+ vI-

Lev

el-S

hift

Cur

rent

Gen

erat

or

To

next

sta

ge

IL

Vdd

-Vss

M10 M12

M11

M9

M5M7

M8M6

ML1 ML2 ML3

ML4

ML6ML7 ML8

ML5

References[1] J. H. Huijsing, and D. Linebarger, “Low voltage operational amplifier with rail-to-

rail input and output stages,” IEEE Journal of Solid-State Circuits, vol. SC-20, no.6, pp. 1144-1150, December 1985

[2] W.-C. S. Wu, W. J. Helms, J. A. Kuhn, and B. E. Byrkett, “Digital-compatiblehigh-performance operational amplifier with rail-to-rail input and output ranges,”IEEE Journal of Solid-State Circuits, vol. 29 , no. 1, pp. 63-66, January 1994

[3] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F. Wassenaar, andJ. H. Huijsing, “CMOS low-voltage operational amplifiers with constant-gm rail-

IEEE Proc. ISCAS 1992, pp. 2876-2879[4] R. Hogervost, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, “A compact

power-efficient 3-V CMOS rail-to-rail input/output operational amplifier for VLSIcell libraries,” IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1505-1513, December 1994

[5] R. Hogervorst, S. M. Safai, and J. H. Huijsing, “A programmable 3-V CMOS rail-to-rail opamp with gain boosting for driving heavy loads,” IEEE Proc. ISCAS1995, pp. 1544-1547

[6] J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, “Low-power low-voltageVLSI operational amplifier cells,” IEEE Trans. Circuits and Systems-I, vol. 42. no.11, pp. 841-852, November 1995

References ( cont’d )[7] W. Redman-White, “A high bandwidth constant gm, and slew-rate rail-to-rail

CMOS input circuit and its application to analog cell for low voltage VLSIsystems,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 701-712, May1997

[8] C. Hwang, A. Motamed, and M. Ismail, “LV opamp with programmable rail-to-rail constant-gm,” IEEE Proc. ISCAS 1997, pp. 1988-1959

[9] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm input-stagearchitecture for low-voltage op amps,” IEEE Trans. Circuits and Systems-I, vol.42. no. 11, pp. 886-895, November 1995

[10] R. Hogervost, J. P. Tero, and J. H. Huijsing, “Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode,” IEEE Journal ofSolid-State Circuits, vol. 31, no. 7, pp. 1035-1040, July 1996

[11] M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Sánchez-Sinencio,“Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition

IEEE Journal of Solid-State Circuits, vol. 34, no. 2, pp. 148-156,February 1999

[12] G. Ferri and W. Sansen, “A rail-to-rail constant-gm low-voltage CMOSoperational transconductance amplifier,” IEEE Journal of Solid-State Circuits, vol.32, no. 10, pp. 1563-1567, October 1997

References ( cont’d )[13] S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operational amplifiers for a

IEEE Journal of Solid-State Circuits, vol. 31, no. 2, pp. 146-156, February 1996

[14] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “Simple rail-to-rail low-voltage constanttransconductance CMOS input stage in weak inversion,” Electronics Letters, vol. 29, no. 12,pp. 1145-1147, June 1993

[15] V. I. Prodanov and M. M. Green, “Simple rail-to-rail constant transconductance input stageoperating in strong inversion,” IEEE 39th Midwest Symposium on Circuits and Systems, vol2, pp. 957-960, August 1996

[16] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “A low voltage CMOS op amp with arail-to-rail constant-gm input stage and a class AB rail-to-rail output stage,” IEEE Proc.ISCAS 1993, vol. 2, pp. 1314-1317, May 1993

[17] J. F. Duque-Carrillo, J. M. Valverde, and R. Perez-Aloe, “Constant-gm rail-to-rail common-IEEE Journal of Solid-State

Circuits , vol. 28, no. 6, pp. 661-666, June 1993[18] A. L. Coban and P. E. Allen, “A low-voltage CMOS op amp with rail-to-rail constant-gm

input stage and high-gain output stage,” IEEE Proc. ISCAS 1995, vol. 2, pp. 1548-1551,April-May 1995

[19] J.F.Duque-Carrillo et al, “ 1-V Rail-to-Rail Operational Amplifiers in Standard CMOS IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 33-44, January 2000

Voltage Multistage Transconductance Amplifier TopologiesFor LV Power Supply.

• Good voltage gain can be obtained using cascode stages. But these stagesare not amenable for LV power supply.

• Under LV conditions, high voltage can be obtained using cascade amplifiers.That is growing horizontally, rather than vertically.

• Direct Cascade of simple (inverting) stages gives the required voltage gainwithout control of poles and zeroes.

• Dynamic behavior for optimal performance requires feedback (and feedforward) circuits.

Analog & Mixed-Signal Center (AMSC)

First Approach: Direct Cascade

0V

2mg1mg CL

inV

Symbolic Representation

PC

iV 0V1M 2MxV

1bI 2bI

(a)

iV1M

1bI

2bIPC

2M

xV

(b)

Two Possible Implementations

0201

2m1m

L

02p

p

01p

2

0201

Lp

01

p

02

L

Lp2m1m

in

0

gg

gg)o(H

C

g ,

C

g

at located are poles The

sgg

CC

g

C

g

Cs1

CC/gg

)s(V

)s(V)s(H

21

=

=ω=ω

+

++

+≅=

PC


How do you bring one pole close to the origin?

-Use feedback

0V

2mg1mg LC

inV

pC

1mC

Neglect Cp (i.e., Cp<<Cm1)

( )( ) 1mL0201L02L2mpL1mL012

1mL1m2m1m

in

0

CC/ggC/gC/gCC/CCgss

CC/)sCg(g

)s(V

)s(V)s(H

+++++

−==

1m

2mz

02012mm1

pp

V1m

01

2m

02

1m

01pL022mp

C

g

RHP at the zero a is news bad The

gain voltageDC Large gg/ggH(o)

stabilityfor Good

: thatis news good The

A

1

C

g

g

g

C

g and C/)gg(

:at locatedely approximat are poles The

1

21

0212

=ω

=

ω<<ω

=

≅ω+≅ω


Now we will use a feedforward circuit to cancel the zero at the RHP.

This will impact the complexity and performance of the design.

1mgmfg

)s(H

=02012m1mL1m

22m1m

gggsCCCs

gg

++

−=

This can be extended to higher-order systems, let us consider first athird-order system.


0V

1mC

1mg 2mg

mfg

inV

LC

No zero

( )( ) 1mL0201L02L2mpL1mL012

1mL1m2m1m

in

0

CC/ggC/gC/gCC/CCgss

CC/)sCg(g

)s(V

)s(V)s(H

+++++

−==

Now the corresponding H(s) becomes:

Recall that before applying the feedforward we had:

1mfg

1mg

1mC

iV 0V2mC

2mg 3mg

2mfg

CL

Three-stage amplifier topology with NGCC

( ) ( )

( ) 2m1mL3

2m1m2m2mf3m2

1m3m2m030201

2m1m1m1mf2m2m2mf1m3m2m1m

i

0

CCCsCCgggsCgsgggg

CCggCggsgggg

)s(V

)s(V)s(H

+−+++

−+−+==

2m1mL3

2m1m3m2

1m3m2m030201

3m2m1m

i

0

2mmf21mmf1

CCCsCCgsCgsgggg

ggg

)s(V

)s(V)s(H

,gg and gg makingBy

+++

−==

==


Nested Gm-C Compensation Amplifier.

30VV01m

01

1m3m2m

030201

030201

3m2m1m

1m

1m

0

11

mi

mii

L2m

3m2m32

2m

2m2

1m

1m1

020301

2m3m1m0

32

2

21

0

0

AA

1

C

g

Cgg

ggg

ggg

gggC

g

A

fP

at located is poledominant that theNote

C

gf ;

CC

ggff ,

C

gf

C

gGBf and

ggg

gggA

ffs

fs

1 f

As1

A-H(s)

as written becan H(s) This

2

====

===

===

++

+

=


1 2 3

1 2 3

1mC2mC

3mC

1mg 2mg 3mg

mfg

4mg−

iV 0V

1mC2mC

3mC 0ViV

1mg 2mg 3mg

mfg

4mg−

iV 0V

1mg 2mg

mfg

1mC

(a) Multipath nested miller compensation topology.FF

(b) An abstract model for the amplifier proposed byCastello, et.al.

(c ) The amplifier with multipath miller zerocancellation.

Multipath Nested Miller Compensation TechnologyPotential Feedforward Schemes: An Amplifier Topologies Re-Visit.


iV 0V

1mg 2mg

3mfg

1mC

3mg 4mg

2mfg

1mfg

2mC

3mC

CL

Four stage amplifier topology with NGCC (Fan You et al)

Let Us Now Compare Several Four-Order Topologies

( )

mi

mi

i3m2m

3m2m

32

4323

322

21

01

33

221

1

0

gC

f1

, gg

CC

ff1

fff

1a ,

ff

1a ,

f

1a

A

GBP

sasasa1 P

s1

A)s(H

==

===

=

+++

+

−=

( )

ly.respective factors,ion normalizatfrequency andcurrent are f and I

C

gf ,

C

C ,

f

f1IVVP

nComsumptioPower

f/f1

ff

GBf , ffff

nn

L

miii

L

mii

1n

1i n

iinssDD

32

24

14321

=α=α

∑

α+−=

•

−>

=≤<<

−

=

Comparison of Several Topologies.

00

1143210

mi

mii

oi

mii

33

2211

33

221

0i

0

A

GB

A

fP , kkkkA

Where

C

gf and 1,3i ,

g

gk

, )sasasa)(1P/s1(

sbsbsb1A

)s(V

)s(V

===

===

++++

−−−−=

Comparison of Polynomial Coefficients for Four Stage NMC and NGCC Amplifier.

Ph(s)

NMC

NGCC

NMC

NGCC

Z(s)

a1 a2 a3

b1 b2 b3

( )

4m2m

3m2m2m4mgg

CgCg − ( )

4m3m2m

3m2m3m2m4mggg

CCggg −−

2m

2mgC

3m2m

3m2mggCC

4m3m2m

L3m2mggg

CCC

4m3m2m

L3m2mggg

CCC

4m

3mgC

0 0 0

4m3m

3m2mggCC

4m3m2m

3m2m1mgggCCC

Design

Complex

Simple


iV 0V

1mg 2mg

mfng

1mC

mng 1gmn +

n Level

2 Level2mfg

1mfg 1 Level

2mC

mnC

1mfg

1mg )s(A

1mCiV 0V

Conceptual multistage amplifier topology with NGCC.

Abstract model.

Nested Gm-C Compensation (NGCC) Nth-Order


iV 0V

1mG 2mG

1mfG

1mC

iV

outV

ddV

ssV1mg

1bV

2bV

2mg12M

22M

21M

1Mf

1mfg

13M

14M

11M

(a) Representation

(b) Transistor Level

How to Implement a Positive Gm?

M22. toparallelin

r transistoPMOS a add and M21 Remove , GG If

current. additional provide toM21

add then ,current Mf1current M22 , GG If

1MfG

gg , 22M21MG

gg , 14M11MG

1mfm2

1mfm2

1mf

2mmM222m

1mmM111m

>•

>>•

⇒

=−⇒

=−⇒


ddV

ssV1mg 2mg 3mg

3M 5M4M

−V +V1mC

2mC 3mC outV

4mg

2mfg

3mfg3bV

2bV

1bV

1mfg

Four stage operational amplifier with NGCC topology

Design Example of a Four-Stage Amplifier


Measured Performance of the 4-Stage NGCC Op Amp.

22

oo

0.22mm 0.22mm Area

//20pF10k 20//10k Condition Load

1.0V 1.0V Supply Power

5.0V S2.5V/ Rate Slew

5.2mV 5.2mV Offset Input

58 60 Margin Phase

1.0MHz 610kHz Bandwidth Gain

100dB 100dB Gain DC

1.40mW 0.68mW n ConsumptioPower

ΩΩ

±±

≈≈

pF

µ


0

1

2

3

4

5

6

7

8

1 2 3 4 5 6 7 80

20

40

60

80Phase MarginTs*GB

f4/GB

___

-----

phase

Ts

The phase margin and normalized settling time (TsGB) of anNGCC amplifier vs. f4/GB.


What is the effect of f4 /GB?

How far should one push f4?

• Trade-off between phase margin versus setting time.

*

*

*

*

*

**

* * * *

+

+

+

++

++ + +

0.5 1 1.5 2 2.5 33

3.5

4

4.5

5

5.5

6

6.5

7

7.5

8

NMC

NGCC

Ts*GB

Nor

mal

ized

Pow

er

The normalized power consumption of the NGCC and the NMC amplifiers asa function of the normalized settling time.


How do the Two Topologies Compare for Power Consumption?


More Experimental Results.

References

S. Pernici, “A CMOS Low-Distortion Fully Differential Power Amplifier with Double NestedMiller Compensation,” IEEE J. Solid-State Circuits, Vol. 28, No. 7, pp. 758-763, July 1993.

F. You, S.H.K. Embabi and E. Sánchez-Sinencio, “Multistage Amplifier Topologies with Nested Gm-C Compensation,” IEEE J. of Solid-State Circuits, Vol. 32, No. 12, pp. 2000-2011,December 1997.

K.N. Leung, P.K. T. Mok, W.-H. Ki, and J. K. O. Sin, “ Three-Stage Large Capacitive Load Amplifier with Damping Factor-Control Frequency Compensation, “IEEE J. of Solid-State Circuits, Vol. 35, No. 2, pp. 221-230, February 2000


S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial, IEICE Trans. Fundamentals, Vol. E83-A, No. 2 February 2000

E. Sánchez-Sinencio and Andreas G. Andreou, Eds. “ Low-Voltage/Low-Power Integrated Circuits and Systems “, IEEE Press, Piscataway, NJ 1999

A. Rodriguez-Vazquez and E. Sánchez-Sinencio, Eds., Special Issue on Low-Voltage and Low-Power Analog and Mixed-Signal Circuits and Systems, IEEE Trans. on Circuits and Systems I, vol. 42, No. 11, November 1995

Conclusions

• Low power supply and smaller size technologies require new analog circuit techniques

• Power Consumption and area are critical specifications in portable equipment, clever design methodologies are needed.


Joe Edgar

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