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Int. J. Electron. Commun. (AEÜ) 66 (2012) 655– 658

Contents lists available at SciVerse ScienceDirect

International Journal of Electronics andCommunications (AEÜ)

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tunable CMOS Wilkinson power divider using active inductors

en Wang ∗, Rui-Xian Wangraduate Institute of Computer and Communication Engineering, National Taipei University of Technology, 1, Sec. 3, Chung-hsiao E. Road, Taipei 10608, Taiwan, ROC

r t i c l e i n f o

rticle history:eceived 22 September 2011ccepted 6 December 2011

a b s t r a c t

This paper presents the design and implementation of a tunable CMOS Wilkinson power divider usingactive inductors. Compared to a conventional active inductor topology, the proposed active inductor

eywords:ctive inductorsilkinson power dividers

umped circuits

features higher inductance tuning range, higher self-resonant frequency, and lower power consumptionby introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkin-son power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mWdemonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. More-over, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth.The active chip size of the lumped design is merely 0.25 mm × 0.15 mm.

MOS

. Introduction

Conventional Wilkinson power dividers (WPDs) are widely usedn the radio-frequency (RF) frond-end of communication systemsor equal power splitting with in-phase responses at differentutput ports [1–4]. Recently, many dual-band, multi-band, andnequal power splitting WPDs are reported for facilitating theystem integration and simplifying the architecture of the RF font-nd [5–7]. However, these transmission line (TL) based WPDs onhe printed-circuit board (PCB) still occupy large chip area com-ared to on-chip circuits, and thus increase the cost and incurdditional power consumption of packaging. CMOS technologieseature low-cost manufacturing and high-volume integrating capa-ilities, and rapid developments of wireless communications makeystems on a single chip (SOC) practical [8,9]. However, frequency-caling and TL-based circuits do not benefit from the acceleratedrocess scaling of CMOS technologies. Therefore most of on-chipistributed circuits are implemented at millimeter-wave frequen-ies for the chip area and insertion loss consideration. [10,11].oreover, peak-Q factors of CMOS inductors suffering from its low-

esistivity substrate are around 10, which limits lumped designsy LC components at microwave frequencies. Typically, acceptableerformances of the passive circuits require inductors with Q-factorf 30 at least.

To reduce the circuit size of distributed TLs and low-Q passive

nductors, many applications of active inductors which are suitableor monolithic system integration are presented [12–15]. Advan-ages of the active inductor include the high-Q factor, reduced

∗ Corresponding author. Tel.: +886 2 2771 2171x2226; fax: +886 2 2731 7120.E-mail addresses: wangsen@ntut.edu.tw (S. Wang),

ick121300653@hotmail.com (R.-X. Wang).

434-8411/$ – see front matter © 2012 Elsevier GmbH. All rights reserved.oi:10.1016/j.aeue.2011.12.005

© 2012 Elsevier GmbH. All rights reserved.

chip area, and easily integrated with other circuits in a singlechip. These circuits successfully demonstrate a good electricalperformance and a significant area reduction due to the activeinductors. However, the transistor-based inductors also pay for ahigh power dc consumption, high noise level, poor linearity, andlow operating frequencies. In this paper, a tunable Wilkinson powerdivider using active inductors is designed and fabricated. Com-pared to a conventional active inductor topology, the proposedactive inductor features higher inductance tuning range, higherself-resonant frequency, and lower power consumption by intro-ducing two additional transistors. With the high-Q factors andtunable inductances provided by the proposed active inductors,the WPD exhibits enhanced performance in terms of insertion loss,return loss, and port isolation while maintaining a wide frequencytuning range. The design will be detailed in the following sections.In Section 2, the design of the tunable Wilkinson power dividerwill be presented. Moreover, simulated and measured results ofthe design implemented in a standard 0.18-�m CMOS process arealso reported in Section 3. Finally, Section 4 concludes this work.

2. Design of tunable Wilkinson power divider

Fig. 1(a) depicts a conventional TL-based WPD with two 3�/4-long TLs and one isolation resistor between the output ports. Adistributed TL with a characteristic impedance of Z0 and an elec-trical length of ˇl can be equivalent to its lumped equivalentT-networks as shown in Fig. 1(b). The lumped LC components can bederived from the ABCD matrices of a 3�/4-long TL and the lumped

T-network. Therefore, by equating the matrices in (1) the corre-sponding Cs and Lp can be obtained as shown in (2) and (3). Whereω is the operating frequency, and Z0 is 50 � in the equations.Typically, inferior Q-factors of CMOS inductors degrade the

656 S. Wang, R.-X. Wang / Int. J. Electron. Commun. (AEÜ) 66 (2012) 655– 658

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Table 1Circuit parameters of the Wilkinson power divider.

Device and setting Unit Designed value

M1 �m/�m 62/0.18M2 �m/�m 49.6/0.18M3 �m/�m 32/0.18M4 �m/�m 50.4/0.18R � 100C pF 0.28I1 mA 0.68–1.45I2 mA 0.9–2.1I3 mA 0.28–1.8

ig. 1. (a) A distributed Wilkinson power divider. (b) A lumped Wilkinson power

ivider.

lectrical characteristics such as insertion losses, return losses, andsolation of a WPD. To improve the low-Q factors and to avoid therea-consuming passive inductors, a high-Q and high self-resonantrequency active inductor with low-power consumption is devel-ped for the lumped WPD.

cos ˇl jZ0 sin ˇljY0 sin ˇl cos ˇl

]=

[0 −jZ0−jY0 0

]

=

⎡⎢⎣

1 − 1ω2LpCs

2jωCs

− 1

jω3C2s Lp

1jωLp

1 − 1ω2LpCs

⎤⎥⎦ (1)

s = 1√2Z0ω

(2)

p =√

2Z0

ω(3)

Fig. 2 shows the complete schematic of the proposed lumpedPD using two active inductors. A conventional active inductor

nly consists of a back-to-back configuration of transistors M1 and2 [12–15]. And the equivalent inductance and Q factors can beerely tuned by the aspect ratio and trans-conductance of the

wo transistors. Moreover, this topology is impractical due to thexcess phase error and trans-conductance degradation contributedy the intrinsic device capacitances at higher frequencies (>5 GHz)16]. The proposed active inductor introduces two additional tran-istors M3 and M4 as shown in Fig. 2. In order to simplify thenalysis, two assumptions gm � gds and Cgs � Cgd in the transistorsre supposed, and the analysis procedure is similar to [17]. Thenhe input impedance Zin including an inductance Leq in series with

resistance Req can be approximated Eqs. (4) and (5). The tran-istor M3 stacking on top of M1 contributes a negative resistanceo compensate resistive losses of the inductor. The active induc-

or is mainly determined by M1, M2, and M3. Typically, a largegs3 while maintaining circuit stability is favorable for a high-Q

nductor with low-power consumption. And unnecessary negativeesistances of the active inductor would result in circuit potentially

Fig. 2. Schematic of the proposed Wilkinson power divider.

Vd V 1.5–1.8Vt V 1.4–2

unstable, especially at high frequencies. In order to avoid the bodyeffect of M2 and M3, these transistors are all implemented in sep-arate regions and wells. By adding the M4, the term gds4/gm4 willresult in a decrease of Req because gm4 is much larger than gds4.Therefore, the M4 can be controlled by varying I3 or Vt, and the Qfactors of the inductor can be tuned independently at operating fre-quencies. Moreover, the M4 is designed to minimize circuit powerconsumption and maintain circuit stability, which will not degradethe inductor at high frequencies. Table 1 summarizes the designparameters and the current settings of the proposed circuit.

Leq �gm2gm3Cgs2 + ω2C2

gs2Cgs3

gm1g2m2gm3 + ω2gm1gm3C2

gs2

(4)

Req � gm2gds3gds1(gds4/gm4) + ω2Cgs2(gm3Cgs2 − gm2Cgs3)

gm1g2m2gm3 + ω2gm1gm3C2

gs2

(5)

The active inductor is conducted by the advanced design sys-tem (ADS) simulator, and the capacitors or interconnections areconducted by the full-wave electromagnetic, or high frequencystructure simulator (HFSS). Fig. 3 shows the simulated inductancesand quality factors of the active inductor under different biasingconditions and power consumptions. The aspect ratio of M1, M2, M3,and M4 is (62 �m/0.18 �m), (49.6 �m/0.18 �m), (32 �m/0.18 �m),and (50.4 �m/0.18 �m), respectively. The self-resonant frequen-cies of the proposed inductor are all higher than 8 GHz, and thetunable inductance ranges from 0.89 nH (at 10.4 GHz) to 2.55 nH(at 5.8 GHz) as shown in Fig. 3(a). The power consumption of eachtunable curve is also marked. Typically, the active inductor con-sumes higher power at higher frequencies. Moreover, the peak-Qfactors tuned by Vd and Vt are 39 at least which are acceptable forthe low-loss WPD design. The proposed WPD operates at 8 GHz,and therefore the corresponding Cs of 0.28 pF and Lp of 1.4 nH arerequired. A further tunable design can be achieved by adjusting thebias conditions.

3. Implementation, measurement, and discussion

The circuit is fabricated in a standard mixed-signal/RF bulk 0.18-�m CMOS process. Typically, 1.8 V-NMOS transistors of the processfeature a threshold voltage (Vt) of 0.42 V, gate oxide thickness (tox)of 4.08 nm, and transit frequency (ft) of 48 GHz. The process alsoprovides poly silicon resistors, metal-oxide-metal (MOM) capaci-tors with a 1.1-fF/�m2 capacitance density, and six metal layers(M1 to M6). The MOM capacitors are implemented from M1 toM5 layers for achieving high capacitance density. Fig. 4(a) showsthe chip photo of the fabricated Wilkinson power divider. The chip

area including all test pads is 0.64 mm × 0.61 mm, where the activearea occupies only 0.25 mm × 0.15 mm. The upper and lower padsprovide dc supply for the circuit, and the power lines are realizedfrom the top metal layer (M6) to the M5 layer through via to avoid

S. Wang, R.-X. Wang / Int. J. Electron. Commun. (AEÜ) 66 (2012) 655– 658 657

1412108642-4

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2

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5.1mW

Indu

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ce (n

H)

Vd=1.5V Vt=1.4V Vd=1.7V Vt=1.6V Vd=1.8V Vt=2.0V

2.8mW

14121086420

20

40

60

80

100

120

10mW

5.1mW

Qua

lity

Fact

or

Vd=1.5V Vt=1.4V Vd=1.7V Vt=1.6V Vd=1.8V Vt=2.0V

2.8mW

rs of t

ut

coprFpci

Fo

Frequency (GHz)

Fig. 3. (a) Simulated inductances and (b) quality facto

nnecessary voltage drop. The left-hand and right-hand pads arehe input and output ports as marked in the chip photo.

Three-port S-parameter experiments of the lumped circuit wereharacterized by on-wafer measurements. The undesired parasiticf pads and interconnections were removed by a de-embeddingrocedure. Good agreements between simulated and measuredesults are also observed to validate the design methodology.

ig. 4(b) shows the simulated and measured results of the lumpedower divider operating at a center frequency of 8 GHz. The cir-uit consumes 10.2 mW, and the isolation between output portss about 22.6 dB. Moreover, the insertion loss and return loss is

ig. 4. (a) Chip photo. (b) Simulated and measured results of the circuit operating at 8 GHzf the tunable circuit.

Frequency (GHz)

he active inductor under different biasing conditions.

0.67 dB and 27 dB at the frequency of interest. The tuning rangeof the circuit is between 5.8 GHz and 10.4 GHz, demonstrating a4.6 GHz bandwidth. The measured insertion loss at 5.8 GHz and10.4 GHz is 1.1 dB and 0.65 dB, respectively. The tunable divideroperating at 5.8 GHz and 10.4 GHz consumes 5.6 mW and 20 mW,respectively. Typically, higher operating frequencies of the circuitdemonstrate higher power consumption as shown in Fig. 4(c). The

input P1 dB of the tunable circuit is also investigated. Typically, thecircuit at higher frequencies features better input P1 dB due to thehigh supply voltage providing large voltage swings at transistors asshown in Fig. 4(d). Table 2 summarizes the comparisons of the two

. (c) Measured |S21| of the tunable circuit. (d) Input P1 dB versus operating frequency

658 S. Wang, R.-X. Wang / Int. J. Electron. Commun. (AEÜ) 66 (2012) 655– 658

Table 2Comparisons with the two lumped Wilkinson power dividers.

Parameter [12] This work

Process 0.18 �m CMOS 0.18 �m CMOS

Topology of active inductor Conventional (M1 and M2) Proposed (M1, M2, M3, M4)

f0 (GHz) 4.0 4.5 5.0 5.8 8.0 10.4Insertion loss (dB) 0.68 0.16 0.7 1.1 0.67 0.65Return loss (dB) 26 30.1 22.6 21 27 29Isolation (dB) 19.7 27 23 15 22.6 17.4

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R.O.C., in 2010. He is currently working toward the M.S.degree in Graduate Institute of Computer and Commu-nication engineering at the National Taipei University ofTechnology, Taipei, Taiwan, R.O.C. His research interestsinclude CMOS RF integrated circuits.

Input P1 dB (dBm) N.A. −10

PDC (mW) 15.6 16.7

Overall chip area (mm2) 0.385

MOS Wilkinson power dividers using active inductors. It revealshat the proposed design demonstrate high operating frequencies,ide tuning range, and low power consumption.

. Conclusion

In this paper, a compact and tunable Wilkinson power dividersing active inductors in a standard 0.18-�m CMOS process isresented. Due to the lumped design concept, a significant areaeduction is achieved, especially for applications at microwave fre-uencies. Compared to a conventional active inductor topology,he proposed active inductor features higher inductance tuningange, higher self-resonant frequency, and lower power consump-ion by introducing two additional transistors (M3 and M4). Withhe high-Q factors and tunable inductances provided by the activenductors, the WPD exhibits enhanced performance in terms ofnsertion loss, return loss, and port isolation while maintaining a

ide frequency tuning range. Good agreement between measurednd simulated results and good electrical characteristics of thePD demonstrate the feasibility of lumped designs using the active

nductor beyond 10 GHz. It is believed that the active inductor isuitable for further practical applications such as filters and phasehifters.

cknowledgements

The authors would like to thank the Chip Implementation CenterCIC) and National Science Council (NSC) of Taiwan for the chipmplementation and financial supports.

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Sen Wang received the B.S. degree in electrical engi-neering from National Taiwan University, Taipei, Taiwan,R.O.C., in 2004, the M.S. degree and Ph.D. degree in gradu-ate institute of communication engineering from NationalTaiwan University, Taipei, Taiwan, R.O.C., in 2006 and2009, respectively. He joined the Faculty of the Depart-ment of Electronic Engineering, National Taipei Universityof Technology, Taipei, Taiwan, as an Assistant Professor inFebruary 2010. His research interests include the designof microwave/millimeter-wave passive circuits, CMOS RFintegrated circuits, and radar system engineering.

Rui-Xian Wang was born in Taichung, Taiwan, R.O.C., in1987. He received the B.S. degree in electrical engineer-ing from the National United University, Miaoli, Taiwan,