A Temperature-Aware Design Methodologyfor Die-Level Thermal AnalysisNanda GopalGradient Design Automation

OutlineIntroductionThermal Effects on Circuit PerformanceFireBolt Thermal Analysis EngineTemperature-Aware Design MethodologyBridging the Thermal Modeling GapConclusion

The Thermal Modeling GapChip assembly is too often a one-way process

Thermal models of the die and package are developed with scarce knowledge of each otherThere is a clear gap in the thermal modeling flowThe increasing dominance of temperature as a performance limiting factor requires this gap be bridged

Technology Impacts on Chip BehaviorProcess trends:

Design trends:

Lower device thresholdsIncreased leakage currentFiner geometriesHigher wire resistanceCopper metallizationHigher conductor currentsLow-k dielectricsPoor thermal conductivity

Larger die sizeIncreased device countIncreasing complexityMixed-signal, multi-core, SIP, Increasing performanceIncreased total powerAggressive power managemntHighly variant chip power profile

Die Temperature is Not Uniform/ConstantOn-chip temperature can vary by as much as 500CSpatial temperature distribution will never attain a uniform, constant value as long as the power distribution varies

Design Challenges at Nanometer ProcessesTiming ClosureSignal IntegrityVoltage DropPowerTemperatureElectromigration180nm130nm90nm65nm

Thermal Impact on PowerLeakage power is seen as dominant at 90nm and belowDevice leakage is exponentially dependent on temperature

Thermal Effects on TimingCell performance is impacted by voltage drop & temperatureClock skews are extremely sensitive to on-chip variationsDelay inversion effects are being observed at 65nm

Thermal Impact on ReliabilityBlacks equation is used to calculate Mean Time To Failure

Exponential dependence of MTTF on temperature can drastically reduce product lifetimes 50-75 years @ 60oC 1000-1500 hrs @ 90oC

Self heating not considered today

Current Design MethodologyLack of predictive and deterministic temperature dataAnalysis tools run with inaccurate thermal assumptionsTemperature incorrectly deduced from powerUndetected potential failuresCostly guard-bands and over-designPoor product reliabilityThermal management systems inadequateIncorrect placement of temperature sensing diodesSelf-heat in metallization ignored

FireBolt Thermal Analysis EngineTiming analysisIR drop analysisBegin thermal analysisEM analysisSilicon verified

FireBolt TechnologyInnovative, high capacity, adaptive algorithmsIncorporation of package and boundary conditionsBond wire/bumps, molding compounds, epoxies, etc.True 3D modeling and analysisPower sources on all layers (devices, wires, vias)Mixed-level analysis (block device)Detailed temperature for all design objects on all layersComprehensive data visualizationTemperature, power, power density, heat flux, Built on the OpenAccess data model for easy integration

FireBolt Data VisualizationPowerTemperatureThermal ContoursThermal Surface3D ThermalIsotherms

Silicon Verification

Thermally-Aware Design FlowBuild physical prototypeRun rail analysisFireBolt3D thermal analysisIncr. SDFPerformance-driven Design FlowThermal delay calculator

Package ModelsPackage models have viewed the die as a point heat source while increasing the resolution of the package itself

Distributed die temperature must now be considered in the package world to improve overall accuracy

Bridging the Thermal Model GapAccuracy of package thermal prediction can be improved by coupling 3D package simulation with FireBoltAllows inclusion of complex cooling mechanismsProvides a bridge between package and design worldsFireBoltFlomericsDesignPackage modelLayoutDie thermal profile

Iterative Refinement of Thermal ModelsPackage model at horizontal face of dieThermal profile at horizontal face of dieFlomericsFireBolt

Effect of Die Temperature on Air FlowAir flow

ConclusionChip-level thermal analysis is essential for designs