A Superposable Silicon Synapse with Programmable Reversal ...

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A Superposable Silicon Synapse with Programmable Reversal Potential Ben V. Benjamin 1 , John V. Arthur 2 , Peiran Gao 1 , Paul Merolla 2 , and Kwabena Boahen 1 Abstract— We present a novel log-domain silicon synapse de- signed for subthreshold analog operation that emulates common synaptic interactions found in biology. Our circuit models the dynamic gating of ion-channel conductances by emulating the processes of neurotransmitter release–reuptake and receptor binding–unbinding in a superposable fashion: Only a single circuit is required to model the entire population of synapses (of a given type) that a biological neuron receives. Unlike previous designs, which are strictly excitatory or inhibitory, our silicon synapse implements—for the first time in the log-domain—a programmable reversal potential (i.e., driving force). To demonstrate our design’s scalability, we fabricated in 180nm CMOS an array of 64K silicon neurons, each with four independent superposable synapse circuits occupying 11.0×21.5 μm 2 apiece. After verifying that these synapses have the predicted effect on the neurons’ spike rate, we explored a recurrent network where the synapses’ reversal potentials are set near the neurons’ threshold, acting as shunts. These shunting synapses synchronized neuronal spiking more robustly than nonshunting synapses, confirming that reversal potentials can have important network-level implications. I. LOG- DOMAIN NEURONS AND SYNAPSES Neuromorphic engineering aims to emulate computations carried out in the nervous system by mimicking neurons and their interconnectivity in VLSI hardware [1]. Having succeeded in morphing visual and auditory sensory systems into mixed-analog-digital circuits, engineers are entering the arena of cortical modeling [2], [3], [4]; an arena in which neuromorphic systems’ parallel operation and low energy consumption give them distinct advantages over software simulation. The neuron model of choice for large-scale cortical simulations [5], the quadratic integrate-and-fire (QIF) neuron, has been implemented successfully with log-domain circuits [6], [7], [8], [9]. The corresponding synapse model, a conductance tied to a programmable reversal potential, is however yet to be fully implemented in the log-domain. Existing log-domain conductance-based silicon synapse designs are either purely excitatory or purely inhibitory [6], [10], [11]. In contrast, biological synapses behave like a con- ductance that drives the membrane toward a fixed voltage— the reversal potential—that can be excitatory (much higher), inhibitory (much lower), or shunting (near the membrane’s spike threshold). Shunting synapses have been shown to synchronize a heterogeneous population of neurons more Supported by a NIH Director’s Pioneer Award (DPI-OD000965) and the Samsung Advanced Institute of Technology GRO Program. 1 B. Benjamin is with Electrical Engineering and P. Gao and K. Boa- hen are with Bioengineering, Stanford University, Stanford CA, U.S.A. {benvb,prgao,boahen}@stanford.edu 2 J. Arthur and P. Merolla were with Bioengineering, Stanford University, Stanford CA, U.S.A. {arthurjo,pameroll}@us.ibm.com M R4 M R1 C R M C1 M C2 C C M A1 M A2 M E5 M E4 M E3 M E1 M E2 M G1 M G2 M G3 M G4 M R3 M R2 V spk M S1 C m M S7 I lk I erev V m Fig. 1. Superposable silicon synapse, together with biasing and neuron circuitry (gray). The cleft (M C1-2 ) models spike-triggered neurotransmitter release and reuptake: M C1 discharges C C to ground (release) and M C2 charges C C back up to V DD (reuptake). The receptor (M R1-4 ) models receptor binding and unbinding: M R1 discharges C R to a limit set by M R2 (binding) and M R3 charges it back up to V DD (unbinding). The diffusor (M G1-4 ) models spatial decay: M R4 ’s current, mirrored by M A1-2 , spreads through M G1-3 into a hexagonal grid. The reverser (M E1-5 ) models a conductance and its reversal potential: M G4 sets M E4 ’s & M E5 ’s currents (conductance) and M E3 sets how much the former’s current is scaled (reversal potential). These currents drive the neuron’s capacitor (Cm), together with a leakage current (M S7 ), to produce an output current (M S1 ). robustly by slowing down those that spike too fast and speeding up those that fire too slowly [12]. To remedy the deficiency in existing log-domain silicon synapse designs, we developed a new silicon synapse by adding a reversal-potential subcircuit to our previous de- sign [6]. In this paper, we present the synapse’s design and test results (Section II), theoretically predict and verify its effect on the QIF neuron’s spike rate (Section III), and con- firm that the highest degree of synchrony is achieved when the synapse is shunting (Section IV). The paper concludes with a brief summary. II. SYNAPSE CIRCUIT The effect a population of synapses with total conductance g syn and a common reversal potential e rev has on the neuron’s membrane potential v m is described by τ m ˙ v m = -v m + g syn (e rev - v m ) (1) where τ m is the membrane time-constant. The linear term, -v m , models a leakage conductance (normalized to one) with its reversal potential set to zero (voltage reference). v m is normalized by the threshold voltage and g syn is normalized by the leakage conductance. Notice that the synaptic input consists of a current source (g syn e rev ) and a conductance to

Transcript of A Superposable Silicon Synapse with Programmable Reversal ...

A Superposable Silicon Synapse with Programmable Reversal Potential

Ben V. Benjamin1, John V. Arthur2, Peiran Gao1, Paul Merolla2, and Kwabena Boahen1

Abstract— We present a novel log-domain silicon synapse de-signed for subthreshold analog operation that emulates commonsynaptic interactions found in biology. Our circuit models thedynamic gating of ion-channel conductances by emulating theprocesses of neurotransmitter release–reuptake and receptorbinding–unbinding in a superposable fashion: Only a singlecircuit is required to model the entire population of synapses(of a given type) that a biological neuron receives. Unlikeprevious designs, which are strictly excitatory or inhibitory,our silicon synapse implements—for the first time in thelog-domain—a programmable reversal potential (i.e., drivingforce). To demonstrate our design’s scalability, we fabricatedin 180nm CMOS an array of 64K silicon neurons, eachwith four independent superposable synapse circuits occupying11.0×21.5 µm2 apiece. After verifying that these synapses havethe predicted effect on the neurons’ spike rate, we exploreda recurrent network where the synapses’ reversal potentialsare set near the neurons’ threshold, acting as shunts. Theseshunting synapses synchronized neuronal spiking more robustlythan nonshunting synapses, confirming that reversal potentialscan have important network-level implications.

I. LOG-DOMAIN NEURONS AND SYNAPSES

Neuromorphic engineering aims to emulate computationscarried out in the nervous system by mimicking neuronsand their interconnectivity in VLSI hardware [1]. Havingsucceeded in morphing visual and auditory sensory systemsinto mixed-analog-digital circuits, engineers are entering thearena of cortical modeling [2], [3], [4]; an arena in whichneuromorphic systems’ parallel operation and low energyconsumption give them distinct advantages over softwaresimulation. The neuron model of choice for large-scalecortical simulations [5], the quadratic integrate-and-fire (QIF)neuron, has been implemented successfully with log-domaincircuits [6], [7], [8], [9]. The corresponding synapse model,a conductance tied to a programmable reversal potential, ishowever yet to be fully implemented in the log-domain.

Existing log-domain conductance-based silicon synapsedesigns are either purely excitatory or purely inhibitory [6],[10], [11]. In contrast, biological synapses behave like a con-ductance that drives the membrane toward a fixed voltage—the reversal potential—that can be excitatory (much higher),inhibitory (much lower), or shunting (near the membrane’sspike threshold). Shunting synapses have been shown tosynchronize a heterogeneous population of neurons more

Supported by a NIH Director’s Pioneer Award (DPI-OD000965) and theSamsung Advanced Institute of Technology GRO Program.

1B. Benjamin is with Electrical Engineering and P. Gao and K. Boa-hen are with Bioengineering, Stanford University, Stanford CA, U.S.A.{benvb,prgao,boahen}@stanford.edu

2J. Arthur and P. Merolla were with Bioengineering, Stanford University,Stanford CA, U.S.A. {arthurjo,pameroll}@us.ibm.com

MR4

MR1

CR

MC1

MC2

CC MA1 MA2

ME5

ME4

ME3

ME1

ME2

MG1

MG2

MG3MG4

MR3

MR2

Vspk

MS1

Cm

MS7

Ilk

Ierev Vm

Fig. 1. Superposable silicon synapse, together with biasing and neuroncircuitry (gray). The cleft (MC1-2) models spike-triggered neurotransmitterrelease and reuptake: MC1 discharges CC to ground (release) and MC2charges CC back up to VDD (reuptake). The receptor (MR1-4) modelsreceptor binding and unbinding: MR1 discharges CR to a limit set byMR2 (binding) and MR3 charges it back up to VDD (unbinding). Thediffusor (MG1-4) models spatial decay: MR4’s current, mirrored by MA1-2,spreads through MG1-3 into a hexagonal grid. The reverser (ME1-5) modelsa conductance and its reversal potential: MG4 sets ME4’s & ME5’s currents(conductance) and ME3 sets how much the former’s current is scaled(reversal potential). These currents drive the neuron’s capacitor (Cm),together with a leakage current (MS7), to produce an output current (MS1).

robustly by slowing down those that spike too fast andspeeding up those that fire too slowly [12].

To remedy the deficiency in existing log-domain siliconsynapse designs, we developed a new silicon synapse byadding a reversal-potential subcircuit to our previous de-sign [6]. In this paper, we present the synapse’s design andtest results (Section II), theoretically predict and verify itseffect on the QIF neuron’s spike rate (Section III), and con-firm that the highest degree of synchrony is achieved whenthe synapse is shunting (Section IV). The paper concludeswith a brief summary.

II. SYNAPSE CIRCUIT

The effect a population of synapses with total conductancegsyn and a common reversal potential erev has on theneuron’s membrane potential vm is described by

τmvm = −vm + gsyn(erev − vm) (1)

where τm is the membrane time-constant. The linear term,−vm, models a leakage conductance (normalized to one)with its reversal potential set to zero (voltage reference). vmis normalized by the threshold voltage and gsyn is normalizedby the leakage conductance. Notice that the synaptic inputconsists of a current source (gsynerev) and a conductance to

ground (gsyn), similar to excitatory and inhibitory synapses,respectively. In the log-domain, these circuit elements arerealized by tying a transistor’s source or drain, respectively,to the silicon neuron’s membrane capacitor [6].

The dynamic gating of synaptic conductances is modeledby emulating neurotransmitter release from axonal terminalsand binding to postsynaptic receptors as was done previ-ously [14], [6]. Spikes are fed into a pulse-extender thatmodels how long neurotransmitter remains in the synapticcleft by producing trise-wide unit-amplitude pulses, prise(t)(Fig 1, cleft). These pulses feed a lowpass filter that modelsreceptor binding–unbinding by decaying at a rate, 1/τsyn,proportional to the unbinding rate (Fig 1, receptor). Thus

τsyngsyn = −gsyn + gsat min(∑i prise(t− ti), 1)

where ti are spike times and gsat is the saturation value—attained when all the synapses’ postsynaptic ion-channelsare open—each synapse is assumed to contribute equally.Overlapping pulses do not sum—they yield an elongatedunit-amplitude pulse that starts with the first and ends withthe last. Hence, gsyn = (1− exp(−triseftot))gsat in steady-state for Poisson spike trains with total rate ftot. This outputfeeds the reversal-potential subcircuit (Fig 1, reverser).

Analysis confirms that the reversal-potential subcircuitbehaves as described by Eq 1—and yields the mappingparameters needed to convert neuronal parameters into biascurrents. The membrane capacitor’s current is

CmVm = IE5 − IE4 + IS7

=αE5

αE1IG4 −

αE4αS1

αE2αE1

IE2IE1

IS1+ αS7Ilk

where In and αn are transistor Mn’s current and sizingratio, normalized by the biasing transistors’ sizing ratio (e.g.,IS7/αS7 = Ilk). IE4 was obtained by applying the translin-ear principle: (IE2/αE2)(IE1/αE1) = (IE4/αE4)(IS1/αS1).With αE1 = αE5, IE2 = IE3 = αE3Ierev , IE1 = IG4 andVm = −UT IS1/(κIS1), where UT is the thermal voltageand κ is the subthreshold slope-coefficient, we obtain

CmUTκαS7Ilk

IS1 =IG4

αS7Ilk

(αE4αS1αE3

αE2αE1Ierev − IS1

)− IS1

Setting vm = IS1/(γIlk), where γ is a normalization factor(derived in [13]), yields

pτmIlk

vm = −vm + pgsyn

IG4

Ilk

(perev

IerevIlk− vm

)(2)

with mapping parameters

perev = αE4αS1αE3/(γαE2αE1) and pgsyn = 1/αS7

Their values are determined either from the device dimen-sions or through a calibration procedure (similar to [13]); thelatter yields more accurate results. Equating Eq 1’s neuronalparameters to Eq 2’s coefficients yields

Ierev = erevIlk/perev and IG4 = gsynIlk/pgsyn

This model-circuit mapping enables us to program the biascurrents appropriately.

10ms

trise(ms)543210.5

10ms

gsat

252015105

100ms

τsyn(ms)12.5255075100125150

100ms

erev

0.175

0.15

0.125

0.1

0.075

0.05

0.025

a

c

b

d

Fig. 2. Synapse circuit’s measured waveforms. a. Increasing the rise time(trise) makes the conductance peak later—and increases its peak value(τsyn = 25ms). b. Increasing the saturation value (gsat) rescales theentire waveform (τsyn = 25ms, trise = 5ms). c. Increasing the timeconstant (τsyn) slows down the rise as well as the fall (trise = 50ms).d. Increasing the reversal potential (erev) cause’s the conductance’s effecton the membrane potential to reverse when erev = vm = 0.1 (τsyn =50ms, trise = 100ms, τm = 25ms).

The synapse circuit’s conductance and membrane potentialwaveforms varied as expected when we programmed variousvalues for its model parameters (Fig 2). Their mappingparameters were used to set MC2’s, MR2’s, MR3’s, andME3’s gate voltages through biasing transistors driven byan on-chip DAC (see Fig 1). Four sets of DACs programeach of a silicon neuron’s four superposable synapse circuitsindependently, but these biases are shared by all synapsecircuits on that chip. IG4 and IS1 were mirrored by transistors(in parallel with ME1,5 and MS1) connected to an on-chipADC through a scanner. For trise � τsyn, the conductancepeaks at gsattrise/τsyn (Fig 2a,b). For trise � τsyn, it plateausat gsat (Fig 2c). Its effect can be excitatory (erev > vm),inhibitory (erev < vm), or shunting (erev ∼ vm) (Fig 2d).

III. QIF NEURON’S CONDUCTANCE-FREQUENCY CURVE

When we drive a QIF neuron with a synaptic populationit obeys the differential equation

τmvm = −vm + v2m/2 + iin + gsyn(erev − vm) (3)

v2m/2 models positive feedback provided by sodium chan-

nels; iin is an input current (normalized by the thresholdvoltage times the leak conductance) that we set to zero. Thismodel is a 1D dynamical system with bifurcation parametergsyn (i.e., it determines the number of fixed points) (Fig 3a).

To find the the conditions under which the neuron spikes,we determine the values for gsyn at which bifurcations occur.They occur when the minimum point of the neuron’s phase

erev � 4, g � 0 1 2 34

5

62 4 6 8

vm

2

4

6

8

10v� m Τm

a

erev � 87

6

5

430 1 2 3 4 5 6

gsyn

0.5

1.0

1.5f Τm

b

Fig. 3. Conductance-driven QIF neuron’s phase (v(v)) and spike-rate(f(gsyn)) curves. a. As gsyn increases, the phase curve’s minimum pointfollows an inverted parabola (dashed line) centered at v = erev, causingthe fixed points (circles) to disappear and reappear. b. As erev increases,the spike rate reaches a higher plateau that occurs at a higher gsyn valueand the upper bifurcation point moves rightward.

curve (vmin, τmvmin) touches the x-axis. This minimumpoint is obtained by equating dvm/dvm to 0 and substitutingthe result into Eq 3

vmin = 1 + gsyn, τmvmin = gsynerev − (1 + gsyn)2/2

It touches the x-axis (i.e., τmvmin = 0) when gsyn’s value is

g∗±syn = (erev − 1)±√

(erev − 1)2 − 1 for erev > 2

For gsyn < g∗−syn, two fixed points exist: an upper unstableone and a lower stable one, at which the neuron rests. Forg∗−syn < gsyn < g∗+syn, these fixed points disappear, and theneuron spikes. For gsyn > g∗+syn, the fixed points reappear andspiking ceases. When erev < 2, τmvmin’s maximum value,erev(erev/2 − 1), is less than zero. Hence the fixed pointsnever disappear and the neuron never spikes.

To calculate the interspike interval T , we integrate Eq 3∫ T

tref

dt = τm

∫ ∞

0

1v2m/2 + gsyn(erev − vm)− vm

dvm

⇔ T − tref = τmh(gsyn)

where tref is the refractory period and

h(gsyn) =π + 2 arccot(

√2erevgsyn/(1 + gsyn)2 − 1)

(1 + gsyn)√

2erevgsyn/(1 + gsyn)2 − 1

Inverting T yields the conductance-driven spike rate

f(gsyn) = 1/(τmh(gsyn)+tref) for g∗−syn < gsyn < g∗+syn (4)

The rate rises sharply from zero as gsyn increases beyondg∗−syn, peaks when gsyn is a little less than erev−1, gsyn’s valuewhen τmvmin is maximum, and drops precipitiously to zero

0 2 4 6 8 10 12 14 16 18gsyn

0

10

20

30

40

50

60

70

80

f(sp

ikes/s

)

erev = 10

98

7

6

5

4

3

Fig. 4. Synapse circuit’s measured rate-conductance curve. An excellentmatch is obtained between theory (lines) and experiment (dots). And, asexpected, the neuron did not spike for erev = 1 or 2. The model’s parametervalues were τm = 15ms and tref = 5ms; the fitted values were 0.96τm,1.00tref , 0.96erev, and 1.00gsyn + 0.3.

when gsyn approaches g∗+syn (Fig 3b). The peak occurs earlierthan expected because the phase curve’s rightward movementmakes vm travel further and further away from zero (reset).For erev � 1, spiking starts at g∗−syn ≈ 1/(erev − 1)/2 andstops at g∗+syn ≈ 2(erev − 1). Quadratic positive-feedback isunable to overcome conductances larger than this. They shuntthe membrane potential to erev strongly enough to preventspiking—even when erev � 1—a counterintuitive result.

We compared these theoretically predicted f(gsyn) curveswith measurements made by varying MR2’s gate voltageand recording the silicon neuron’s spikes (Fig 4). MR1

was kept on continuously by inputing spikes at intervalsshorter than trise (set to 30ms), thereby pinning gsyn to gsat.The spike rate varied as expected, with lower and upperbifurcation points, steep onset and offset, and peak spike rateall closely matching the theory. These results also validatedthe calibration procedure: The fitted parameter values werewithin 4% of the programmed ones.

IV. SYNCHRONY

The f(gsyn)-curves’ extended plateau makes the neuron’sspike rate relatively independent of the amount of synapticinput, which should promote synchrony in a heterogeneouspopulation by homogenizing spike rates. Indeed, this hasbeen demonstrated in a recurrent network model of gamma-band (30-80Hz) synchronization: Coherence (normalizedpairwise cross-correlation) was highest when synapses wereshunting [12]. Shunting also rescued neurons silenced byinhibition, increasing the number of active neurons by 100%.

We confirmed that synchrony is more robust whensynapses are shunting (Fig 5). A recurrent neural networkmodel with circularly symmetric local arbors was imple-mented in a 256× 256-array of silicon neurons on a singlechip. Point-to-point connections were realized by multiplex-ing spikes using the address-event representation and arborswere realized by relaying analog currents from neuron toneuron with a programmable decay factor λ = 0.8 (Fig 1,

eerev rev=0.1 =1.0

100ms 100ms

Fig. 5. Spike rasters from a recurrent network of 65,536 silicon neurons.Synchrony improves as erev changes from inhibitory (0.1) to shunting (1.0).The rhythm’s frequency and the number of active neurons increase as well.Neurons firing faster than twice the mean rate were excluded (τm = 15ms,tref = 1ms, iin = 0.6, gsat = 40, τsyn = 10ms, τrise = 5ms).

diffusor), both as described previously [6].The model’s parameters were mapped onto the chip’s

single set of circuit biases using its silicon neurons’ andsynapses’ median mapping parameters. This approach re-sulted in a heterogenous implementation of the model whosemedian parameter values matched the specified values butwhose variance was determined by device mismatch [13].For instance, all neurons received a lognormally distributedtonic current with median iin = 0.6 and CV = 22.5%(standard deviation/mean) [13]. This degree of heterogeneityis significantly higher than the previous study’s, whose toniccurrent was normally distributed with CV = 10% [12].

We varied erev from inhibitory (0.1 to 0.5), to shunting(0.5 to 1.0), to excitatory (1.0 to 3.0) and found coherenceto be highest in the shunting region (Fig 6). For iin > 0.5, thetheory predicts that the f(gsyn) curve starts with a nonzerospike rate (at gsyn = 0) that can either decrease or increaseas gsyn increases, depending on erev. The slope is flat neargsyn = 0 when erev ≈ 1, because the f(gsyn) curve stillpeaks near gsyn = erev − 1 when iin 6= 0. Hence, weexpect the spike rates to be maximally homogenized whenerev ≈ 1, enabling the neurons to synchronize with maximalcoherence. Indeed, coherence peaked when erev was 0.9.As erev increased from 0.3 to 0.9, the rhythm’s frequencyincreased from 15Hz to 70Hz and the number of activeneurons increased from 3,789 to 9,671.1

V. SUMMARY

We presented the first log-domain silicon synapse witha programmable reversal-potential, realized with just fivetransistors. Our’s is a pure log-domain design, unlike arecent proposal, which requires a resistor [15]. In addition toreversing its effect when the membrane potential crosses thereversal potential, our superposable synapse circuit capturesa synaptic population’s dynamic behavior through its pro-grammable rise time, decay constant, and saturation value.We proved analytically that the QIF neuron’s f(gsyn) curveis nonmonotonic—unlike its f(i) curve [9], [13]—and con-firmed that silicon neurons driven by our new silicon synapse

1Only a small fraction were active because the highly excited neuronssuppressed their neighbors. The chip’s kill bits, which can be set to disableneurons, were not utilized in this study.

0.0 0.5 1.0 1.5 2.0 2.5 3.0erev

3456789

10

Act

ive

Neu

rons( ×

103)

0.02

0.04

0.06

0.08

0.10

0.12

Coh

eren

ce

Fig. 6. Coherence (squares) peaked at erev = 0.9 whereas the number ofactive neurons (discs) increased monotonically with erev.

displayed this behavior. Finally, we demonstrated that thesilicon synapse synchronizes silicon neurons most robustlywhen it is shunting, confirming that reversal potentials canhave important implications at the network-level.

ACKNOWLEDGEMENTS

The authors would like to thank Julie Dethier and PatrickYe for collecting and analyzing the synchrony data.

REFERENCES

[1] C. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison-Wesley, 1989.

[2] R. J. Vogelstein, U. Mallik, E. Culurciello, G. Cauwenberghs, andR. Etienne-Cummings, “A multichip neuromorphic system for spike-based visual information processing,” Neural Computation, vol. 19,pp. 2281–300, 2007.

[3] J. Schemmel, D. Brandderle, A. Grandbl, M. Hock, K. Meier, andS. Millner, “A wafer-scale neuromorphic hardware system for large-scale neural modeling,” in Proc. ISCAS, pp. 1947–50, 2010.

[4] T. Y. Choi, P. A. Merolla, J. V. Arthur, K. A. Boahen, and B. E. Shi,“Neuromorphic implementation of orientation hypercolumns,” IEEETrans. Circuits Syst. I, vol. 52, pp. 1049–60, 2005.

[5] E. M. Izhikevich and G. M. Edelman, “Large-scale model of mam-malian thalamocortical systems,” PNAS, vol. 105, pp. 3593–98, 2008.

[6] J. V. Arthur and K. A. Boahen, “Synchrony in silicon: The gammarhythm,” IEEE Trans. Neural Netw., vol. 18, pp. 1815–25, 2007.

[7] V. Rangan, A. Ghosh, V. Aparin, and G. Cauwenberghs, “A subthresh-old aVLSI implementation of the Izhikevich simple neuron model,” inProc. EMBS, pp. 4164–67, 2010.

[8] A. van Schaik, C. Jin, A. McEwan, and T. J. Hamilton, “A log-domainimplementation of the Izhikevich neuron model,” in Proc. ISCAS,pp. 4253–56, 2010.

[9] J. V. Arthur and K. Boahen, “Silicon-neuron design: A dynamicalsystems approach,” IEEE Trans. Circuits Syst. I, vol. 58, pp. 1034–1043, 2011.

[10] C. Bartolozzi and G. Indiveri, “Synaptic dynamics in analog VLSI,”Neural Computation, vol. 19, pp. 2581–603, 2007.

[11] R. Z. Shi and T. Horiuchi, “A summating, exponentially-decayingCMOS synapse for spiking neural systems,”, NIPS 16, S. Thrun etal., eds, pp. 1003–10, MIT Press, Cambridge MA, 2004.

[12] I. Vida, M. Bartos, and P. Jonas, “Shunting Inhibition ImprovesRobustness of Gamma Oscillations in Hippocampal Interneuron Net-works by Homogenizing Firing Rates”, Neuron, vol. 49, no. 1,pp. 107–17, 2006.

[13] P. Gao, B. V. Benjamin and K. Boahen, “Dynamical system guidedmapping of quantitative neuronal models onto neuromorphic hard-ware,” IEEE Trans. Circuits Syst. In press.

[14] A. Destexhe, Z. F. Mainen, and T. J. Sejnowski, “Synthesis of modelsfor excitable membranes, synaptic transmission and neuromodulationusing a common kinetic formalism,” J. Comp. Neuro., vol. 1, pp. 195–230, 1994.

[15] T. Yu, S. Joshi, V. Rangan, and G. Cauwenberghs, “SubthresholdMOS dynamic translinear neural and synaptic conductance,” Int.IEEE/EMBS Conf. Neural Eng., pp. 68-71, 2011.