26.2

A Standard-Cell Solution to a Ten-Cell Problem: The Development of a State-of-Charge ASIC for

Primary Lithium Batteries

Jason Pecor Program Manager, Government Services

Silicon Logic Engineering, Inc. Eau Claire, WI 54701 jason@siliconlogic.com

Abstract: Numerous solutions exist for determining and displaying battery state-of-charge information. The sharp increase in popularity of portable personal electronics in the commercial world, coupled with the migration toward highly mobile dismounted-soldier communications and weapons technology, has lead to a multitude of battery management integrated circuits (ICs) from leading vendors in the semiconductor industry. Unfortunately, very few of the ICs are targeted for implementation in primary batteries – especially batteries with the unique attributes that often characterize primary lithium batteries. As a result, finding an existing semiconductor solution for state-of-charge determination in primary lithium batteries is a challenging endeavor.

This paper presents the development process of an application-specific integrated circuit (ASIC) targeted for implementation into primary lithium batteries. Specifically, this ASIC was developed to address the need for a state-of-charge solution in the BA-5590 LiSO2 and BA-5390 LiMnO2.

Keywords: State of Charge; Battery Management; Lithium Batteries; Battery Electronics; Primary Batteries

Introduction Based on the results of a feasibility study performed in 2004, a follow-on effort began in 2005 to design and develop an ASIC for state-of-charge indication (SOCI). The primary target application for this ASIC was the BA-5590; however, requirements and constraints of other battery chemistries and form-factors were taken into account to provide a broader application space for the final device.

Early in the program, it became clear that the ASIC would need to be a mixed-signal device – integrating analog and digital circuitry on the same IC. The IC would contain a 16-bit analog-to-digital converter (ADC), analog multiplexers, and additional analog circuitry such as op-amps, comparators, and a voltage regulator. Furthermore, it would contain digital logic gates for processing all readings as well as responding to and driving external devices.

Microcontroller Architecture The original development plan called for an algorithmic implementation fixed in permanent logic gates. However, after further analysis, the decision was made to develop a device with an integrated microcontroller for algorithm implementation.

Using a microcontroller as the main digital processor allows algorithm and configuration changes without requiring changes to the device hardware. For example, the requirements for LED functionality changed very late in the 2005 development schedule; however, the LED driver function of the ASIC was able to adapt to the new light-ramp requirement. Not only was it easy to meet the modified specification, additional functionality was added to provide temperature compensation depending on selected LED component. This kind of flexible algorithmic implementation also allows the ASIC to be more easily ported to other battery chemistries.

Although the per-component cost of a microcontroller-based IC is slightly more than a standard ASIC, the advantages associated with a microcontroller offset the increase in cost by mitigating risk in the areas of circuit verification schedule and potential redesign effort. In the future, when it becomes desirable to implement micro-code algorithms in the form of logic gates, hardening the ASIC will still be an available path, and the cost benefits of a standard ASIC can be realized.

High Performance, Low Power The ASIC needs to accurately measure a very wide range of battery loads. This range can make current measurement difficult since the low end of the range is much more susceptible to electrical or system noise than the top end of the range. What this meant to the ASIC design was that an ADC with a high dynamic range was required to detect current flow and accurately count coulombs for very small loads.

To meet these requirements, a 16-bit ADC was targeted to ensure that accuracy would be maintained across the entire current range. However, finding a silicon vendor that could provide a 16-bit ADC as part of a larger mixed-

signal platform proved to be quite challenging. Most vendors only supported up to 14-bit ADC circuits on their mixed-signal offerings. Furthermore, many of the vendors that could offer a 16-bit ADC did so at the cost of current consumption, unacceptable power performance and high costs.

The ASIC vendor that was eventually chosen was specifically selected because of their expertise with very low-power device development. More importantly, they had prior experience in the development of microcontroller-based mixed-signal ASICs with an available 16-bit ADC.

Architecture Performance Testing Prior to initiating the custom ASIC design effort, an external test vehicle was developed to validate the base technology architecture for the SOCI ASIC. At that time, the vendor offered an off-the-shelf device that utilized the same analog circuitry and microcontroller architecture that would be leveraged in the final ASIC design. Building up a system using this device provided an opportunity for algorithm verification, testing of the analog circuitry accuracy and current consumption measurements.

Though cumbersome and somewhat crude, the SLE SOCI PT1 external prototype provided the perfect test bed for validating design assumptions prior to initiating the custom chip design. The following images show the PT1 prototype enclosure and the prototype PCB.

Figure 1. PT1 External SOCI Test Prototype

Figure 2. PT1 Prototype PCB

Testing with the external prototype yielded encouraging results. The 16-bit ADC provided the desired accuracy of less than 5% total error and average current consumption was measured at <50uA for normal operation. In addition, the prototype allowed verification of the algorithms that adjust coulomb count and state-of-charge based on temperature and discharge rate.

The following tables show results of current measurement, coulomb count and temperature measurement tests that were performed using the external prototype.

Table 1. PT1 Current Test vs Fluke 179 DMM

PT1 Measured Current

Fluke 179 Measured Current

% Error

0.050 0.050 0.0% 0.124 0.125 -0.8% 0.250 0.250 0.0% 0.500 0.500 0.0% 1.000 1.000 0.0% 2.007 2.000 +0.4%

Table 2. PT1 Coulomb Count Test

Elapsed Time

PT1 Coulombs

Calculated Coulombs

% Error

02:30:00 455 450 +1.1% 16:05:00 7214 7237 -0.3% 16:00:00 14371 14400 -0.2% 08:30:18 15309 15309 0.0% 03:00:00 10816 10800 +0.1% 08:00:01 57590 57602 0.0%

Table 3. PT1 Temperature Test vs Fluke 179 DMM

PT1 Measured Temp

Fluke 179 Measured Temp Deg C Error

22.6 23.5 -0.9 36.2 37.2 -1.0 51.3 52.4 -1.1 77.5 78.4 -0.9 99.3 100 -0.7 113.3 113.9 -0.6

SOCI ASIC Specifications Based upon the feasibility study findings and the results of PT1 external prototype testing, the following primary requirements list for the custom SOCI ASIC emerged:

• Mixed-signal microcontroller design • 16-bit current measuring, coulomb counting ADC • High-resolution ADC for temperature/voltage • Dedicated LED/LCD driver interface • Internal or external temperature sensor • 25uA average current – active operation • Total measurement error: < %5 • Operating temperature: -40C to +95C • Storage temperature: -50C to +125C • SMBus interface

SMBus Though not currently required for primary battery SOCI functionality, the ASIC includes a communication interface that implements a streamlined version of the SMBus protocol. SMBus was added in anticipation of potential future communication requirements. For example, this interface could be used to read state-of-charge information when the visual indicator is not visible – providing a path for future enhancement where host equipment could communicate directly with the battery to determine capacity and remaining service time.

Given that SMBus is designed for management of rechargeable batteries, many of the commands were not applicable to a primary battery. As a result, the ASIC does not support the full SMBus protocol. Instead, a small number of important parameters are provided via the SMBus interface. The SMBus implementation on the SOCI ASIC only supports three commands: Read Word, Write Word, and Read Block. The parameters available on this device through the SMBus interface are presented in the following table.

Table 4. SMBus Parameters

Parameter Command Type Size

RemainingCapacity Read Word 2 bytes

FullChargeCapacity Read Word 2 bytes

MaxCurrent Read Word 2 bytes

Temperature Read Word 2 bytes

Voltage Read Word 2 bytes

Current Read Word 2 bytes

FirmwareInfo Read Block 5 bytes

ManufactureName Read Block 12 byte

DeviceName Read Block 8 bytes

DeviceChemistry Read Block 6 bytes

ManufacturerData Read Block 6 bytes

Cut-off Voltage Read Word Write Word

2 bytes

ASIC Test Hardware A SOCI carrier PCB has been designed for the ASIC that provides the peripheral circuitry needed to meet SOCI requirements for the BA-5590 battery. The ASIC is currently being assembled and tested as a complete electronics solution using this design and a mating PCB that provides external connectivity, complete discharge device and safety circuitry.

Figure 3. SLE SOCI ASIC on SOCI Carrier PCB

Results At the time of writing this paper, engineering samples of the SOCI ASIC have been received, and preliminary testing of the device is in process. Performance results have been very good. Both ADCs appear to be very accurate and linear across a wide range of voltage and current measurements. Furthermore, current consumption measurements indicate that the analog circuitry is functioning well within the targeted specification. This means that the total chip consumption should be less than 25uA in normal operating mode.

Full environmental testing of the device has not yet been completed. However, standard characterization and testing processes by the silicon vendor have also yielded very good results for measurement accuracy and current consumption.

ASIC Improvements The current SOCI ASIC exists as a multiple-time programmable (MTP) device. This means that the microcontroller software that contains the state-of-charge determination algorithm and other functionality can be programmed into the device numerous times. However, while that flexibility provides a benefit early in the development of the complete SOCI solution, its weakness is the associated per-part cost. A better solution is to capture the final functionality for the device and produce the ASIC with a read-only memory (ROM) version of the microcontroller software.

The next step for this design is to transition the ASIC from a programmable device to a read-only solution. This change reduces ASIC fabrication and testing costs and results in overall cost reduction for SOCI solutions that incorporate this integrated circuit.

Conclusions Though the base architecture selected to implement the SOCI ASIC had a proven history of accurate low-power designs, customizing the analog circuitry to provide the required precision for the final design and silicon implementation still proved to be a challenging process. Providing the core performance requirements while minimizing power consumption and final die size was a delicate balancing act. However, the final result of this development effort was a design that meets the targeted requirements and provides an IC device that can meet primary battery SOCI needs both now and in the future.

Acknowledgements SLE would like to extend our appreciation to Dr. Terrill Atwater and U.S Army CERDEC for all of their support and assistance throughout this development effort.