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  • A RELIABLE WAFER-LEVEL CHIP SCALE

    PACKAGE (WLCSP) TECHNOLOGY

    Umesh Sharma, Ph.D., Philip Holland and Harry Gee California Micro Devices, Inc.

    Milpitas, CA, USA [email protected], [email protected], and [email protected]

    Metin Ozen, Ph.D. and Can Ozcan Ozen Engineering, Inc. Sunnyvale, CA, USA

    [email protected] and [email protected]

    ABSTRACT

    In conventional WLCSP process, after defining the under bump metal (UBM) layer, a solder ball is dropped in the UBM opening. A subsequent thermal reflow cycle melts the solder ball and cools it in a well defined shape on top of the UBM layer. One draw back of this technology is the fracture or cracking of passivation film that may occur during the solder ball reflow process. The cracks in the passivation expose the underlying semiconductor devices to the ambient environment. Such cracks result in long term reliability problems or complete failure depending on the extent of the exposure to harmful ambient.

    In this paper, we systematically analyze the problem of passivation cracking and present a WLCSP process that is resistant to cracking during solder flow and subsequent multiple reflow steps. ANSYS thermo-mechanical finite element modeling software is used to model the WLCSP structure and process flow to evaluate stress and deformation at various points across the device structure. Contour plots clearly highlight the high stress regions and pinpoint the potential failure region. The use of ANSYS software in optimizing process parameters, and predicting reliability is presented. The experimental results confirm our simulation results and we conclude by presenting an optimized process that is resistant to passivation cracking and resulting failures.

    Keywords: WLCSP, passivation cracks, re-passivation, ANSYS, simulations

    INTRODUCTION AND PROBLEM DESCRIPTION

    WLCSP is a well established IC package technology. In its simplest form, the WLCSP process technology requires an under ball metallization layer (UBM) deposited and patterned over the passivation openings on a wafer. Subsequently, a solder ball is dropped through a stencil mask on the UBM stack. The wafer is then subjected to a thermal flow process in an oven. The thermal treatment melts the solder ball and cools it in a well defined shape as shown in Fig. 1.

    The entire structure is subject to thermo-mechanical stresses during the solder melt and subsequent solidification and cool down to room temperature.

    Figure 1. WLCSP ball formation Cross sectional view

    The forces are severe enough to create cracks in the underlying passivation film. Fig. 2 shows the cracks and their propagation along the surface and in the film.

    Figure 2. Cracks in the passivation film after solder flow. The SEM on the left shows a portion of the ball structure and the two SEMs on the right highlight the cracked regions.

    Solder Ball

    UBM Stack

    Passivation

    Metal Pad

    Crack

  • These cracks left in the passivation film expose the underlying structures to the harmful ambient environment. It is quite easy for moisture and other contaminants to penetrate the device structures through the cracks leading to circuit failure. Besides environmental damage, the primary catastrophic failure is caused when the IC is assembled on the PC board using conventional SMT techniques. Standard procedures for mounting the ICs on a PC board require application of a flux and then a thermal cycle to melt the solder. It is during the flux application process, we have seen the most damage done to the IC. Figure 3 clearly highlights this problem. The flux can easily migrate through the crack and attack the metal pad or the metal wiring. Typical chemicals used in the flux are strong enough to corrode the metal and etch away selected portions of metal lines as shown in the bottom SEM in Figure 3.

    Figure 3. The flux used during PCB mounting of the IC, flows through the cracks (top) and etches away the Aluminum pad (bottom).

    The location, density, and size of the cracks in the passivation film are dependent on several critical parameters. The solder reflow temperature, the composition of the UBM material, composition of the passivation films, the vertical and horizontal geometries of the ball structure, etc., are some of the parameters that affect passivation cracking.

    In this work we embarked upon understanding the relationship between all of the above factors and the composite thermo-mechanical stress produced in the passivation film during solder reflow. The goal was to arrive at an optimum WLCSP process that would be resistant to

    crack formation. We combined theoretical simulations with experimental results on carefully designed daisy chain structures to develop the best WLCSP process. In the following paragraphs we describe our experimental methods and highlight our major findings.

    THEORETICAL ANALYSIS ANSYS SIMULATIONS

    To aid design of experiments and develop a deeper understanding of the failure mechanism, we created a finite element model of a WLCSP ball structure. Figure 4 shows a unit cell of the WLCSP structure. Finite Element Model is generated using APDL(Ansys Parametric Design Language) parametrically such that the dimensions, material properties, and loading conditions can be changed for subsequent simulations. Periodic boundary conditions are applied on the finite element model boundaries to model physics with the representative model. Material models are assumed to be linear elastic and isotropic for this analysis. Material properties used in the model are taken from the available sources in the web[1],[2]. The material names, and properties are presented in Table 1. Deposition process of different layers are carried out using the EKILL and EALIVE commands in Ansys which allow turning-off and turning-on of the active elements during simulations. This capability allows the deposition modeling of different materials at different temperatures. Reference temperature is taken as 25C for the model, but the materials are activated at the elevated deposition temperatures such that the stress free state is achieved at the time of deposition.

    Figure 4. Finite Element Model of a 0.5mm pitch WLCSP structure. Periodic boundary conditions are assumed.

    Table I. Mechanical and thermal properties of the materials used in the WLCSP structure model.

  • The finite element analysis simulates the thermal cycle during the entire process. The most relevant information is the 1st principal stress before and after the solder flow thermal cycle. Both the magnitude and location of the stress vectors are important. In the next few paragraphs, we present path plots in the passivation layer, around the edge to extract stresses along this critical path and compare results for various simulation conditions. The top view of the path location for the WLCSP structure is shown in Figure 5.

    Figure 5. Top view of the WLCSP structure. The dashed line shows the path of 1st principal stress near the edge of the passivation layer.

    Simulations were performed in several batches, varying one process parameter at a time and evaluating the impact of the variation on the final stress. An example of such a simulation is the study of the effect of gradually increasing the nitride passivation thickness. The nitride thickness was varied from 8K to 20K in steps of 2K. The results of the principal stress calculations are plotted in Fig. 6.

    Figure 6. The stress in the passivation film is shown as a function of the nitride thickness. The stress value increases in the color coded charts from blue to red.

    For all thickness values, the maximum stress values are around the region where the circular metal pad connects to the metal interconnects. For thinner nitride films, the stress is highly non-uniform ranging from very high values near the interconnect regions versus very low values further away. As the thickness increases, the average stress rises throughout the film but the peak stress actually reduces. This is an important finding as it suggests a possibility of optimizing the stress level in the passivation film by choosing the right thickness.

    Figure 7. Principal stress along the cracking path. As the path location (a) is varied, the stress increases or decreases depending on the location. Peak stress is observed at the pad connection to the metal lines. Average stress rises with film thickness but peak stress reduces with increasing thickness.

    We ran several simulations and were able to predict both qualitative and quantitative stress levels in the passivation film after completion of the WLCSP process. Results from key simulation runs are presented below in Figures. 8-11.

    Figure 8. Principal stress along the cracking path. In this experiment a dual dielectric passivation film (oxide + nitride) was chosen. The figure compares 4 different cases: 1) original 12K nitride, 2) Case-1 6K oxide + 6K nitride, 3) Case-2 8K oxide + 6K nitride, and 4) Case-3 12K oxide + 6K nitride. Clearly, both peak and average stress values can be reduced by using a dual dielectric film of oxide + nitride instead of the nitride film alone.

    X

    Y

    X

    Y

  • Figure 9. Principal stress along the cracking path. In this simulation run comparison is made between two WLCSP processes (0.4mm ball pitch vs. 0.5mm ball pitch). We observe higher peak stress for the 0.4mm ball pitch case. This suggests different optimizations for these two processes.

    Figure 10. Principal stress along the cracking path. In this simulation run, the UBM opening and the metal pad diameter are varied to study the dependence on layout rules. Comparing 3 different cases: 1) Original UBM opening = 240um + Pad size = 260um, 2) Case-1 UBM = 240um + Pad size = 290um,