1

A Passive Filter Aided Timing Recovery SchemeFaisal A. Musa, Student Member, IEEE, and Anthony Chan Carusone, Member, IEEE

Abstract— This paper presents a passive filter for the frontend of a high speed serial link receiver to aid timing recovery.The filter provides simultaneous lowpass and highpass transfercharacteristics to generate the data and its slope respectively.Slope detection is demonstrated at 10-Gb/s. As a proof of concept,the filter was used to extract a 2-GHz clock from a 2-Gb/s 2

31-1 random data sequence based on a modified minimum meansquared error (MMSE) criterion. The circuit is fabricated in a0.18 µm CMOS process and consumes 21.6 mW from a 1.8Vsupply.

Index Terms— Baud-rate timing recovery, MMSE, CMOS,passive filter.

I. INTRODUCTION

This paper introduces a high speed passive filter that aidsan external timing recovery loop by generating the slope ofan incoming random data waveform.

Typically, timing recovery (TR) is achieved by tracking theedges of the incoming random bit stream [1]. This approachrequires an extra clock phase for sampling the edges of theinput data. TR without edge sampling (also called baud-rateTR) requires only data samples and thus is more hardware-efficient than edge-sampled TR [2]. Baud-rate techniquesreported in the literature either rely on specific 4-bit patterns[2] or uncorrelated random data [3],[4]. Recently, an activefilter aided baud-rate TR scheme has ben reported that isbased on a modified minimum mean squared error (MMSE)criterion [5]. Unlike other baud-rate schemes, this schemeis not constrained by the properties of the input randomdata. However, continuous-time slope detection is the majorchallenge in implementing this scheme. Although the activefilter reported in [5] provides the slope information of theinput data and performs linear equalization as well, it suffersfrom low speed and increased power consumption. This workdemonstrates the use of a low-power passive filter that providesslope information at a higher speed for baud-rate TR.

II. MODIFIED MMSE TR

Although this scheme has been described in detail in [5],it is briefly described here for completeness. MMSE TR isbased on the following stochastic gradient update rule:

τk+1 = τk + 2µek

(

δy(kT + τk)

δτk

)

(1)

Here y(t) represents the received waveform, T the symbolperiod, τk the sampling phase for the kth received bit Rk,

The authors are with the Edward S. Rogers Sr. Department of Electri-cal and Computer Engineering, University of Toronto, CANADA. (Email:faisal@eecg.utoronto.ca, tcc@eecg.utoronto.ca.)

This work was supported by Intel Corporation, the Canadian Microelec-tronics Corporation and the Emerging Communications Technology Institueat the University of Toronto.

(a)

Slope

Data

(b)

∫

∫

Input

Slope

Data∫

Tb

Input

Input

Data

Slope

CLK

CLK

Integrate& Dump

LossyIntegrators

(c)

Fig. 1. Slope detection techniques. (a) Integrate and Dump [7]. (b) ActiveFilter [5]. (c) Passive filter comprised of RC-CR section [This work].

ek = Rk − y(kT + τk) and µ is a parameter that is chosento tradeoff acquisition time with jitter and determines howquickly τk is adjusted. Practical high speed implementationsof the LMS algorithm often use only 1-bit representations ofthe sign of the error and the slope [6]. Applying this idea toMMSE TR results in the following Sign-Sign (SSMMSE) rule[7]:

τk+1 = τk + 2µsgn(ek)sgn

(

δy(kT + τk)

δτk

)

(2)

For NRZ data, the TR equation can be simplified to excludethe error signal ek [5]:

τk+1 = τk + 2µsgn

(

y(kT + τk)δy(kT + τk)

δτk

)

(3)

The main point here is that this scheme requires a continu-ous time slope detector. Although a two-tap slope detector hasbeen reported in [8], this leads to large jitter in the recoveredclock [9].

III. HIGH SPEED SLOPE DETECTION

As shown in Fig. 1 (a) slope detection can be simplifiedby an integrate and dump circuit, which has the followinginput-output relationship [7]:

y(kT + τ) =

∫ kT+τ

(k−1)T+τ

u(t) dt (4)

where u(t) is the input and y(t) is the output. Taking thederivative on both sides,

(

δy(kT + τk)

δτk

)

= u(kT + τ)− u((k − 1)T + τ) (5)

This approach is simple and provides a low power solutionto slope detection. However, the low-pass characteristics ofintegrating front-ends make them prone to intersymbol inter-ference (ISI) thus limiting the maximum allowable data rate

2

Data

Bias

Front End Amplifier

RC-CR Filter

Ro

2C2C

R

R/2R/2 C

RC-CRFilter

Front-EndAmplifier

Data

Slope

(a)

(b)

M1

IT

L1

L2

L2

Buffer

Slope

Buffer

Buffer

Ro

RoVcm

In+

In-

L2

L1

Ro

(12 mA)

Parameter Value

Ro 50 ohms

L1 1 nH

L2 0.75 nH

C 50 fF

R 200 ohms

IT 12 mA

M120x2u0.18u

L2Vcm 1.2 V

(30 mA each)

1.8 V

Fig. 2. Passive Filter. (a) Block diagram. (b) Schematic.

for this scheme. An active filter can be utilized to provide dataand slope information simultaneously as shown in Fig. 1(b).The active filter can be designed to include linear equalizationas well [5]. Fabricated in a 0.18 µm CMOS process, the activefilter in [5] consumed 39.6mW from a 1.8V power supplyand operated upto 2.7-Gb/s. A lower power and higher speedsolution is a passive filter comprised of an RC-CR section,as shown in Fig. 1(c). Here the data is passed simultaneouslythrough a low-pass and a high-pass first order filter section.This aligns the slope signal with the data signal over a broadbandwidth.

IV. PASSIVE FILTER

Fig. 2 shows the complete schematic of the passive filter. Itconsists of a front-end amplifier, an RC-CR section and twosets of output buffers. The lowpass RC section is called the“data path” and the high pass CR section is the “slope path”.To ensure a 90 degree relative phase shift between the data andslope paths, identical elements were used in both paths. Thecut-off frequency of the passive filter is a critical parameterin the design. Decreasing the RC time constant ensures widebandwidth in the data path, but reduces the gain in the slopepath proportionately. To ensure that the bandwidth was notlimited by the passive filter, the RC time constant was chosento be 10ps. The input impedance of the filter per side as afunction of frequency is given as:

Zin =R

4+

1

4jωC(6)

Since R was set to 200 ohms, the input impedance of the filterwas 50 ohms only at high frequecncies. Therefore, in orderto provide a broadband input match to the external 50 ohmcharacteristic impedance a front-end amplifier was needed asshown in Fig. 2. Inductors L1 and L2 were used to improvethe amplifier’s bandwidth. Note that the presence of theseinductors do not effect the slope detection action of the passivefilter. This can be derived as follows:

vs2

Z2HPF Z1HPF

Z3HPF

Cp

Ro

L1

R/2

2C Cp

L2

gmvin2

vd2

Cp

L22C

R/2

vs2

vc2 Ro

L1

gmvin2

vd2

vc2

Z2LPF Z1LPF

Z3LPF

Cp

(a) (b)

Fig. 3. Small signal model of passive filter. (a) Small signal half-circuit. (b)Small signal half-circuit with RCL-CRL sections replaced by equivalent ∆sections.

109

1010

−30

−25

−20

−15

−10

−5

0

5

10

Frequency (Hz)

Mag

nitu

de (

dB)

D3 S3

S2

S1

D2 D1

Fig. 4. Data and slope path frequency responses. D1 and S1 respectivelydenote the data and slope path transfer functions without inductors L1, L2;D2 and S2 respectively denote the data and slope path transfer functionswith inductor L1 only and D3 and S3 respectively denote the data and slopepath transfer functions without both inductors L1, L2. For these simulations,gm = 20mA/V, Cp = 110fF and all other parameters were taken fromthe table in Fig. 2.

Fig. 3 (a) shows the small signal circuit of the passivefilter. Cp denotes the parasitic capacitance at the input tothe buffer. To simplify the analysis, the RCL-CRL sectionsare replaced by their equivalent ∆ network by using a Y-∆transformation (Fig. 3 (b)). The impedances in the ∆ networkcan be expressed as,

Z1LPF (jω) = Z3HPF (jω) = jω(L2 −1

2ω2C) +

L2

RC(7)

Z2LPF (jω) = Z2HPF (jω) =jω R

2 (L2 −1

2ω2C) + L2

2C

jωL2(8)

Z3LPF (jω) = Z1HPF (jω) = −ω2RC(L2 −1

2ω2C) + jωL2

(9)The gain in the data path can be expressed as:

vd

vin

(jω) = A1(jω)KL(jω) = A1(jω)Z1LPF (jω)

ZT (jω)(10)

where ZT (jω) = Z1LPF +Z3LPF + jωCpZ1LPF Z3LPF andA1(jω) is the gain from vc/2 to vin/21. The gain in the slopepath can be expressed as:

vs

vin

(s) = A1(jω)KH(jω) = A1(jω)Z3LPF (jω)

ZT (jω)(11)

1A1(jω) = −gm

Yo+2Y2LP F +(1−KL(jω))Y3LP F +(1−KH(jω))Y1LP F

3

Output

Bias

R1

M1

I1

L1 L1

R1

Parameter Value

R1 100 ohms

R2

L1 1 nH

I1 10 mA

M1 20x2u0.18u

1.8 V

50 ohms

20 mAI2

M2 40x2u0.18u

R2

M2

L1 L1

R2

1.8 V

Input

BiasI2

Fig. 5. Schematic of two-stage buffer.

Front-EndAmplifier

DataBuffers

SlopeBuffers

RC-CRFilter

Fig. 6. Die Photo of Passive Filter

Thus the ratio of the gains in the data and slope paths canbe expressed as:

vd

vs

(s) =Z1LPF

Z3LPF

=1

jωRC(12)

Eq. (12) shows that inductors L1 and L2 do not hamperthe slope detection action of the passive filter. Fig. 4 plots thetransfer functions in the data and slope paths with and withoutinductors L1 and L2. The plots reveal that inductors L1 andL2 improve the bandwidth and gain in both paths.

Output buffers were provided in both the data and slopepaths, each comprising of two inductively peaked differentialpairs (Fig. 5). The total current consumption was 72mA froma 1.8V power supply. Of this total, 12mA was consumed in thefront-end amplifier and 30mA in each of the output buffers.Excluding the output buffers, the power consumption was 21.6mW.

V. MEASUREMENT RESULTS

The passive filter was fabricated in a 0.18-µm CMOStechnology and occupied an area of 1.1 mm2. The die photois shown in Fig. 6. A network analyzer was used to measurethe frequency response (Fig. 7) of the filter on wafer. Themeasured -3dB bandwidth in the data path was 6 GHz. Inthe slope path, the magnitude of S21 increased at a rate of20dB/dec. The relative phase shift between the data and slopepaths is plotted in Fig. 8(a). The phase shift is near 90 degreesover a broad bandwidth. The input impedance of the filter isshown in Fig. 8(b). A Centellax PRBS board was connectedto the passive filter to test its functionality. Eye diagrams ofdata and slope outputs captured by an Agilent 86100B scopefor a 10-Gb/s 231-1 PRBS sequence are shown in Fig. 9. Notethat the slope output exhibits peaks aligned with transitions

100

101

-50

-40

-30

-20

-10

0

10

Frequency (GHz)

Data Path (Measured)

Slope Path (Measured)

|S21

| (d

B)

Slope Path RC Sims (tt@27C)

Data Path RC sim (tt@27C)

Data Path RC sim (ss@125C)

Slope Path RC Sims (ss@125C)

Fig. 7. Measured and simulated S21 in the data and slope paths.

0 2 4 6 8 1070

75

80

85

90

95

100

Frequency (GHz)

Rel

ativ

e A

ng

le (

deg

rees

)

(a)

100

101

50

50.5

51

51.5

52

52.5

53

53.5

54

Frequency (GHz)

Inp

ut

Imp

edan

ce, 5

0x|Z

11| (

oh

ms)

(b)

Fig. 8. Network analyzer measurements. (a) Relative angle between the dataand slope paths.(b) Input impedance of the passive filter.

Fig. 9. Data (top eye) and slope (bottom eye) outputs of passive filterat 10-Gb/s (Vertical scale (top eye)=100mV/div; Vertical scale (bottomeye)=25mV/div ; Horizontal scale=20ps/div).

4

Mixer

Loop FilterVCO

BERT

2 Gb/s

8403A

Data Data

Slope

Latch

Scope

86100B RecoveredClock (2 GHz)

Trigger

External Timing Recovery Loop

Prototypefilter I.C.

Fig. 10. Test set up for external TR loop using the passive filter.

DA

TA

SLO

PE

MIX

ER

OU

TC

LO

CK

(c)

(b)

(a)

Fig. 11. Waveforms at different points of the TR loop. (a) Data (top eye)and slope (bottom eye) outputs of passive filter at 2-Gb/s.(Vertical scale(top eye)=100mV/div; Vertical scale (bottom eye)=50mV/div ; Horizontalscale=200ps/div) (b) Mixer output corresponding to a 2-Gb/s random datasequence (Vertical scale= 50mV/div; Horizontal scale=200ps/div). (c) Recov-ered 2-GHz clock (Vertical scale= 100mV/div; Horizontal scale=200ps/div).

in the data waveform. At high speeds, capturing the data andslope signal that are precisely aligned is challenging due to themismatches in cables. To offset this issue, the data signal wascaptured first and then the same cable was connected to theslope path to capture the slope. The scope time delay settingswere kept fixed during this measurement as shown in the timedelay slots of the eye diagrams in Fig. 9.

The passive filter was combined with external componentsto demonstrate the proposed TR scheme as shown in (Fig. 10).The mixer, latch, VCO and loop filter were implemented on aseparate board using commercial components. The loop wastested with a 2-Gb/s 231-1 PRBS data pattern generated froma BERT. The data rate for this test was limited by the external

TABLE I

PERFORMANCE SUMMARY & COMPARISON TABLE

Reference Data Clock Conditions RMSRate Freq. Jitter

This work 2 Gb/s 2 GHz 231-1 PRBS; 6.1 ps(Baud-rate)

[5] 2 Gb/s 2 GHz 231-1 PRBS; 6.5 ps(Baud-rate)

[2] 5 Gb/s 1 GHz Random data; 4.8 ps(Baud-rate)

[10] 2.5 Gb/s 2.5 GHz 223-1 PRBS; 17.4 ps(Edge-sampled)

components. The mixer takes the product of the slope and datasignals, as required by Eq. (3), and the latch performs the sgnoperation. Fig. 11 shows the waveforms at different points ofthe test setup. As expected, a baud-rate timing tone is visibleat the output of the mixer. The resulting RMS clock jitter was6.1 ps. Table I summarizes the performance of the TR schemeand compares it to other published timing recovery schemes.

VI. CONCLUSION

This paper presented a passive filter that is used to gener-ate timing information from a random data waveform. Thisfilter provides simultaneous lowpass and highpass transfercharacteristics over a broad bandwitdh. The highpass transfercharacteristic is utilized to provide the slope information upto10-Gb/s. The data and slope signals can be used to recover aclock based on the modified MMSE criterion. To demonstratethe timing recovery concept, the prototype passive filter wasused with external components to recover a 2-GHz clock froma 2-Gb/s 231-1 random data sequence.

REFERENCES

[1] J. Alexander,“Clock recovery from random binary signals,” ElectronicsLetters, vol. 111, pp. 541-542, October 1975.

[2] A. Emami-Neyestanak, S. Palermo, H. Lee and M. Horowitz,“CMOSTransceiver with Baud Rate Clock Recovery for Optical Interconnects,”2004 VLSI Symposium on Circuits, pp. 410-413, 2004.

[3] V. Balan et. al,“A 4.8-6.4-Gb/s Serial Link for Backplane ApplicationsUsing Decision Feedback Equalization,” IEEE J. of Solid State Circuits,vol. 40, no. 9, pp. 1957-1967, September 2005.

[4] K. Mueller and M. Muller,“Timing Recovery in Digital SynchronousData Receivers,” IEEE Transactions on Communications, vol. COM-24,no. 5, pp. 516-531, May 1976.

[5] F. Musa and A. Chan Carusone,“A baud-rate timing recovery schemewith a dual-function analog filter,” IEEE Transactions on Circuits andSystems II: Express Briefs, vol. 53, no. 12, pp. 1393-1397, December2006.

[6] M. Le, P. Hurst and J. Keane,“An Adaptive Analog Noise-PredictiveDecision-Feedback Equalizer,” IEEE J. of Solid State Circuits, vol. 37,no. 2, pp. 105-113, February 2002.

[7] F. Musa and A. Carusone,“Clock recovery in high speed multilevel seriallinks,” in Proc. of the 2003 International Symposium on Circuits andSystems, pp. 449-452, May 2003.

[8] P. Roo, R. Spencer and P. Hurst,“A CMOS analog timing recovery circuitfor PRML detectors,” IEEE J. of Solid State Circuits, vol. 35, no. 1,pp. 56-65, January 2000.

[9] E. Lee and D. Messerschmitt, Digital Communication, 2nd ed. KluwerAcademic Publishers, Massachusetts, 1997.

[10] S. Anand and B. Razavi,“A CMOS Clock Recovery Circuit for 2.5-Gb/sNRZ Data,” IEEE J. of Solid State Circuits, vol. 36, no. 3, pp. 432-439,March 2001.