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Optik 122 (2011) 891–895

Contents lists available at ScienceDirect

Optik

journa l homepage: www.e lsev ier .de / i j leo

novel frequency encoded all optical logic gates exploiting polarizationnsesensitive four wave mixing in semiconductor optical amplifier, filteringroperty of ADD/DROP multiplexer and non-linearity of reflectiveemiconductor amplifier

ousik MukherjeeG and PG Department of Physics, B.B. College, Asansol 713303, West Bengal, India

r t i c l e i n f o

rticle history:eceived 17 October 2009

a b s t r a c t

All optical logic gates exploiting polarization independent four wave mixing in semiconductor opti-cal amplifier (SOA), filtering property of ADD/DROP multiplexer (ADM) and non-linearity in reflective

ccepted 12 May 2010

eywords:requency encodingour wave mixing

semiconductor optical amplifier (RSOA) have been proposed. The logic gates proposed are polarizationindependent which ensures hardware simplicity and greater speed. The all optical frequency encodedlogic gates NOT, OR, NOR, AND, NAND, X-OR, X-NOR are implemented which are very useful in opticalcomputing ad signal processing, cryptography, etc. The logic gates proposed have the advantages thatthere is no intensity loss dependent problem, and are polarization and temperature insensitive.

© 2010 Elsevier GmbH. All rights reserved.

ogic gatesemiconductor optical amplifier

. Introduction

All optical information processing has become a major fieldf research in the area of future communication technologies.everal all optical data processor, image processors, have been pro-osed [1–4] which has overcome the speed limitations in electronicrocessor, because photon is a very suitable information carrierompared to electron in many aspects. But it is the clear that con-entional techniques of electronics cannot be applied in optical datarocessing. To overcome this difficulty, a vast community of scien-ists and technologists has proposed different direct and indirectays to implement the all optical operations with Boolean logic

ystem. All optical logic gates are the key element of all opticalignal processing systems. Many schemes of all optical logic gatesre reported, using semiconductor devices [5–10], optical fibers11–14], or waveguides [15] and other new structures [16,17]. In

ost of the cases, to implement the logic state ‘1’, a prefixed value ofhe intensity level is required to be maintained. If not due to loss ofntensity, major problems in channel selection is created. This is dueo fact that a non-linear material sends the light (photon) passing

hrough it in different channel if the value of the intensity is varied.ecently frequency encoding technique has been proposed whichas not any intensity loss dependent problems but the use of PPLNave guide [18] makes it temperature and polarization sensitive. A

E-mail address: lipton007@indiatimes.com

030-4026/$ – see front matter © 2010 Elsevier GmbH. All rights reserved.oi:10.1016/j.ijleo.2010.05.033

relatively advantageous scheme is proposed by the author by usingdifference frequency generation and dielectric thin films [19] butis not SOA based.

Similarly the proposal based on polarization based logicimplementation [18,20,21] has some drawbacks as the state ofpolarization may alter at the reflecting or refracting points alongthe transmission or propagation path. Semiconductor opticalamplifiers (SOA) are very attractive non-linear device and easilyintegrable but most of the SOA based proposals use interferomet-ric configurations including two or more devices [6–8]. This needsaccurate control and stabilization schemes. In contrast to theseproposals one can propose a scheme which does not have the dis-advantage of intensity loss dependent problems, does not use anyinterferometric configuration, and polarization insensitive. In thiscommunication the author wish to propose an implementation ofall optical logic gates NOT, OR, AND, NOR, NAND, X-OR, X-NORin frequency encoded format exploiting polarization independentfour wave mixing in SOA, filtering property of ADD/DROP multi-plexer and non-linearity of Reflective SOA (RSOA). In frequencyencoding technique the logical state ‘0’ is represented by a fre-quency �1 (LOW) and ‘1’ by another frequency �2 (HIGH). The mainadvantage of this scheme is that, there is no intensity loss depen-

dent problem. The other advantages of this proposal are it does notuse any interferometric configuration, polarization and tempera-ture insensitive. As far as the author’s knowledge goes this type ofpolarization independent SOA based frequency encoded differentlogic gates is proposed first time in this communication.

8 tik 122 (2011) 891–895

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Fig. 2. Tunable SOA filter ADD/DROP multiplexer: the frequency channel selectedis reflected by the filter, amplified second time by the MQW section and extractedto drop port using circulator. The remaining frequency channels pass through thefilter section.

92 K. Mukherjee / Op

. Working principle

The working of the different logic gates are based on the mainhree processes, four wave mixing, filtering property of ADD/DROP

ultiplexer and non-linearity in RSOA.

.1. Four wave mixing (FWM)

Four wave mixing is a coherent non-linear process and can occurn SOA between two signals, a strong pump and a weaker probeignal. There are different mechanisms behind the generation ofour wave mixing:

(i). Modulation of the carrier density, in which the carrier –holerecombination between the conduction and valence band.

(ii). Spectral hole burning (SHB), is caused due to the creation ofhole in the inter band carrier distribution.

iii). Carrier heating which is caused by the stimulated emissionand free carrier absorption.

For efficient FWM, the polarization state of the pump and therobe signals must be the same. So some polarization control mech-nism of either probe or pump will be necessary. But in co-polarizednd orthogonal polarized dual pump schemes, the FWM is polar-zation insensitive. In the implementation of all optical logic gatesn this communication orthogonal polarized pumps scheme to gen-rate FWM will be used. In this scheme the orthogonal polarizedumps interact with the input data signal to generate a new con-

ugate signal, the power of which is also polarization independent.he scheme is shown in Fig. 1 [22,23].

.2. ADD/DROP multiplexer (ADM)

The function of ADM is to separate a particular frequency chan-el without interference from adjacent channels. This is achievedy a frequency demultiplexer by integrated tunable SOA filter as inig. 2 [23,24].

The filter can be tuned by changing injection current. The fre-uency channel selected is reflected by the filter, amplified secondime by the MQW section and extracted to drop port using cir-ulator. The remaining frequency channels pass through the filterection.

ig. 1. Generation of FWM by orthogonal polarization scheme: the main action ofhis is to generate sum frequency �1 + �2 and then the difference of this sum andhe frequency �s.

Fig. 3. Reflective SOA: a weak signal of frequency �1 can be converted to a highpower signal of a different frequency �2 by using a signal of frequency �2 fromoutside. Inside the RSOA multiple reflections occurs and the power of the weaksignal is converted to the high power signal.

2.3. Reflected semiconductor amplifier (RSOA)

It utilizes a high reflecting coating on one facet and ultra lowreflecting coating on the other facet to produce a highly versatilereflective gain medium. The basic structure is shown in Fig. 3 asused in this communication. A weak signal of frequency �1 can beconverted to a high power signal of a different frequency �2 byusing a signal of frequency �2 from outside. Inside the RSOA multi-ple reflections occurs and the power of the weak signal is convertedto the high power signal [25,26].

3. Operating principle of different logic gates

The operating mechanism of different logic gates NOT, OR, AND,NOR, NAND, X-OR, X-NOR is shown in Tables 1 and 2. Here the

frequency encoding technique i.e. the logical state ‘0’ is representedby a frequency �1 and ‘1’ by another frequency �2 is used. For NOTgate FWM is not required but to implement rest of the gates FWMis necessary.

Table 1NOT gate operation.

�in �out

�1 �2

�2 �1

Table 2Operation of different logic gates.

A B OR AND NOR NAND X-OR X-NOR

�1 (0) �1 (0) �1 (0) �1 (0) �2 (1) �2 (1) �1 (0) �2 (1)

�1 (0) �2 (1) �2 (1) �1 (0) �1 (0) �2 (1) �2 (1) �1 (0)

�2 (1) �1 (0) �2 (1) �1 (0) �1 (0) �2 (1) �2 (1) �1 (0)

�2 (1) �2 (1) �2 (1) �2 (1) �1(0) �1 (0) �1 (0) �2 (1)

K. Mukherjee / Optik 122 (2011) 891–895 893

Fig. 4. NOT gate.

Table 3Operating conditions and outputs of the NOT gate.

�in Converted frequencies Outputs of the NOT gate

�1 2�1 − �s �2 (1)

�2 2�2 − �s �1 (0)

Table 4Operating conditions and outputs of the OR gate.

�A �B Converted frequencies Outputs of the OR gate

�1 �1 2�1 − �s �1 (0)

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Table 5Operating conditions and outputs of the AND gate.

�A �B Converted frequencies Outputs of the AND gate

�1 �1 2�1 − �s �1 (0)

�1 �2 �1 + �2 − �s �1 (0)

�2 �1 �1 + �2 − �s �1 (0)

�2 �2 2�2 − �s �2 (1)

�1 �2 �1 + �2 − �s �2 (1)

�2 �1 �1 + �2 − �s �2 (1)

�2 �2 2�2 − �s �2 (1)

.1. NOT gate

The NOT gate implementation requires two ADM and two RSOAs shown in Fig. 4.

Here the inputs are either �1 or �2. When the input is opticalignal of frequency �1 (LOW), the ADM1 blocks it and reflect back,nd is dropped to RSOA1 by the circulator which convert it to anptical signal of frequency �2. So the output is �2 (HIGH). Similarlyhen the input is the optical signal of frequency �2, the ADM2 andSOA2 make it to become a signal of frequency �1. So the output isow �1 (LOW). This is nothing but the operation of a NOT gate aslear from Table 3.

.2. OR gate

For implementation of the OR gate one has to use FWM in an

OA, three ADMs, and two RSOAs. In Table 4, the inputs, the FWMonverted frequencies, and corresponding outputs are shown. Themplementation of the OR gate is shown in Fig. 5.

Fig. 5. OR gate.

Fig. 6. AND gate.

When both the inputs are �1, the converted signal of frequency2�1 − �s is blocked and reflected back by the ADM1 and is droppedby the circulator to the RSOA1 and is further converted to a signalof frequency �1 by the RSOA1 and extracted as output �1 (LOW).Similarly when any one of the two inputs are either �1 or �2, theconverted signal of frequency �1 + �2 − �s is blocked and reflectedby ADM2 and dropped by the circulator to the RSOA2. RSOA2 con-verts it to a signal of frequency �2. When both the inputs are �2,then the converted signal of frequency 2�2 − �s is blocked andreflected by ADM3 and dropped by the circulator to the RSOA2.RSOA2 converts it to a signal of frequency �2. In last three condi-tions the output are �2 (HIGH) and the rest is �1 (HIGH). So this isthe operation of an OR gate.

3.3. AND gate

For implementation of the AND gate one has to use FWM in anSOA, three ADMs, and two RSOAs. In Table 5, the inputs, the FWMconverted frequencies, and corresponding outputs are shown. Theimplementation of the AND gate is shown in Fig. 6.

When both the inputs are �1, the converted signal of frequency2�1 − �s is blocked and reflected back by the ADM1 and is droppedby the circulator to the RSOA1 and is further converted to a signalof frequency �1 by the RSOA1 and extracted as output �1 (LOW).Similarly when any one of the two inputs are either �1 or �2, theconverted signal of frequency �1 + �2 − �s is blocked and reflectedby ADM2 and dropped by the circulator to the RSOA1. RSOA1 con-verts it to a signal of frequency �1. When both the inputs are �2,then the converted signal of frequency 2�2 − �s is blocked andreflected by ADM3 and dropped by the circulator to the RSOA2.RSOA2 converts it to a signal of frequency �2 (HIGH). In first threeconditions the output are �1 (LOW) and the rest is �2 (HIGH). Sothis is the operation of an AND gate.

3.4. NOR gate

The implementation of this gate also requires FWM in an SOA,

three ADMs, and two RSOAs. In Table 6, the inputs, the FWMconverted frequencies, and corresponding outputs are shown. Theimplementation of the NOR gate is shown in Fig. 7.

When both the inputs are �1, the converted signal of frequency2�1 − �s is blocked and reflected back by the ADM1 and is dropped

894 K. Mukherjee / Optik 122 (2011) 891–895

Table 6Operating conditions and outputs of the NOR gate.

�A �B Converted frequencies Outputs of the NOR gate

�1 �1 2�1 − �s �2 (1)

�1 �2 �1 + �2 − �s �1 (0)

�2 �1 �1 + �2 − �s �1 (0)

�2 �2 2�2 − �s �1 (0)

Fig. 7. NOR gate.

Table 7Operating conditions and outputs of the NAND gate.

�A �B Converted frequencies Outputs of the NAND gate

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Table 8Operating conditions and outputs of the X-OR gate.

�A �B Converted frequencies Outputs of the X-OR gate

�1 �1 2�1 − �s �2 (1)

�1 �2 �1 + �2 − �s �2 (1)

�2 �1 �1 + �2 − �s �2 (1)

�2 �2 2�2 − �s �1 (0)

y the circulator to the RSOA1 and is further converted to a signalf frequency �2 by the RSOA1 and extracted as output �2 (HIGH).imilarly when any one of the two inputs are either �1 or �2, theonverted signal of frequency �1 + �2 − �s is blocked and reflectedy ADM2 and dropped by the circulator to the RSOA2. RSOA2 con-erts it to a signal of frequency �1. When both the inputs are �2,hen the converted signal of frequency 2�2 − �s is blocked andeflected by ADM3 and dropped by the circulator to the RSOA2.SOA2 converts it to a signal of frequency �1. In last three condi-ions the output are �1 (LOW) and the rest is �2 (HIGH). So this ishe operation of a NOR gate.

.5. NAND gate

The NAND gate is implemented by the use of FWM in an SOA,hree ADMs, and two RSOAs. In Table 7, the inputs, the FWMonverted frequencies, and corresponding outputs are shown. Themplementation of the NAND gate is shown in Fig. 8.

Fig. 8. NAND gate.

�1 �1 2�1 − �s �1 (0)

�1 �2 �1 + �2 − �s �2 (1)

�2 �1 �1 + �2 − �s �2 (1)

�2 �2 2�2 − �s �1 (0)

When both the inputs are �1, the converted signal of frequency2�1 − �s is blocked and reflected back by the ADM1 and is droppedby the circulator to the RSOA1 and is further converted to a signalof frequency �2 by the RSOA1 and extracted as output �2 (HIGH).Similarly when any one of the two inputs are either �1 or �2, theconverted signal of frequency �1 + �2 − �s is blocked and reflectedby ADM2 and dropped by the circulator to the RSOA1. RSOA1 con-verts it to a signal of frequency �2. When both the inputs are �2,then the converted signal of frequency 2�2 − �s is blocked andreflected by ADM3 and dropped by the circulator to the RSOA2.RSOA2 converts it to a signal of frequency �1 (HIGH). In first threeconditions the output are �2 (HIGH) and the rest is �1 (LOW). Sothis is the operation of an NAND gate.

3.6. X-OR gate

For implementation of the X-OR gate one has to use FWM in anSOA, three ADMs, and two RSOAs. In Table 8, the inputs, the FWMconverted frequencies, and corresponding outputs are shown. Theimplementation of the X-OR gate is shown in Fig. 9.

When both the inputs are �1, the converted signal of frequency2�1 − �s is blocked and reflected back by the ADM1 and is droppedby the circulator to the RSOA1 and is further converted to a signalof frequency �1 by the RSOA1 and extracted as output �1 (LOW).Similarly when any one of the two inputs are either �1 or �2, theconverted signal of frequency �1 + �2 − �s is blocked and reflectedby ADM3 and dropped by the circulator to the RSOA2. RSOA2 con-verts it to a signal of frequency �2 (HIGH). When both the inputsare �2, then the converted signal of frequency 2�2 − �s is blockedand reflected by ADM2 and dropped by the circulator to the RSOA1.RSOA1 converts it to a signal of frequency �1. In middle two con-ditions the output are �2 (HIGH) and rest are �1 (LOW). So this isthe operation of an X-OR gate.

3.7. X-NOR gate

For implementation of the X-OR gate one has to use FWM in an

SOA, three ADMs, and two RSOAs. In Table 9, the inputs, the FWMconverted frequencies, and corresponding outputs are shown. Theimplementation of the X-OR gate is shown in Fig. 10.

When both the inputs are �1, the converted signal of frequency2�1 − �s is blocked and reflected back by the ADM1 and is dropped

Fig. 9. X-OR gate.

K. Mukherjee / Optik 122

Table 9Operating conditions and outputs of the X-NOR gate.

�A �B Converted frequencies Outputs of the X-NOR gate

�1 �1 2�1 − �s �2 (1)

�1 �2 �1 + �2 − �s �1 (0)

�2 �1 �1 + �2 − �s �1 (0)

�2 �2 2�2 − �s �2 (1)

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y the circulator to the RSOA1 and is further converted to a signalf frequency �2 by the RSOA1 and extracted as output �2 (HIGH).imilarly when any one of the two inputs are either �1 or �2, theonverted signal of frequency �1 + �2 − �s is blocked and reflectedy ADM3 and dropped by the circulator to the RSOA2. RSOA2 con-erts it to a signal of frequency �1 (LOW). When both the inputsre �2, then the converted signal of frequency 2�2 − �s is blockednd reflected by ADM2 and dropped by the circulator to the RSOA1.SOA1 converts it to a signal of frequency �2 (HIGH). In middle twoonditions the output are �1 (LOW) and rest are �2 (HIGH). So thiss the operation of an X-NOR gate.

. Conclusions

Ultrafast all optical logic gates are proposed exploiting novel,roblem free, integrable scheme based on polarization insen-itive orthogonal pump Four Wave Mixing in Semiconductorptical Amplifier, filtering property of ADD/DROP multiplexer,nd non-linearity in Reflective Semiconductor Optical Amplifier.he polarization insensitiveness, non-interferometric configura-ion, strongly reduces the hardware complexity and the instabilitiesf the logic gates and increases the speed of operation. However thenused frequencies �1, �2 and �s are not properly utilized in thischeme. But if they are made to be utilized properly they can gener-te optical logic families like OR/NOR or AND/NAND simultaneouslyimilar to electronic logic families like ECL OR/NOR, etc, which theuthor believes to be his future communications. In the logic gatemplementation there are circulators associated with each RSOAsor proper routing of the output of the RSOAs (not shown in theig. 4 to Fig. 10) as in the Fig. 3.

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