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Transcript of A Novel Bulk Vertical Layer Thyristor Cell for DRAM ... Novel Bulk Vertical Layer Thyristor Cell for...
A Novel Bulk Vertical Layer Thyristor Cell for DRAM Applications
MemCon - October 11, 2016 - Bruce Bateman
© 2016 Kilopass Technology. All rights reserved. Kilopass Technology
Page 2
Outline
Introduction to Kilopass
VLT Thyristor Memory Cell
Validation on 55nm Testchip
Cross-point Memory Operation
Static Retention vs. DRAM Refresh
TCAD Characterization
Scaling to 10nm and beyond
© 2016 Kilopass Technology. All rights reserved.
Page 3© 2016 Kilopass Technology. All rights reserved.
Kilopass Overview
Company
Since 2001
HQ at San Jose
75 Employees
10x Growth ‘08-’16
Leader in OTPMemory
70+ Patents
Integrated by 250+ IDM or fabless companies
Over 10 billion units shipped
TSMC 10nm eFuse
New ThyristorMemory
SRAM & DRAM
1/10 Standby Power
Silicon Proven Bit-Cell
Patents Issued and
Pending
Device Physics Expertise
80 Ports down to 10nm
BiCMOS, BCD, SOI,
FD-SOI
HK, FinFET
HV, DRAM
Now Kilopass is introducing a new breakthrough technology: VLT
Page 4
Outline
Introduction to Kilopass
VLT Thyristor Memory Cell
Validation on 55nm Testchip
Cross-point Memory Operation
Static Retention vs. DRAM Refresh
TCAD Characterization
Scaling to 10nm and beyond
© 2016 Kilopass Technology. All rights reserved.
Page 5
Patented 3D Thyristor Memory Bitcell
© 2016 Kilopass Technology. All rights reserved.
CMOS logic compatible
No new material
No new thermal cycle
~ 1/10 variability
Silicon proven
Silicon matches TCAD
VERY fast (10’s of pS)
Low holding current (< 1pA)
108 between “0” & “1”
Negative temperature coefficient
10µA
1pA
10pA
100pA
1nA
10nA
100nA 1µA
Cu
rre
nt
Voltage (Anode-to-Cathode)
OFF
Negative
Resistance
ON
IHOLDVTRIG
100fA
N+
Cathode Anode
P
N
P
N
P
N
P
N
PNP
NPN
sPW
bNW
P-well/P-Sub
P+sNWsNW
Page 6© 2016 Kilopass Technology. All rights reserved.
Bipolar / Thyristor Circuit Myths
Myth – Bipolar transistors are significantly larger than CMOS transistors
• Fact: With vertical integration using conventional STI for isolation, Bipolar devices can have similar layout dimension to CMOS transistors
• Fact: VLT thyristor minimum dimensions are only limited by the min Feature-Size
Myth – Bipolar memory circuits use significantly higher operating currents than CMOS memory circuits
• Fact: When used in pre-charge/discharge operations similar to CMOS memory, operating currents are similar – determined by delta-V across capacitances, not DC current flow
• Fact: Thyristor “holding” current for “ON” cells is extremely small and thus can be lower than both 6T SRAM leakage and DRAM refresh overhead
Page 7© 2016 Kilopass Technology. All rights reserved.
1.E-16
1.E-15
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Cell
Cu
rre
nt
Cell Voltage (VAK)
VLT DRAM "typical" S-curve (TCAD)
Thyristor cell operation – the “S-curve”
“DC” Trigger VoltageVTRIG increases as
pulse width decreases
“DC” Collapse to OFF
“OFF” Curve
“ON” Curve
~60mV/decade “diode”@ 25C
Page 8© 2016 Kilopass Technology. All rights reserved.
1.E-16
1.E-15
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Cell
Cu
rre
nt
Cell Voltage (VAK)
VLT DRAM "typical" S-curve (TCAD)
Thyristor cell operation – Operating window
VHOLD_MIN VHOLD_MAX
DC operating window
IHOLD_MIN
Cell can be biased outside DC op window for “limited” time without disturbing state of cell
“limited” = 10’s-100’s nSec
Bias Un-selected cells near VHOLD_MIN for minimum retention current
“OFF” Curve
“ON” Curve
Page 9© 2016 Kilopass Technology. All rights reserved.
1.E-16
1.E-15
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Cell
Cu
rre
nt
Cell Voltage (VAK)
VLT DRAM "typical" S-curve (TCAD)
Thyristor cell operation – Read & Write operation
Write-0 above VHOLD_MAX
Write-1 below VHOLD_MIN
• VW0 > VHOLD_MAX
• Faster @ more Pos-V
• VW1 < VHOLD_MIN
• Faster @ more Neg-V
Read: above “knee” in ON-
curve to avoid steep slope of
diode curve
VHOLD_MIN VHOLD_MAX
VW0VW1
VREAD
“OFF” Curve
“ON” Curve
Page 10© 2016 Kilopass Technology. All rights reserved.
VLT Thyristor process cross-section
• Additional of N and P doping steps combined with CMOS S/D junctions forms vertical PNPN thyristor structure
• Conventional Shallow-Trench-Isolation (STI) separates vertical thyristors at minimum feature size dimensions
• Cathodes connected in row direction by buried-metal jumpers formed in bottom of column-wise trench
~F
~F
W
W
W
P+ P+ P+ N+
N- N- N-
P- P- P-
N+ N+ N+ N+
WW W W
NW
Page 11
Outline
Introduction to Kilopass
VLT Thyristor Memory Cell
Validation on 55nm Testchip
Cross-point Memory Operation
Static Retention vs. DRAM Refresh
TCAD Characterization
Scaling to 10nm and beyond
© 2016 Kilopass Technology. All rights reserved.
Page 12© 2016 Kilopass Technology. All rights reserved.
TCAD validation at 55nm – S-curve measurements
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Cu
rre
nt
(A)
VAnode (V)
SMIC 55LL SRAM TDM - Wafer 20, MOD19minV 120x155 2T Thyristor Switching Char
IA_VG=1.6V
VbNW=0V, VG=1.6V, VA=Linear Double Sweep
Silicon
TCAD
Page 13© 2016 Kilopass Technology. All rights reserved.
55nm AC Write/Read Measurements
Write ON time 5 ns
Write OFF time 100 ns
Write-
0
pulse
Write-
1
pulse
Silicon
Page 14
Outline
Introduction to Kilopass
VLT Thyristor Memory Cell
Validation on 55nm Testchip
Cross-point Memory Operation
Static Retention vs. DRAM Refresh
TCAD Characterization
Scaling to 10nm and beyond
© 2016 Kilopass Technology. All rights reserved.
Page 15© 2016 Kilopass Technology. All rights reserved.
VLT DRAM cross-point memory array
WLk
(M2)
WLj
(M2)
Wli(M2)
BLl
(M1)
BLm
(M1)
BLn
(M1)
Cathodes & Silicide/Metal-plugs
Bitlines
in M1
Wordline straps
in M2
W
W
W
P+ P+ P+ N+
N- N- N-
P- P- P-
N+ N+ N+ N+
WW W W
WL
WL
WL
BL BL BL
Page 16© 2016 Kilopass Technology. All rights reserved.
OFF ON
OFFON
OFFON
VLT thyristor cross-point in Standby
• All rows connected to
common current source
• Current source value set
at VLT cell IHOLD_MIN
times # of cells in array
• Current source will bias
wordline Standby voltage
at VBL – VHOLD_MIN
• Excess current for “OFF”
cells shifts to “ON” cells,
small change in VWL_SB
due to exponential
behavior of cell IV curve
VDDA
Vak = ~0.7v
Icell = <1e-17
Vak = ~0.7v
Icell = <1e-14Vak = ~0.7v
Icell = <1e-17
Vak = ~0.7v
Icell = <1e-14
Vak = ~0.7v
Icell = <1e-14
Vak = ~0.7v
Icell = <1e-17
BL BL
WL
WL
WL
# cells x IHOLD_MIN
VWL_SB
VDDA
VDDA – ~0.7v
Page 17© 2016 Kilopass Technology. All rights reserved.
OFF ON
OFFON
OFFON
VLT thyristor cross-point Read operation
• Full select
ON/OFF ratio > 1e10
• Full select : Half select
ON/ON ratio > 1e8
• ON cell in selected row
discharges BL
• OFF cell in selected
row leaves BL floating
high
• Leakage from ON cells
in unselected rows
insufficient to
discharge BL
VDDA VDDA float high
Vak = ~0.7v
Icell = <1e-17
Vak = ~0.7v
Icell = <1e-14Vak = ~0.7v
Icell = <1e-17
Vak = ~0.7v
Icell = <1e-14
Vak = VRD
Icell = >10uA
Vak = VRD
Icell = <1e-15
BL BL
WL
WL
WL
VWL_SB
VWL_SB
VWL_RD
VWL_SB
Page 18© 2016 Kilopass Technology. All rights reserved.
OFF ON
OFF
OFFON
VLT thyristor cross-point Write-0 operation
• Full select
ON/OFF ratio > 1e10
• Full select : Half select
ON/ON ratio > 1e8
• OFFON cell in
selected row
discharges BL after
trigger
Off->On
VDDA
Vak = ~0.7v
Icell = <1e-17
Vak = ~0.7v
Icell = <1e-14Vak = ~0.0v
Icell = <1e-17
Vak = ~0.0v
Icell = <1e-17
Vak = VW0
Icell = >10uA
Vak = ~0.7v
Icell = <1e-14
BL BL
WL
WL
WL
VWL_SB
VWL_SB
VWL_W0
VWL_SB
VNSEL
VDDA
Page 19© 2016 Kilopass Technology. All rights reserved.
OFF ON
OFFOn->Off
OFFON
VLT thyristor cross-point Write-1 operation
• Full select
ON/OFF ratio > 1e10
• Full select : Half select
ON/ON ratio > 1e8
• Cell in selected row/col
sees 0v or negative
voltage for VW1
Vak = <0.7v
Icell = <1e-17
Vak = <0.7v
Icell = <1e-15Vak = ~0.7v
Icell = <1e-17
Vak = ~0.7v
Icell = <1e-14
Vak = VW1
Icell = >10uA
Vak = <0.7v
Icell = <1e-15
BL BL
WL
WL
WL
VWL_SB
VWL_SB
VWL_W1
VWL_SB
VBL_W1
VDDA VDDA
Page 20
Outline
Introduction to Kilopass
VLT Thyristor Memory Cell
Validation on 55nm Testchip
Cross-point Memory Operation
Static Retention vs. DRAM Refresh
TCAD Characterization
Scaling to 10nm and beyond
© 2016 Kilopass Technology. All rights reserved.
Page 21© 2016 Kilopass Technology. All rights reserved.
VLT vs. DRAM Retention Current
8Gb DDR4 DRAM
IDD6N = 22mA (85C self-refresh)
IDD8 = 10mA (Max power-down)
Array refresh overhead ~12mA
= 1.4pA per bit
VLT cell current at Minimum data
holding voltage < 10fA
VLT Cell in Standby
Vhold_min
(85C)
Vhold_min
(27C)
Vhold_min
(-40C)
DRAM Self-refresh
VLT Retention
Page 22
Outline
Introduction to Kilopass
VLT Thyristor Memory Cell
Validation on 55nm Testchip
Cross-point Memory Operation
Static Retention vs. DRAM Refresh
TCAD Characterization
Scaling to 10nm and beyond
© 2016 Kilopass Technology. All rights reserved.
Page 23© 2016 Kilopass Technology. All rights reserved.
Approximate schematic for TCAD string simulation
bNW
“K”
W
Plug
BL0
“A”
BL0
PWL
bNW
“K”
W
Plug
BL1
“A”
BL1
PWL
bNW
N
W
Plug
BL2
“A”
BL2
PWL
bNW
N
W
Plug
BL3
“A”
BL3
PWL
bNW
N
W
Plug
BL4
“A”
BL4
PWL
bNW
N
W
Plug
BL5
“A”
BL5
PWL
bNW
N
W
Plug
BL6
“A”
BL6
PWL
bNW
N
W
Plug
BL7
“A”
BL7
PWL
WL
PWL
PWL
Res
Simulation includes effects of lateral resistance thru bNW of cathode “K” and W-plugs between cathodes• VK of cells to left see IR drop from “ON” current of cells to the right
Resistors on BL anodes “A” emulate impedance of external BL write driver
Page 24© 2016 Kilopass Technology. All rights reserved.
TCAD String Simulation
• 8-cell string with one-sided buried Wordline pickup
– Write-0/write-1/retention sims including the effect of parasitics & neighbor cell interference
– Simulated operations: w55 - 14ns-21ns, Retention at 0.55V from 21ns to 100s
End of 7ns checkerboard write After 51 seconds of retention
on off on off on off on off on off on off on off on off
Page 25© 2016 Kilopass Technology. All rights reserved.
VTRIG vs. Process Variability
Worst-case fixed corner approach to study doping variability
• bNW, sNW & sPW doping concentration independently varied by ±3-sigma, P+ variation negligible
• Write-0 trigger time is exponential function of VTRIGmeasure tWRITE-0 delay response to process
0.68ns – 4.74ns range across extreme corners
• Using exponential conversion, this corresponds to <100mV variation in VTRIG
Corner # DOE 23 bNW Peak sNW Peak sPW Peak Trigger time (@27C)
0 0 0 0 Nominal Nominal Nominal 1.320ns
1 + + + +3 sigma +3 sigma +3 sigma 0.884ns
2 + - - +3 sigma -3 sigma -3 sigma 2.040ns
3 - - + -3 sigma -3 sigma +3 sigma 4.740ns
4 - + - -3 sigma +3 sigma -3 sigma 0.772ns
5 + + - +3 sigma +3 sigma -3 sigma 0.683ns
6 + - + +3 sigma -3 sigma +3 sigma 4.490ns
7 - - - -3 sigma -3 sigma -3 sigma 2.330ns
8 - + + -3 sigma +3 sigma +3 sigma 0,989ns
Page 26© 2016 Kilopass Technology. All rights reserved.
VTRIG vs. Process Variability – Monte Carlo comparison
Worst-case fixed corner approach to study doping variability
• bNW, sNW & sPW doping concentration independently varied by ±3-sigma, P+ variation negligible
• Write-0 trigger time is exponential function of VTRIGmeasure tWRITE-0 delay response to process
• 0.68ns – 4.74ns range across extreme corners
• Fixed corner results covers +6-sigma tail of 2048 Monte Carlo simulation of sNW/sPW/bNW space
Monte Carlo Simulations of Cell Write-0 Time
Mean=1.35 Median=1.25 Min=0.50 Max=4.35 Stdev=0.50
Expected Normal
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4
Write-0 Time (ns@27C)
0
50
100
150
200
250
300
350
400
450
Fre
qu
en
cy (
#)
Page 27© 2016 Kilopass Technology. All rights reserved.
Retention VHOLD vs. Process Variability
Worst-case fixed corner approach to study doping variability
• bNW, sNW & sPW doping concentration independently varied by ±3-sigma, P+ variation negligible
• VHOLD measured at fixed holding current of 1pA thru “ON” cell
570mV – 600mV range across extreme corners
Corner # DOE 23 bNW Peak sNW Peak sPW Peak VHOLD (@ 1pA)
0 0 0 0 Nominal Nominal Nominal 591mV
1 + + + +3 sigma +3 sigma +3 sigma 590mV
2 + - - +3 sigma -3 sigma -3 sigma 580mV
3 - - + -3 sigma -3 sigma +3 sigma 600mV
4 - + - -3 sigma +3 sigma -3 sigma 582mV
5 + + - +3 sigma +3 sigma -3 sigma 569mV
6 + - + +3 sigma -3 sigma +3 sigma 593mV
7 - - - -3 sigma -3 sigma -3 sigma 592mV
8 - + + -3 sigma +3 sigma +3 sigma 598mV
Page 28© 2016 Kilopass Technology. All rights reserved.
VREAD vs. Process Variability
Worst-case fixed corner approach to study doping variability
• bNW, sNW & sPW doping concentration independently varied by ±3-sigma, P+ variation negligible
• VREAD measured at a fixed 5uA read current thru “ON” cell
1.02v – 1.04v (20mV) range across extreme corners
• With 80mV/decade slope for “ON” cell IV curve, this corresponds to an IREAD variation of 2.5uA across process corners
Corner # DOE 23 bNW Peak sNW Peak sPW Peak VREAD (@ 5uA)
0 0 0 0 Nominal Nominal Nominal 1.034
1 + + + +3 sigma +3 sigma +3 sigma 1.033
2 + - - +3 sigma -3 sigma -3 sigma 1.029
3 - - + -3 sigma -3 sigma +3 sigma 1.036
4 - + - -3 sigma +3 sigma -3 sigma 1.026
5 + + - +3 sigma +3 sigma -3 sigma 1.019
6 + - + +3 sigma -3 sigma +3 sigma 1.032
7 - - - -3 sigma -3 sigma -3 sigma 1.036
8 - + + -3 sigma +3 sigma +3 sigma 1.038
Page 29
Outline
Introduction to Kilopass
VLT Thyristor Memory Cell
Validation on 55nm Testchip
Cross-point Memory Operation
Static Retention vs. DRAM Refresh
TCAD Characterization
Scaling to 10nm and beyond
© 2016 Kilopass Technology. All rights reserved.
Page 30© 2016 Kilopass Technology. All rights reserved.
VLT DRAM Cell – Scaling Roadmap
The VLT Cell can be well scaled to 10nm and beyond
From 20nm to 1x/1y/1z, cell area scales ~50% for each litho generation• Cell area limited by active half-pitch
0.0000
0.0005
0.0010
0.0015
0.0020
0.0025
0.0030
101520
Un
it C
ell
Are
a (
um
^2)
Litho Node (nm)
Kilopass VLT DRAM Cell
Page 31© 2016 Kilopass Technology. All rights reserved.
VLT DRAM Cell – Scaling Roadmap
Silicon trench patterning and isolation are a critical module in baseline cell design• Trench isolations formed by orthogonal crossing of line-shaped patterns
• Trenches in WL direction are uniform stripe patterns
• Trenches in BL direction for buried Silicide/Metal plugs result in rectangular holes at WL intersections
0
5
10
15
20
25
30
35
40
101520
Tre
nc
h A
sp
ec
t R
ati
o
Litho Node (nm)
Kilopass Thyristor DRAM Cell
DPT STI Holes w/ Buried Metal
DPT Parallel STI Lines Separating WLs
Page 32
Summary
VLT functions well as “static” high density memory cell
• Good DC and AC operating window with low retention current
• Near 4F2 cell size in cross-point array implementation
Cell functionality and TCAD calibration validated in 55nm Testchip
Thorough TCAD Characterization show excellent manufacturing window
Scalable down to and below 10nm
© 2016 Kilopass Technology. All rights reserved.
Page 33
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© 2015 Kilopass Technology. All rights reserved.
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System bugs found by software team or customer. Bus/fabric
bandwidth is less than predicted bus bridge hangs under stress.
Access by multiple IPs reveals address decode bug.NVM IP. Boundless Freedom to Embed.
Thank you for attending Kilopass 2016 MemCon presentation.
We look forward to partnering with you in future endeavors.
Contact Kilopass for more Information:
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