A New Static Test of a DAC with a Built-in Structure

Incheol Kim, Jaewon Jang, HyeonUk Son and Sungho Kang Dept. of Electrical and Electronic Engineering

Yonsei University Seoul, Korea

{kich8718, jaera82, chaos302}@soc.yonseLac.kr and shkang@yonseLac.kr

Abstract- A new BIST(Built-In Self-Test) scheme to test static parameters of a DAC(Digital-to-Analog Converter) is proposed in this paper. The proposed BIST employs a ramp generator

and two voltage references to calculate static parameters of a DAC such as offset, gain, INL(Integral Non-Linearity) and DNL(Differential Non-Linearity). The optimization of calculating static parameters and the element sharing can

reduce the BIST circuitry. The simulation results which validate our method are able to detect the linearity errors with the simple hardware architecture.

I. INTRODUCTION

Data converters such as ADCs(Analog-to-Digital Converter) and DACs are essential modules in most mixed­signal SoCs because they provide the interface between analog and digital systems. Their performance impacts on the overall system, therefore verifying their reliability is very important[1]. However, testing them has become a difficult work because deeply embedded IPs in a single chip have poor observability and controllability. A BIST approach has risen as a solution to enhance them. A BIST provides high quality and low cost testing since it can increase testability and provide in-field verification.

To test ADCs and/or DACs, it is common to measure both static and dynamic parameters. However, in production test, testing strategy is determined by the end use of the ADC and/or DAC[2]. In this paper, we focus on a static test of a DAC in BIST environments because a dynamic test requires a microprocessor or a processing unit which is not suitable for BIST structure. In a static test, static parameters such as offset, gain, INL and DNL errors are calculated.

Several BIST methods have been proposed to test static parameters of a DAC[3-7]. In [3], a linearity test method is proposed using DDEM(Deterministic Dynamic Element Matching) ADC with dithering. This method can test high resolution high speed DAC, however it is hard to implement a BIST structure because too many resistors and switches are required. [4] proposes a BIST structure with a calibration circuit. The accuracy of the BIST is enhanced due to the calibration circuit, but this method requires some complex modules such as an ALU(Arithmetic Logic Unit), a charge

pump and a Schmitt trigger. For this reason, this method has a limit on application. [5] performs a static test using various reference voltages. The BIST compares the voltages between the output of the DAC and the selected voltage from an analog MUX. This method is easy to implement but requires too many voltage references. [6] tests static parameters with the reduced number of voltage references, but needs many control signals and the calculation of INL requires a heavy hardware overhead. [7] can test both ADC and DAC using a ramp signal. This method also requires a complex module such as code/index memory, and the hardware structure for the calculation of static parameters is not provided.

In this paper, a new static BIST method to test a DAC in a simple way is proposed. Static parameters to be tested are introduced in Section II, and the structure of the proposed BIST is explained in Section III. In Section IV, the simulation results are shown and Section V concludes the paper.

II. STATIC PARAMETERS

As mentioned above, a static test calculates offset, gain, INL and DNL. For each parameter, BIST determines pass or fail according to the output of the DAC. Generally, it is assumed that the acceptable range of the error of the DAC output is ±1I 2 LSB. It means, if the difference between the actual DAC output and the ideal expected output is larger than + 112 LSB or less than -112 LSB, the DAC is faulty.

Offset is an error at test start. When the test input of the DAC is all Os, the output voltage is expected to be OV but it may not in actual case. The output must be in the range of -112 LSB � + 112 LSB to pass the offset test. (l) presents the acceptable range of offset test.

1 1 - 2LSB ::;; V real (0) ::;; + 2LSB (1)

Gain means an error of the slope in the transfer function. It can be measured with the last input from incremental digital codes. For example, when a 3-bit DAC is tested, the last input should be '111' and the expected output voltage is 7 LSB, then the actual output should be in the range of + 13/2 LSB �

978-1-61284-857-0/11/$26.00 ©2011 IEEE

+ 15/2 LSB. (2) presents the acceptable range of the gain test for testing an N-bit DAC.

lNL is a linearity error between ideal and actual transfer functions. In Fig. I, the ideal and actual DAC outputs are illustrated. For each digital input code, the difference between the ideal and actual outputs must be in the acceptable range to pass the lNL test. DNL is also a linearity error. In Fig. 2, the actual DAC outputs and the difference between consecutive outputs are illustrated. The outputs are expected to be 1 LSB apart however the actual distances are far or closer than I LSB. The difference between the actual distance and 1 LSB must be in the acceptable range to pass the DNL test.

DNL: + 1.. LSB S; Vreal (i) - Vreal (i -I) S; + 2. LSB (3) 2 2

1 1 - "2LSB ::; Vrea1 (0)::; + "2LSB - offset

+ +LSB ::; Vreal (I)::; + fLSB

INL: + fLSB ::; Vrea1 (2)::; + fLSB (4)

Equations for these four static parameters are shown above, in (3) and (4). i means the ith digital input from the entire 2N

inputs. As they show, the offset and gain test can be included in the lNL test. In addition, the equations for the lNL test can be merged into one equation, such as (5), because VideaAi) = i LSB.

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Figure I. The INL test

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Figure 2. The DNL test

As shown in (5), the INL test requires two voltage references of -112 LSB and + 112 LSB to implement while the DNL test needs +112 LSB and +3/2 LSB. However, if the equation is modified such as (6), the voltage references can be shared in the lNL and DNL tests.

+ � LSB S; Videal (i + 1) - Vreal (i) :5: + � LSB (6)

With (3) and (6), therefore, all of the static tests can be performed with only two voltage references - + 112 LSB and +3/2 LSB. These optimization processes enables the proposed BIST to reduce the required resources.

III. PROPOSED METHOD

The proposed DAC BIST is implemented using two equations, as mentioned in Section II. In this section, the INL and DNL test methods are introduced individually and then the combined structure with resources sharing is proposed.

A. The INL Test The lNL test is inducted from (6) and adopts a ramp signal

generator to acquire faulty-free voltages, �deali). The output of the ramp generator is 1 LSB shifted because the proposed method requires �deali+ 1) instead of Videali) for Vreali) as shown in (6). A new ramp signal which is moved 1 LSB from the original ideal line is presented in Fig. 3.

In Fig. 1, the difference between the actual and ideal outputs should be in the range of -112 LSB - + 112 LSB. On the other hand, the shifted ramp and the actual outputs must be in +112 LSB - +3/2 LSB, as shown in Fig. 3. This range is the same as the one of the DNL testing, therefore the required number of voltage references can be reduced. Fig. 4 presents the circuit to achieve the lNL test.

1 LSB shifted ramp

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Digital e(){/e.'-

Figure 3. The shifted ramp signal for the INL test

3K12 LSB

Kl2 LSB

Figure 4. The circuit for the INL test

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T T T T T T T Sample-all d-fl old

Figure 5. Sample-and-hold timing

As mentioned above, the INL test is perfonned with comparison of the outputs of the DAC and the ramp generator. The voltage differences between the DAC outputs and the ramp generator are K times amplified by the amplifier and compared with two voltage references. The references are now +K/2 LSB and +3K/2 LSB because �deali+l) - VrealO is amplified as K times. These test processes are applied to the DNL test in common.

In the meantime, �deali+ 1) is continuously increasing and VOU1 also changes while VrealO does not change during one cycle. For this reason, Vout becomes like sawtooth shape, as illustrated in Fig. 5. To test INL, the voltage differences at the moment when VrealO increases are required, and they are illustrated in Fig. 5 with the circles. For this reason, the outputs of the comparators are sampled when the DAC output is changed. Then, the Vcompl and Vcomp2 signals are monitored for pass/fail decision.

B. The DNL Test Fig. 6 shows the circuit for the DNL test. During the DNL

test, <1>1 and <1>2 perfonns cross switching to hold the previous DAC output and make 112 cycle delay. Then, the voltage differences between the consecutive DAC outputs are calculated. The operation of switches and the voltages of DAC output and capacitors are described in Table I.

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B(o--------,-----Figure 6. The circuit for the DNL test

TABLE I. THE OPERA nON DURING THE DNL TEST

DAC V(O) V(l) V(2) V(3) ...

fIJI close open close open close open close ...

C1 V(O) V(O) V(l) V(l) V(2) V(2) V(3) ...

flJ2 open close open close open close open ...

C2 - V(J) V(l) V(2) V(2) V(3) V(3) ...

Normal mode input Normal mode output

Figure 7. The proposed BIST structure

The DNL testing circuit also has two outputs, Vcompl and Vcomp2, as in the INL testing circuit. However, the results of the DNL test are valid only first half of each cycle as Table I shows 112 cycle delay. In the second half, VrealO is charged into C1 and the calculation of the voltage difference of consecutive outputs does not happen. Therefore, the DNL testing circuit also has S/H circuits. The outputs of the comparators are sampled when the DAC output is changed, as in the INL test.

C. Combined Structure Fig. 7 shows the whole structure of the proposed DAC

BIST. The amplifier, comparators and voltage references are used in common for both INL and DNL tests. Therefore, the elements can be shared in the combined structure.

The counter, which provides test inputs, is I-bit larger than the DAC to test both the INL and DNL test. The INL test is perfonned from '0000 ... 00' to '0111...11' , and the DNL test is executed from '1000 ... 00' to '1111...11'. The highest I-bit presents the INLIDNL test mode and is used for generating control signals. During the INL test, <1>1 and <1>3 are always closed and <1>2 is always opened. On the other hand, during the DNL test, <1>1 and <1>2 are opened and closed according to the phases and <1>3 is always opened. The target DAC is fault-free if Vcompl < 0 and Vcomp2 < 0 during the whole test.

IV. SIMULATION RESULTS

In order to validate the proposed BIST, a 6-bit current steering DAC is simulated. For a high precision linear ramp, the design method in [8] is adopted. The shift of the ramp signal is achieved by modifying the start voltage of the ramp. The target DAC operates at 4 MHz speed and the output range is from -I V to + I V. The output has 26 levels and therefore I LSB = 2V / 64 = 0.03125V. The amplifier multiplies the voltage differences 16 times so that the voltage references are 0.75V and 0.25V. To make the gain more accurate, the amplifier is divided and operated according to the output range of the DAC. A 7-bit counter is adopted as a test input generator and the acceptable range is assumed as ± 112 LSB. The proposed BIST was simulated using HSPICE and the Vcompl and Vcomp2 signals were observed. We made variance at the current sources in the DAC as faults.

Fig. 8 shows the wavefonns of the ramp signal, DAC output, VOUI> Vcompl and Vcomp2 during the INL test. Vcompl and Vcomp2 are flattened after sample-and-hold, and monitored if

they go over OV. In Fig. 8, Vcomp2 shows the existence of a fault with Vcomp2> OV.

Figure 8. The simulation results of the INL test

Fig. 9 shows the waveforms of the previous and present DAC output, VOUl' VcompJ and Vcomp2 during the DNL test. To reduce the clock-feedtbrough effect due to repetitive closing and opening switches, we adopted a method in [9] for better performance. In Fig. 9, Vout is only valid in fIrst half of each cycle because of cross switching, as shown in Table 1. VcompJ and Vcomp2 are also sampled in the DNL test, and Vcomp2 reveals the fault with Vcomp2> OV.

The proposed BIST can detect static errors by monitoring VcompJ and Vcomp2. If a test requires changing the acceptable range, the modifIcation can easily be performed by changing the reference voltages. The strongest point of the proposed method is its simplicity. The number of voltage references, control signals, and the area overhead are greatly reduced. Table 2 shows a summarized comparison of DAC BIST methods.

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TABLE II. THE COMPARISON OF DAC BIST METHODS

Hardware overhead # of voltage # of control references signals

H. Xing's Very high Medium Very high

method[3] (many resistors, many switches, (4 unit) (for many

�ither Df A converter, decoder, etc switches) G. Chen's Very high Medium High method[4]

(ALU, charge pump, Schmitt (4 unit) (for complex trigger, integrator, etc) modules)

K. Arabi's Very low Very high High method[5] (AMUX, amp, counter, etc) (at least 7 unit) (for AMUX) 1. Tsai's Low Medium High

methodf61 (amp, counter, ramp generator) (4 unit) (for many amps) 1. Huang's

High Minimum High (amp, counter, ramp generator, method[7] memory) (0 unit) (for memory)

Proposed Low Low Low (amp, counter, ramp generator, method SIH) (2 unit) (3 switches)

V. CONCLUSIONS

This paper presents a new BIST method for testing static parameters of a DAC. Static parameters to be tested are reduced with the optimization process and the number of reference voltages can be reduced with the simple modifIcation of the ramp generator. Furthermore, the hardware resources are shared in the INL and DNL tests. Compared with the conventional method, the proposed method requires a few control signals and a simple circuitry to be easily applied as a built-in structure. The experimental results show that the proposed BIST can detect static faults with reduced number of voltage references and elements.

REFERENCES

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[2] M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, 2001, pp. 403.

[3] H. Xing, D. Chen and R. Geiger, "On-Chip At-Speed Linearity Testing of High-resolution High-Speed DACs Using DDEM ADCs with Dithering," Proceedings of IEEE International Conference on ElectrolInformation Technology, pp. 117- 122, May 2008.

[4] G. Chen, C. Lee and 1. Chen, "A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC," Proceedings of Asian Test Symposium, pp. 58-61, Nov 2004.

[5] K. Arabi, B. Kaminska and M. Sawan, "On Chip Testing Data Converters Using Static Parameters," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, pp. 409-419, Sep 1998.

[6] 1. Tsai, M. Hsiao and T. Chang, "An Embedded Built-In-Self-Test Approach for Digital-to-Analog Converters," Proceedings of Asian Test Symposium, pp. 423-428, Nov 2001.

[7] 1. Huang, C. Ong and K. Cheng, "A BIST Scheme for On-Chip ADC and DAC Testing," Proceedings of Design, Automation and Test in Europe, pp. 216-220, Mar 2000.

[8] W. Lee, Y. Liao, 1. Hsu, Y. Hwang and 1. Chen, "A High Precision Ramp Generator for Low Cost ADC Test", Proceedings of 9th IEEE. International Conference on Solid State and Integrated Circuit Technology, pp. 2103-2106, Oct. 2008.

[9] K. Watanabe and S. Ogawa, "Clock-feedthrough Compensated Sample/Hold Circuits," Electronics Letters, vol. 24, no. 19, pp. 1226-1228, Sep. 1998.