A New Frontier: CMOS Terahertz Signal Generation...

Ehsan Afshari

(http://unic.ece.cornell.edu)

April 2012

Cornell University

A New Frontier: CMOS Terahertz Signal

Generation and Amplification

Acknowledgement

• The people who actually make it happen! • Funding Agencies: ONR, DARPA, FCRP, and NSF.

Other Projects

• Low phase noise oscillators:

– Dual mode,

– Quadrature.

• Wideband low phase noise VCO:

– 2.6GHz – 5.8GHz that satisfies ALL cellular specifications

• Low power, high speed ADC

– 8GS/sec, 4b with 32mW

– 1.2GS/sec, 4b with 2mW

• Gain close to fmax of transistor

– A 107 GHz amplifier on standard 130nm CMOS

Cc

Cc

LM

CLC

Gmc

Gmc

-Gm

Gmc

Gmc

-Gm

Outline

• Motivation

• THz Signal Generation – High Power CMOS Source

– A Tunable CMOS Source

– CMOS Frequency Multipliers

– GaN Implementations

– Sharp Pulse Generation in CMOS

• THz Signal Amplification – Around 300GHz

– 500GHz and Above

• THz Spectroscopy in CMOS

• THz Imaging Systems

• Imaging (e.g., detection of concealed weapon, cancer diagnosis, and semiconductor wafer inspection )

• Compact range radars

• High data rate communication (e.g.,100 Gbps)

High power is needed for these applications

Application of THz Systems

Fundamental Challenges: • Transistors offer no power gain above fmax • Limited power efficiency of devices • Limited break down voltage • Quality factor of passives is low

High power signal generation is the main challenge in realizing CMOS THz systems.

Challenge

Electronic Source progress Optical Source

progress

Solid-State THz Sources (CW)

Electronic Source progress Optical Source

progress

Outline

• Motivation










Fundamental Limit?

• Most of the fundamental oscillators have the oscillation

frequency in the order of the half of the fmax of the

transistors. Why not higher?

• What is the maximum oscillation frequency of a circuit

topology, considering the quality factor of the passive

components?

• For a fixed frequency, what is the topology that results in

maximum output power?

Fundamental Limit • Example: IBM 130 nm CMOS process:

– fmax: simulated: 174 GHz

– fmax: measured: ~135 GHz

• Regular Cross-Coupled oscillator: – Maximum achievable frequency (simulation): 120 GHz

– This is with IDEAL inductors! VDD

Activity Condition (ΙΙ)

• Normalized real power flowing out of the device:

I2

V2

+

−

I1

V1

+

−

[ ]

=

2

1

2

1

VV

YII

))(cos()( 2112211222111

21

ϕ++∠+−+−==⇒ ∗∗− YYYYAGGAVV

PG Rm

)()(

2222

1111

YrealGYrealG

==

)(&1

2

1

2

VV

VVA ∠== ϕ

• Gm is the maximum conductance that can be placed across the transistor and maintain the oscillation.

I2

V2

+

−

I1

V1

+

−

[ ]

=

2

1

2

1

VV

YII

I1 I2

V1V2

+

−

+

−

2-port Device [Y]

Activity Condition: 0||2)||||

max( *21122211

21

>++−= YYGGVV

PR

To achieve fmax, Aopt and ϕopt should be satisfied for the device.

@ fmax 0)

||||max(

21

=VV

PR

Activity Condition (ΙΙΙ)

Maximum Activity

• Optimum gain and phase conditions for maximum generated power (maximum oscillation frequency)

22

11

GGAA opt ==)()12( *

2 11 2 YYko p t +∠−+== πϕϕ

φ opt

(deg

ree)

Aopt

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

100

110

120

130

140

150

160

170

180

Frequency (GHz)

0 25 50 75 100 125 150 175 200

Higher Frequency: Harmonics

• In order to achieve higher frequencies, we need to generate

strong harmonics

• This means we should maximize the swing at the fundamental

frequency

• It might be better to back off from the maximum possible

oscillation frequency to boost the harmonic generation

• We need to maximize “Gm”

Optimum Conditions

• Optimum phase and voltage conditions in a 65nm process • Target frequency is 450 GHz

50 100 150 200 250 300

145

150

155

160

165

170

175

Frequency (GHz)

1.0

0.8

0.6

0.4

0.2

Opt

imum

ϕ (d

egre

e)

Opt

imum

Α

+

−

+

−V2V1

Triple Push Oscillator

Ld

W

Vout

RL=50 Ω

Lg

Bia

s-te

e

ZD

ZG

+

-V1

+

-

V2

optAVVA ≅=

1

2

optVV ϕϕ ≅∠= )(

1

2

• The gate inductor helps

with both amplitude

and phase conditions:

– It resonates with Cgs to

boost the gate-source

voltage, resulting in

lower A across the

device

– It also delays the voltage

to increase the phase

shift from 120.

The Effect of Lg on Matching

• The gate inductance also helps with matching for the 3rd harmonic.

.1 .2 .5 1 2 3 4 5 10 20

ZD for Lg=13 pH

Lg=0

ZG for Lg=13 pH

Lg=0

Lg

Ld

For Lg=13 pH :ZD @ 480 GHz = 0.4-j0.5ZG @ 480 GHz =0.4+j0.4

W

ZD

ZG

Implementation

200 µm

110

µm

VoutDUT

Cascade i500-GSG Probe

WR-2.2 waveguide

Bias-tee

Power Supply

Vdd

WR-2.2 to WR-10 tapered waveguide

Power-meter(Erickson PM4)

Sensor head

DUT


WR-2.2 waveguide

Harmonic mixer

VDIWR-2.2 EHM

Diplexer

VDIIF

LO

Signal Generator

20 - 40 GHz

(Agilent E8257D)

(Agilent 8564E)

Spectrum Analyzer

µW

Bias-tee

Power Supply

Vdd

• The power and frequency test setups

Results: Spectrum

• The second harmonic is 15.5dB lower than the third harmonic • Output frequency is 482GHz

Results: Power

• Measured output power using both setups

-20

-18

-16

-14

-12

-10

-8

-6

-4

0 10 20 30 40 50 60 70

DC Power (mW)

Cal

ibra

ted

Out

put

Pow

er (d

Bm

)

-2

0

Measured with power meter

Measured with harmonic mixer and spectrum analyzer

Outline

• Motivation










Challenge: Terahertz VCO

At mm-wave and terahertz frequencies it is challenging to get high tunability with varactors due to dominance of device parasitics

Varactors are very lossy at mm-wave and are not desirable in mm-wave and terahertz signal generation

Ref. Technology Fundamental (GHz)

Output frequency (GHz)

Power (dBm) Tunability

JSSC ’06 130nm CMOS 102GHz 102 GHz -25 dBm 0.2%

ISSCC 09 32nm CMOS SOI 102GHz 102GHz N/A 4.2%

ISSCC `08 45nm CMOS 205GHz 410GHz -47 dBm -

ISSCC ’11 45nm CMOS 150GHz 300GHz -19 dBm -

JSSC ‘11 65nm CMOS 160GHz 480GHz -8 dBm -

A Simple Case: IL

• In an electrical oscillator with locking assumption Alder derives Ω that results in

• The above equations hold valid only if • There has been a considerable body of study on coupled

oscillators ever since. • This coupling mechanism has remained as a valid first order

approximation.

ωc ω0

Observation: Frequency Control

• In injection locking frequency is dictated by the external source and the phase shift is a consequence

• In a VCO we would like to dictate the phase shift and as a result tune the frequency

Vinj

Vcore

Injected at ωc

ωcω0

Locked at ωc

∆ω

ωc, φc ωc, φ

∆φ 0inj

core

ωΔω

VVQ2)φSin( ⋅=∆∆φ = φ − φc

Ring of Coupled Oscillators

Frequency is tuned by changing the phase shift of the coupling block

φ0

φ1

φ2

φ4

ψ

ψ

ψ

ψ

ψ

∆φ

Vinj

Ring of Coupled Oscillators

By selecting the coupling mode, we can combine the desired harmonic

ϕi−ϕi-1

∆ϕ

π/2

−π/2

−π/2

π/2

π

π 3π/2

−π Mode 0

Mode 1

Mode 2

Mode -1

Core 1 Core 2 Core 3 Core 4

Combined output (4ω0)

Application: Harmonic THz VCO

• Each core oscillator is optimized to generate maximum power

prior core

LdLd

LgLg

ψ

VDD

next core

Lg

Ld

Zdrain

Zout

Idrain

IoutIgate

50Ω

S11Power Combiner/ Matching

Z*out

Layout

• The chip layout in the employed 65nm CMOS process.

OUTPUT

Lg

Ld

Vcontrol

Vcontrol

Vcontrol

Vcontrol

Core

Combining CoreCore

Core

CouplingCouplin

g

CouplingCoupling

600µm

600µ

m

Measurement Results

-0.25 0 0.25 0.5 0.75 1 1.25 1.5 1.75Control Voltage (V)

280

286

292

298

304

310

316

322

Freq

uenc

y (G

Hz)

328

290GHz

320GHz

-12

-10.5

-9

-7.5

-6

-4.5

-3

0

-0.25 0 0.25 0.5 0.75 1 1.25 1.5 1.75

Out

put P

ower

(dB

m) -1.5

290GHz

320GHz

Output power

• The varactor-less core is optimized for maximum harmonic generation and power delivery to the output.

φ0

φ1

φ2

φ4

ψ

ψ

ψ

ψ

ψ

∆φ

injV

-12

-10.5

-9

-7.5

-6

-4.5

-3

0

-0.25 0 0.25 0.5 0.75 1 1.25 1.5 1.75

Out

put P

ower

(dB

m) -1.5

290GHz

320GHz

State-of-the-Art Sources Ref. This work [1] [5] [6]

Frequency (GHz)

Output Power (dBm)

Phase Noise(dBc/Hz)

DC Power (mW)

Tuning Range

Technology

290 482 324 291

-1.2 -7.9 -46 -10.9(radiated, 4 elements)

NA -76 @ 1 MHz

-78 @1MHz NA

325 61 12 74

4.5% Non-tunable 1.2% Non-tunable

65 nmBulk CMOS

65nmBulk CMOS

90nmBulk CMOS

45nmSOI CMOS

This work

320

-3.3

-78 @ 1 MHz

339

2.6%

65 nmBulk CMOS

[4]

296

-3.9

-78 @1MHz

115

4%

InP HBT (fmax>800 GHz)

[2]*

325

-3

NA

420

6.2%

130nm SiGe HBT

Area (mm2) 0.36 0.02 0.03 0.640.36 0.510.41

* [2] is a frequency multiplier, not an oscillator. We added this work to the table to compare with a frequency multiplier at a similar frequency.

Outline

• Motivation










• Effective harmonic generation and combining

Zoωo

Cd

Vout

Lg

A

RLBias-T

Ld

Cg

Cm

Lm

Basic Idea

• Effective harmonic generation and combining

Zo

Cd

Vout

Lg

A

RLBias-T

Ld

Cg

Cm

Lm-R @ ωo

Matched @ nωo

ωo• Efficient loss cancellation

Basic Idea

Theory

2Zo

ωo= 2πfo

Lg

ALg/2

φ phase shift

V1=cos(ωot)+cos(ωot - k- φ - k ) V2=cos(ωot- k)+cos(ωot - k- φ)

V2V1

I2=a1V2+a2V22=…+a2cos(2ωot - 2k- φ)+...I1=a1V1+a2V2

2=…+a2cos(2ωot - 2k- φ)+...

ggCLk °= ω

reflected

incident

reflected

incident

• The second harmonics add in phase at the output • The basic principle is independent of frequency

W

fo

Lin

Lg

A

Cg

Zin

Ld

-4

-2

0

2

4

120 125 130 135 140 145 150

Ld=68 pH

Ld=60 pH

Ld=53 pH

Ld=46 pHLd=40 pH

Input Frequency (GHz)

Rea

l(Zin

) (Ω

)

• There is a trade-off between better output matching and higher input voltage swing.

Negative Input Impedance

1)gR

CC(CωL

m

gddsgd

2d <++

Real(Zin) < 0

Implementation

• The power and frequency test setups

250 µm

200

µm

Vin

Vout

DUT


WR-3.0 waveguide

Harmonic mixer

OMLWR-3.0

Diplexer OMLIF

LO

Signal Generator

4 - 7 GHz

(Agilent E8257D)

(Agilent 8564E)

Spectrum Analyzer

Bias-tee

Power Supply

VddVGS

GGB 140-GSG Probe

WR-8.0 waveguide

VDIWR-8.0X3

Frequency Tripler

Signal Generator

36 - 47 GHz

(Agilent E8257D)

Amplifier(Centellax A4MVM3)

DUT


WR-3.0 waveguide

Bias-tee

VGS

GGB 140-GSG Probe

WR-8.0 waveguide

VDIWR-8.0X3

Frequency Tripler

Signal Generator

36 - 47 GHz

(Agilent E8257D)

Amplifier(Centellax A4MVM3) Power Supply

Vdd

WR-3.0 to WR-10 tapered waveguide

Power-meter(Erickson PM4)

Sensor head

µW

Results

220 230 240 250 260 270 280-30

-25

-20

-15

-10

-5

5

10

15

20

25

30

P out

@ 2

f 0 (d

Bm

)

Frequency (GHz)

Con

vers

ion

loss

(dB)

• In this case the input power is kept at 3dBm

Results

-8 -6 -4 -2 0 2 4 6-30

-25

-20

-15

-10

-5

10

12

14

16

18

20

P out

(dBm

) @ 24

4 G

Hz

Pin (dBm) @ 122 GHz

Conv

ersi

on lo

ss (d

B)

• The output power is not saturated • A maximum of -6.6dBm is achieved at 244GHz

Comparison

Ref. This work [3] [6]*[4]

Frequency (GHz)

Power (dBm)

Con. Loss (dB)

DC Power (mW)

Type

Technology

244 125 324180

-6.6 / 0 -1.5 -460

11.4 10 NA6.5

40 0 1292.5Traveling

waveSchottkey

diodeSuperposition

oscillatorx6 multiplier

chain

65nm CMOS 0.13µm CMOS 90nm CMOS100nm GaAs mHEMT

[5]

300

-6.4

7.4

NA

Single transistor

50nm GaAs mHEMT

[2]

115

-2.6

NA

12Injection locking

65nm CMOS

Tuning Range 22.2% 12.7% 1.2%23.5% 21.4%13.1%

* This is a CMOS oscillator, not frequency multiplier. It is cited to show the maximum output powers on CMOS.

Power Measurement Power meter/mixer Mixer MixerPower meter Power meterMixer

Outline

• Motivation










First Prototype

W

Zo

fo

Cin

Lin

CdVout

Lg

A

RLBias-T

Ld

Cg

Vin

• Simulated maximum output power: 400 - 600 mW at 500 GHz

1 THz Implementation

W

Zo

fo

Cin

Lin

CdVout

Lg

A

RLBias-T

Ld

Cg

Vin

• Simulated maximum output power: 100- 200 mW at 1 THz

Outline

• Motivation










2-D Soliton Resonance

• For a certain range of parameters, two Soliton fronts can combine to generate one.

2-D Soliton Resonance

• For a certain range of parameters, two Soliton fronts can

combine to generate one.

Fabrication in a 0.13 µm CMOS

Prototype

Chip microphotograph

t (ns)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1 2 3 4 5 6 7 8 9

0.05

0.10

0.15

0.20

0.25

0.30

x 10 GHz

0 20 40 60 80 100-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

Vol

tage

(V)

Time (ps)

InputOutput

InputOutput

0 100 150 200 250 300 350 400 450 5000

100

200

300

400

500

600

700

800

Am

plitu

de (m

V)Frequency (GHz)

900

50

Optimized Output Time-domain response Frequency-domain response

• Output pulse: 1.6psec

• 65nm CMOS • Better than 1-D line since the signal travels shorter distances.

Outline

• Motivation










Maximum Stable/Available Gain

I1 I2

V1 V2

+

−

+

−

2-port Device [Y]

50 60 70 80 90 100 110 120 130 140 1500

2

4

6

8

10

12

14

16

18

Gai

n (d

B)

Frequency (GHz)

Gs /Ga

• Maximum gains for a single device

Maximum Achievable Gain

Linear, Lossless, ReciprocalEmbedding

+

−

+

−

Vʹ2

Iʹ2Iʹ1

Vʹ1

I1 I2

V1 V2

+

−

+

−

2-port Device [Y]

)(4 21122211

21221

GGGGYY

U−

−= UUUUG 4)1(2)12(max ≈−+−=

• U is the maximum unilateral gain. • Gmax is the maximum achievable gain and is ~6 dB higher than U.

Gain Comparison

Gain simulation of a 40 µm transistor in a 130 nm CMOS

50 60 70 80 90 100 110 120 130 140 1500

2

4

6

8

10

12

14

16

18

Gai

n (d

B)

Frequency (GHz)

Gs /Ga

Gmax

U

How to Reach Gmax ?

I1 I2

V1 V2

+

−

+

−

2-port Device [Y]

2*

21*

1 IVIVP +=

))(cos()( 21122112222

1121

ϕ++∠+−+−=⇒ ∗∗ YYYYAGAGVPR

)(&1

2

1

2

VV

VVA ∠== ϕ )()12( *

2112 YYkopt +∠−+= πϕ22

2112

2||

GYYAopt

∗+=

For the same |V1| (i.e., the same input power), maximum PR (i.e., output power) results in maximum power gain of the device.

Power Amplifier: the Limit • The highest possible gain?

Vin Vout

Vdd

780 µm

460 µm

|S-p

aram

eter

| (dB

)

Frequency (GHz) 90 95 100 105 110-30

-20

-10

0

10

20

S22 S12

S11

S21

• High gain close to the fmax of the process

• Maximum gain at any frequency

• Up to 6dB higher than maximum available gain

LC

V

+

- m

d

x

l

Parametric Amplification

xlg

dtxd

−=2

2

VLCdt

Vd 12

2

−=

ClVx

↔↔

Parametric amplification at swing Duality between swing and LC resonator

(distance)

(length)

(voltage)

(capacitance)

The amplitude of the swing increases by moving the body up and down.

The change of the effective length, l, injects the energy to amplify x.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.050

100

150

200

250

300

350

Cap

acita

nce

(fF)

Voltage across varactor (V)

+ωc

ω

2ω

t

t+φ

ω

Vp1

Vs VOUT1st StageNth Stage

( )*ejπ/2 + t+φ−π/2

... C(V)l l

Vs

Vp

ω

2ω

0-30

-25

-20

-15

-10

-5

0

5

10

15

Gai

n (d

B)

Initial phase difference (radian)

bAp=0.5

bAp=0.2

bAp=0.4bAp=0.3

Section number = 20, ∆β/β = 0

-π/2 π/2-π/4 π/4

C(V)=C0(1+bV)

Accumulation-mode MOS varactor

Distributed Parametric Process

Proposed phase-matched section

Simulation result

Cc

Cc/2 Cc/2

For signal: differential mode

For pump: common mode

+Vs -Vs

Vp Vp

Vp+Vs

Vp-Vs

C(V)=C0(1+bV)C(V)

0 0.2 0.4 0.6 0.8 1-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

Out

put a

fter

20

sect

ions

(V)

Time (ns)

w/o Pumpw/ Pump (w/ Dispersion Compensation Capacitor)w/ Pump (w/o Dispersion Compensation Capacitor)

Phase Matching

Electronically Pumped Signal

In a standard 65nm CMOS: @300GHz, 10dB gain, 35GHz BW

Electrical Signal ( )

Schottky diode

ω

ωSIGNAL

ωIDLEPUMP

Differential Pump Signal( )

Vp+

Vp-

......

ωPUMP

2ωPUMP

ωPUMP

ωSIGNAL

Optically Pumped Signal

In a standard 65nm CMOS: @550GHz, 12dB gain, 20GHz BW

Electrical Signal

λ1

λ2

Optical path

Electrical path

Schottky diode

ω(λ2)

ω

ω(λ1)

ωSIGNAL

ω IDLE

PUMP

λ1=1550 λ2=1558

nm

nm

(193.41 THz)(192.42 THz)

PUMPω = 990 GHz

p-substrate

Optical waveguide

λ1 λ2n-terminal

λ2

λ1

Schottky terminal

PhysicalImplemention

I

Vin(t)

Q

t

σ

t

Vout(t)

I

Q Amplitude fluctuation

(contributed by nI)

Phase fluctuation

(contributedBy nQ)

m

Vout(t)

I

Q

Suppressed phase

fluctuation(squeezed nQ)

t

Input signal and noise

Output @ linear amplifier with a power gain of G

Output @ phase-sensitive amplifier with an in-phase gain GI and a quadrature gain GQ

(A0,0)

( GIA0,0)

Gσ

σσ

Nin(t)=nI(t)cosω +nQ(t)sinωt

Vin(t)=A0cosωt+Nin(t)

GIGQ

( GA0,0)

When GI=G, GQ<<G

Nin2(t)=nI

2(t)+nQ2(t)=2σ2

Nout2(t)=2Gσ2=GNin

2(t)

Nout2(t)=(GI+GQ)σ2

= [(GI+GQ)/2] Nin2(t)

nI2(t)=nQ

2(t)=σ2where

Noise Squeezing

Outline

• Motivation










High-frequency Filtering

• The quality factor of conventional passive filters is in the order of the lowest quality factor of the individual components which is low due to ohmic and substrate loss

• We need a filter that offers a quality factor higher than all individual components!

• The quality factor should be function of the geometry.

Spatial Filter

Different frequency components travel in different directions

321 ωωω ++

1ω2ω

3ω

Basic Principle

=∠ −

11

221

sinsintan

khkhVg

−

+

+

−

−

+

=∠= −

2sin

2sin

2sin

2sin

tan2121

2121

1

21

kkkk

kkkk

hhVgt

θ

First Prototype

• The first implementation at around 40GHz • Quality factor of around 50

Effect of Loss

• The performance enhances with frequency

LC Section Quality Factor

Filte

r Qua

lity

Fact

or

0

100

200

300

400

500

600

0 20 40 60 80 100 120

freq=230GHz

freq=115GHz

freq=57GHz

freq=460GHz

Outline

• Motivation










A THz Camera

Ehsan Afshari

(http://unic.ece.cornell.edu)

April 2012

Cornell University

A New Frontier: CMOS Terahertz Signal

Generation and Amplification

Example: Ring

Gd LdGd Ld Gd Ld

M1 M2 MN

Gd LdMnVʹ2

+

−

Iʹ2

+

Iʹ1

−

Vʹ1

Nk

VV πφ 2

1

2 =′′

∠=′

11

2 =′′

=′VV

A

[ ]

′′

′=

′′

2

1

2

1

VV

YII

• In a ring oscillator the phase conditions are set by the number of stages

• The gain of each stage is 1.

Example: Ring

Simulation of the maximum frequency of oscillation for a 3-stage ring oscillator in the employed 0.13 um CMOS

process.

Simulation of the maximum frequency of oscillation for a 2-stage ring oscillator in the employed 0.13 um CMOS

process.

Gm

(mS)

(N=2

, Gd=

0)

Frequency (GHz)

0 25 50 75 100 125 150 175 200

-2

0

2

4

8

6

-4

-6

-8

-10

fm-2=120.7 GHz

Max Gd for 100 GHz=1.5 mS

fmax=174 GHz

φʹ =180o

φʹ =0o

Gm

(mS

)(N

= 3, G

d=0 )

fm-3=172 GHz

fmax=174 GHz

Max Gd for 100 GHz=3 mS

Frequency (GHz)

-2

0

2

4

6

-4

-6

-8

-10

-120 25 50 75 100 125 150 175 200

φʹ =0o

φʹ =-120o

φʹ =120o

0)2)(cos()( 21122112221121

>++∠+−++−== ∗∗

NkYYYYGGG

VVPG d

Rm

πActivity Condition:

A New Frontier: CMOS Terahertz Signal Generation...

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