A NEW FAMILY OF TRANSFORMERLESS MODULAR … A New Family of Transformerless Modular DC-DC Converters...

A NEW FAMILY OF TRANSFORMERLESS MODULAR DC-DC CONVERTERS FOR HIGH POWER

APPLICATIONS

by

Abdelrahman Hagar

A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy

Graduate Department of Electrical and Computer Engineering University of Toronto

© Copyright by Abdelrahman Hagar 2011

ii

A New Family of Transformerless Modular DC-DC Converters for

High Power Applications

Abdelrahman Hagar

Doctor of Philosophy

Department of Electrical and Computer Engineering

University of Toronto

2011

Abstract

This thesis presents a new family of converters for high power interconnection of dc buses

with different voltage levels. Proposed converters achieve high voltage dc-dc conversion without

an intermediate ac conversion stage. This function is implemented without series connection of

active switches, or the use of isolation transformers. The salient features of proposed converters

are (i) design and construction simplicity, (ii) low switching losses through soft turn-on and soft

turn-off, (iii) single stage dc-dc conversion without high-current chopping, (iv) modular

structure, (v) equal voltage sharing among the converter modules.

Three converter circuits are investigated. The first performs unidirectional power transfer

from a dc bus with higher voltage to a dc bus with lower voltage. The second performs

unidirectional power transfer from a dc bus with lower voltage to a dc bus with higher voltage.

Both converters are suitable for interconnecting single pole dc buses with same polarity, or

double pole dc buses. A third converter is also presented which performs the function of either

the first or the second converter with polarity reversal. The third converter is suitable for

interconnecting single pole dc buses with different polarities, or double pole dc buses. By hybrid

iii

integration of the proposed three converters, the thesis also investigates other topologies for

bidirectional power transfer between two dc buses.

Proposed converters operate only in discontinuous conduction mode and exhibit soft

switching operation for the active and passive switches. A common feature between the proposed

converters is the self current turn-off for the active switches at zero voltage. This allows the use

of thyristors as active switches alleviating their reverse recovery losses. For each converter

topology, the structure is presented, its operation principle is explained and a complete set of

design equations are derived. Comparisons are performed on high-power and high-voltage

design examples. The merits and limitations of each converter are concluded. Practical

considerations regarding components selection, loss analysis, filter design and the non-idealities

of the circuits are studied. Experimental implementation of scaled-down laboratory prototypes is

presented to provide a proof of concept and validate the operation principle of the proposed

converter topologies.

iv

Acknowledgments

First of all I would like to express my gratitude and appreciation to my thesis advisor, Prof.

Peter W. Lehn. His continuous advice, guidance, feedback and encouragement are much behind

the realization of this work.

I also owe a lot to my committee members, whose advice and feedback were a valuable

contribution to my thesis.

I would like to thank Mr. Jack Goldstein, the laboratory manager, for his help and invaluable

advice during the experimental phase of this project. Finally, I‘d like to thank Mr. Mike Ranjram

for his assistance in the laboratory.

v

Table of Contents

Acknowledgments .......................................................................................................................... iv

Table of Contents ............................................................................................................................ v

List of Tables ................................................................................................................................. ix

List of Figures ................................................................................................................................. x

List of Appendices ........................................................................................................................ xv

Nomenclature ............................................................................................................................... xvi

Chapter 1 Introduction ................................................................................................................. 1

1.1 Statement of the Problem .................................................................................................... 1

1.2 Thesis Objectives ................................................................................................................ 2

1.3 Background ......................................................................................................................... 4

1.3.1 Classical PWM Converters ..................................................................................... 4

1.3.2 DC-DC Converters with Transformers or Coupled Inductors ................................ 8

1.3.3 Multi-module series-parallel dc-dc converters ..................................................... 12

1.3.4 Transformerless switched capacitor dc-dc converters .......................................... 15

1.3.5 Voltage Multiplier-based Hybrid DC-DC Converters .......................................... 17

1.3.6 Soft-switched Tranformerless DC-DC Converters ............................................... 18

1.4 Thesis Outline ................................................................................................................... 21

Chapter 2 Structure and Operation Principle ......................................................................... 22

2.1 Introduction ....................................................................................................................... 22

2.2 Structure of the active switching network ........................................................................ 23

2.3 The Modular Step-down Converter. ................................................................................. 26

2.4 The Modular Step-up Converter. ...................................................................................... 32

2.5 The Modular Inverting Converter ..................................................................................... 39

vi

2.6 Modular Bidirectional Converters .................................................................................... 46

2.7 Summary ........................................................................................................................... 50

Chapter 3 Converter Modeling and Design .............................................................................. 51

3.1 Introduction ....................................................................................................................... 51

3.2 Assumptions ...................................................................................................................... 52

3.3 Resonant capacitors design ............................................................................................... 54

3.3.1 Step-down converter ............................................................................................. 54

3.3.2 Step-up converter .................................................................................................. 55

3.3.3 Inverting converter ................................................................................................ 57

3.3.4 Comments ............................................................................................................. 58

3.4 Current and voltage in resonant elements ......................................................................... 59

3.5 The conduction angle ........................................................................................................ 63

3.6 Resonant inductor sizing ................................................................................................... 65

3.7 Semiconductors current ratings ......................................................................................... 66

3.8 Semiconductors voltage ratings ........................................................................................ 68

3.9 Summary ........................................................................................................................... 72

Chapter 4 Practical Aspects ....................................................................................................... 74

4.1 Introduction ....................................................................................................................... 74

4.2 Fault propagation .............................................................................................................. 75

4.2.1 Input terminal faults .............................................................................................. 75

4.2.2 Output terminal faults ........................................................................................... 76

4.3 Semiconductors power losses ........................................................................................... 84

4.3.1 Thyristor losses ..................................................................................................... 84

4.3.2 Diode losses .......................................................................................................... 87

4.4 Filtering capacitors ............................................................................................................ 88

4.5 Black-start during step-up operation ................................................................................. 89

vii

4.6 The ESR effect on the maximum step-up ratio ................................................................. 90

4.7 Effect of the stray inductance ........................................................................................... 91

4.8 Thyristors turn-off time ..................................................................................................... 97

4.9 Design steps ...................................................................................................................... 99

4.10 Design trade-offs ............................................................................................................. 101

4.11 Summary ......................................................................................................................... 102

Chapter 5 Design Examples and Experimental Prototyping ................................................ 103

5.1 Introduction ..................................................................................................................... 103

5.2 Converters design ............................................................................................................ 105

5.2.1 Switch selection .................................................................................................. 105

5.2.2 Resonant capacitance .......................................................................................... 105

5.2.3 Converter cells .................................................................................................... 106

5.2.4 Diode selection .................................................................................................... 106

5.2.5 Inductor sizing .................................................................................................... 107

5.2.6 Design results ...................................................................................................... 107

5.3 Graphical Comparisons .................................................................................................... 118

5.4 Experimental prototyping ............................................................................................... 123

Chapter 6 Conclusions and Future Work .............................................................................. 135

6.1 Conclusions ..................................................................................................................... 135

6.2 Thesis Contributions ....................................................................................................... 137

6.3 Suggested Future Work ................................................................................................... 138

References ................................................................................................................................... 139

Appendix A ................................................................................................................................. 144

Appendix B ................................................................................................................................. 146

Appendix C ................................................................................................................................. 148

Appendix D ................................................................................................................................. 153

viii

Appendix E ................................................................................................................................. 155

Appendix F .................................................................................................................................. 160

ix

List of Tables

Table 3-1 Summary of basic design parameters derived in chapter 3 .......................................... 73

Table 5-1 Comparison between the ratings of light triggered thyristors .................................... 104

Table 5-2 Comparison between the ratings of fast recovery diodes ........................................... 104

Table 5-3 Design parameters for the converters of the first design example ............................. 108

Table 5-4 Design parameters for the converters of the second design example ......................... 109

Table 5-5 Design parameters for the converters of the third design example ............................ 110

Table 5-6 Design parameters for the converters of the fourth design example .......................... 111

Table 5-7 Comparison between design parameters of the proposed converter for the four design

examples ..................................................................................................................................... 112

Table 5-8 Loss analysis of the proposed converters for the four design examples .................... 113

Table 5-9 Comparison between inverting and non-inverting step-up converters ....................... 121

Table 5-10 Comparison between inverting and non-inverting step-up converters ..................... 122

Table 5-11 Design parameters of the experimental converters................................................... 127

Table 5-12 Semiconductor parameters for the conduction losses calculations .......................... 131

Table 5-13 Loss analysis of the converters ................................................................................. 132

Table F- 6-2 Simulation parameters ............................................................................................ 164

x

List of Figures

Figure 1-1 Alternatives for the connection of two dc buses with different voltage levels ............. 2

Figure 1-2 Basic classification of dc-dc converters ........................................................................ 4

Figure 1-3 Classical dc-dc converters. (a) Boost converter, (b) buck converter ............................ 6

Figure 1-4 (a) Cuk converter, (b) Middlebrook‘s converter [26] ................................................... 7

Figure 1-5 Quadratic dc-dc converter [28] ..................................................................................... 7

Figure 1-6 DC-DC converter topology with coupled inductors [22]. ............................................. 9

Figure 1-7 An active clamp flyback converter [23] ........................................................................ 9

Figure 1-8 Voltage fed full Bridge dc-dc converter [3]. .............................................................. 10

Figure 1-9 Current fed full bridge dc-dc converter [12]. .............................................................. 11

Figure 1-10 Multi-module converters. (a) Input-Series Output-Series, (b) Input-Series Output-

Parallel, (c) Input-Parallel Output-Series, (d) Input-Parallel Output-Parallel .............................. 13

Figure 1-11 Example of an ISOP converter [28] .......................................................................... 14

Figure 1-12 Switched capacitor multilevel dc-dc converter proposed in [30]. ............................. 15

Figure 1-13 Modular multilevel capacitor clamped converter proposed in [31] .......................... 16

Figure 1-14 Resonant switched capacitor dc-dc converters [33] .................................................. 16

Figure 1-15 Cockroft-Walton voltage multiplier .......................................................................... 17

Figure 1-16 A dc-dc multilevel boost converter [21] ................................................................... 18

Figure 1-17 Bidirectional high power dc-dc converter of [10] ..................................................... 19

Figure 1-18 High-power step down dc-dc converter of [13] ........................................................ 20

Figure 1-19 High power step-down dc-dc converter of [37] ........................................................ 20

Thesis_final_SGS.docx#_Toc287730686

xi

Figure 2-1 Structure of the modular active switching network .................................................... 24

Figure 2-2 Different switching schemes of the active switching network .................................... 25

Figure 2-3 Structure of the modular step-down converter ............................................................ 28

Figure 2-4 Step-down converter during intervals a, b, c of the first switching half-cycle ........... 29

Figure 2-5 Step-down converter during intervals d, e, f of the second switching half-cycle ....... 30

Figure 2-6 Ideal steady-state waveforms of the modular step-down converter ............................ 31

Figure 2-7 Structure of the modular step-up converter ................................................................. 33

Figure 2-8 Step-up converter during intervals a, b, c of the first switching half-cycle ................ 35

Figure 2-9 Step-up converter during intervals d, e, f of the second switching half-cycle ............ 36

Figure 2-10 Ideal steady-state waveforms of the modular step-up converter ............................... 37

Figure 2-11 Capacitor voltage build-up process during the step-up converter black-start ........... 38

Figure 2-12 Inductor and output currents of the step-up converter during the black-start process

....................................................................................................................................................... 38

Figure 2-13 Structure of the modular inverting converter ............................................................ 40

Figure 2-14 Capacitor voltage build-up of the inverting converter in step-up mode ................... 41

Figure 2-15 Inverting converter during intervals a, b, c of the first switching half-cycle ............ 42

Figure 2-16 Inverting converter during intervals d, e, f of the second switching half-cycle ........ 43

Figure 2-17 Ideal steady-state waveforms of the inverting converter during step-down ............. 44

Figure 2-18 Ideal steady-state waveforms of the inverting converter during step-up .................. 45

Figure 2-19 Structure of the modular bidirectional converter ...................................................... 46

Figure 2-20 Structure of the single-inductor modular bidirectional converter ............................. 47

xii

Figure 2-21 Structure of the inverting modular bidirectional converter ....................................... 48

Figure 2-22 Structure of the single-inductor inverting modular bidirectional converter .............. 49

Figure 3-1 Simplified structure of (a) step-down, (b) step-up and (c) inverting converters ......... 53

Figure 3-2 Basic waveforms for step-down operation during continuous conduction ................. 59

Figure 3-3 Basic waveforms for step-up operation during continuous conduction ...................... 60

Figure 3-4 Equivalent circuit of the converters when the active switches are conducting ........... 61

Figure 3-5 The voltage gain vs. the conduction angle for the step-down converter ..................... 64

Figure 3-6 The voltage gain vs. the conduction angle for the step-up converter .......................... 64

Figure 3-7 The voltage gain vs. the conduction angle for the inverting converter ....................... 64

Figure 3-8 Voltage and current waveforms of the switches and diodes during step-down

operation ....................................................................................................................................... 70

Figure 3-9 Voltage and current waveforms of the switches and diodes during step-down

operation ....................................................................................................................................... 71

Figure 4-1 Zero impedance input fault condition for the (a) step down, (b) step up and (c)

inverting converters ...................................................................................................................... 77

Figure 4-2 Voltage and current waveforms of the inverting converter during a zero impedance

input fault condition during the step up mode .............................................................................. 78

Figure 4-3 Zero impedance output fault condition for the (a) step down, (b) step up and (c)

inverting converters ...................................................................................................................... 79

Figure 4-4 Voltage and current waveforms of the step-down converter during a zero impedance

output fault condition at its terminal ............................................................................................. 82

Figure 4-5 Voltage and current waveforms of the inverting converter during a zero impedance

output fault condition at its terminal ............................................................................................. 83

xiii

Figure 4-6 Linear model to estimate the reverse recovery losses ................................................. 86

Figure 4-7 The influence of the commutating inductance on the current and voltage waveforms

during step-down operation .......................................................................................................... 92


of the switches and diodes during step-down operation ............................................................... 93


during step-down operation .......................................................................................................... 94


of the switches and diodes during step-down operation ............................................................... 95

Figure 4-11 Simplified design flow-chart ................................................................................... 100

Figure 5-1 Comparison between the resonant inductance values (units are in m.H per pole) ... 118

Figure 5-2 Comparison between the resonant capacitance values (units are in µ.F per pole) .... 119

Figure 5-3 Comparison between the semiconductor losses ........................................................ 120

Figure 5-4 Picture showing two active switching cells .............................................................. 124

Figure 5-5 Picture showing the diodes and measurement units .................................................. 125

Figure 5-6 Picture showing the transformer of the high voltage side ......................................... 125

Figure 5-7 Schematics of the experimental (a) Step-down and (b) step-up converters .............. 126

Figure 5-8 Step-down converter experimental waveforms. The figure shows the inductor current

on Ch1, the diode current on Ch4, the voltage of the capacitor of the first cell on Ch2 and the

voltage of the capacitor of the second cell on Ch3. .................................................................... 128

Figure 5-9 Step-down converter experimental waveforms. The figure shows the inductor current

on Ch1, the capacitors current on Ch4, the switch voltage vs1 on Ch2 and the switch voltage vs2

on Ch3 ......................................................................................................................................... 129

xiv

Figure 5-10 Step-down converter experimental waveforms. The figure shows the inductor

current on Ch1, the diode current on Ch4, the diode voltage on Ch2 and the voltage of the active

switching network vc* on Ch3. .................................................................................................... 130

Figure 5-11 Step-up converter experimental waveforms. The figure shows the inductor current

on Ch4, the diode current on Ch1, the voltage of the capacitor of the first cell on Ch3 and the

voltage of the capacitor of the second cell on Ch2. .................................................................... 131


on Ch4, the capacitors current on Ch1, the switch voltage vs1 on Ch3 and the switch voltage vs2

on Ch2 ......................................................................................................................................... 132


on Ch4, the diode current on Ch1, the diode voltage on Ch2 and the voltage of the active

switching network vc* on Ch3. .................................................................................................... 133

Figure 5-14 The efficiency of the experimental prototypes ........................................................ 134

xv

List of Appendices

Appendix A Voltage gain for passive loads

Appendix B Derivation of the maximum step-up ratio

Appendix C The stray inductance

Appendix D Bidirectional single-inductor converter design

Appendix E Final design parameters

Appendix F Power controller design

xvi

Nomenclature

Acronyms

AC Alternating Current

CCM Continuous Conduction Mode

CW Cockroft Walton

DC Direct Current

DCM Discontinuous Conduction Mode

ESR Equivalent Series Resistance

EMI Electromagnetic Interference

HVDC High Voltage Direct Current

IGBT Insulated Gate Bipolar Transistor

IGCT Insulated Gate Commutated Thyristor

IPOP Input Parallel Output Parallel

IPOS Input Parallel Output Series

ISOP Input Series Output Parallel

ISOS Input Series Output Series

LCC Line Commutated Converter

LPF Low Pass Filter

PWM Pulse Width Modulation

RMS Root-Mean-Square

RB-IGBT Reverse Blocking IGBT

VSC Voltage Sourced Converter

ZCS Zero Current Switching

ZVS Zero Voltage Switching

xvii

Symbols

nrc Capacitance per converter cell (F)

rC Equivalent resonant capacitance for the converter (F)

rr CC / Equivalent resonant capacitance per pole (F)

fC Filter capacitance (F)

rL Equivalent resonant inductance for the converter (H)

rr LL / Equivalent resonant capacitance per pole (H)

fL Filter inductance (H)

cL

Stray inductance in the commutation circuit (H)

ro / Natural (or resonant) frequency of the converter (rad/s)

sf

Switching frequency of the active switches (Hz)

max|abssf

Absolute maximum switching frequency (Hz)

sT

Switching period of the active switches (s)

BST

Black-start time of the step-up converter (s)

ot Discontinuous time interval of the inductor‘s current (s)

offrt Thyristor off-time duration while reverse biased (s)

offft

Thyristor off-time duration while forward biased (s)

qt Circuit commutated turn-off time of thyristors (s)

N Number of converter cells

Conduction angle at which commutation starts (rad)

cv

Voltage of the equivalent resonant capacitance (V)

rncv

Voltage of the capacitor of one converter cell (V)

cov

Initial resonant capacitor voltage before switching (V)

xviii

*

cv

Voltage of the active switching network (V)

rsv

Reverse blocking voltage of the active switch (V)

fsv

Forward blocking voltage of the active switch (V)

pkcpc vv ,

Peak voltage of the equivalent resonant capacitor (V)

fpkcv

Peak voltage of the equivalent resonant capacitor during fault (V)

iv

Voltage of the input side of the converter (V)

ov

Voltage of the output side of the converter (V)

offDv

Turn-off voltage of the diode (V)

offsv

Turn-off voltage of the switch (V)

TV

On-state voltage drop on a thyristor/ diode (V)

TOV

Threshold voltage of a thyristor/diode (V)

FRMV

Maximum forward recovery voltage of the diode (V)

maxTv

Maximum on-state voltage drop on a thyristor (V)

maxonDv

Maximum on-state voltage drop on a diode (V)

avi

Average current (A)

RMSi

Root-mean-square current (A)

Li Resonant inductor current (A)

pkLi Peak resonant inductor current (A)

crnc ii ,

Resonant capacitor current (A)

Di Diode current (A)

si Active switch current (A)

ii Input current (A)

oi Output current (A)

oI

Continuous conduction current (A)

TI

Thyristor on-state current (A)

xix

faulti

Fault current (A)

fpkLi Peak current of the resonant inductor during fault (A)

iP

Input power (W)

oP

Output power (W)

LP

Load power (W)

CondP

Conduction power loss (W)

ONTurnP Switching power loss during turn-on (W)

OFFTurnP Switching power loss during turn-off (W)

ONTurnW Switching energy loss during turn-on (J)

OFFTurnW Switching energy loss during turn-off (J)

StateONW On-state energy loss (J)

StateOFFW Off-state energy loss (J)

offD

dt

id|

Diode current rate of change at turn-off (A/s)

onS

dt

id|

Switch current rate of change during turn-on (A/s)

offs

dt

vd|

Rate of change of the forward bias voltage of a thyristor while in the off-state

(V/s)

rrE

Reverse recovery energy loss (J)

rrQ

Reverse recovery charge (C)

RMI

Maximum reverse recovery current (A)

1

Chapter 1 Introduction

1

1.1 Statement of the Problem

While high power High Voltage Direct Current (HVDC) transmission is now considered a well-

established technology, its application is still dependent on utilizing either Line Commutated

Converters (LCC) or Voltage Sourced Converters (VSC). These converters connect dc buses

with ac buses and handle power of hundreds of megawatts at voltages of hundreds of kilovolts.

Recently, the subject of dc bus interconnections has started to gain increased interest. This

interest is driven by the desire to (i) interface power sources that generate dc on a megawatt

power range [1], [2], (ii) integrate windfarms through offshore dc networks [3], (iii) build dc

distribution networks and dc microgrids [4]-[6], (iv) build dc back-up energy systems [7], (v)

build medium-voltage industrial drives, high-speed train power systems and undersea

observatories [8],[9] and (vi) provide additional access points to the existing HVDC lines [10].

Two possible alternatives enable the interconnection of dc buses and are shown in Fig.1-1. The

first is by using VSC or LCC systems while the second by direct dc-dc conversion. In contrast to

VSC and LCC systems, the use of dc-dc converters will directly interconnects dc buses of

different voltage levels without use of intermediate ac conversion stage.

Low-voltage and low-power dc-dc converters have long been studied and implemented. High

voltage low-power dc-dc converters are less popular but are used in some applications, such as

medical X-ray imaging, radio frequency generation, travelling-wave tubes, lasers and high

intensity discharge lamps [11], [12]. High-voltage and high-power dc-dc converters are not

available as market products yet, but are subject to research efforts [10],[13]-[15],[37].

Classical dc-dc converter topologies have limitations preventing their use for high-power and

high-voltage applications. Since power semiconductors have limited voltage ratings, the high-

voltage realization of classical topologies would require series connection of active switches

(IGBTs in this case). This requires active gate control to ensure equal voltage sharing between all

2

devices at switching instances [16],[17]. Implementing active gate control techniques results in

significant increase in switching losses (up to 36% as in [18] ).

Additionally, classical PWM circuits (e.g. buck and boost topologies) require extreme duty

cycles at higher conversion ratios. An extreme duty cycle impairs efficiency and may cause

malfunctions due to the very short conduction time of power semiconductor devices [19]. Other

classical topologies use intermediate isolation transformers, such as the fly-back converter. If the

application does not require isolation, the use of a transformer would only increase the cost, the

volume, and the losses especially for high power applications, as detailed in [19]-[21]. Specifically,

the large number of turns ratio with the need for high voltage isolation increases the leakage inductance

and parasitic capacitance of the windings. This causes undesirable voltage and current spikes to

switches leading to increased losses and reduced reliability [11]. Proposed transformerless soft-

switched topologies for high voltage and high power applications in [10], [13]-[15] have several

limitations of unequal voltage stresses on semiconductors as in [13], or restrictions to bipolar dc

network interconnections as in [10], [14], [15] with potential shoot-through problems during

fault conditions. Moreover, these topologies require the use of high voltage resonant capacitor

banks, and long series strings of high voltage active switches.

Figure ‎1-1 Alternatives for the connection of two dc buses with different voltage levels

1.2 Thesis Objectives

This thesis addresses the problem of dc-dc converters suitable for high-power and high-

voltage applications. A new family of converter topologies is proposed and studied for these

3

applications. Proposed converters employ ZCS and ZVS of the switches, having modular

structure and equal voltage distribution among the converter modules.

. The main objectives of this thesis are:

1. To propose a new family of converter topologies for high voltage and high power dc

applications, specifically kilovolt and megawatt scale. Four topologies are presented:

i. Modular step-down converter. This converter performs unidirectional power

transfer from a dc bus with higher voltage to a dc bus with lower voltage without

the need for a transformer or series connection of active switches. It operates on

both unipolar and bipolar buses and has modular structure with soft switching

behavior of power semiconductor devices.

ii. Modular step-up converter. This converter performs unidirectional power transfer

from a dc bus with lower voltage to a dc bus with higher voltage with the same

features mentioned in i.

iii. Modular polarity-reversal converter. This converter performs unidirectional power

transfer between two dc buses with different polarity and voltage levels. It can

operate in either step-down or step-up modes, maintaining the same features

mentioned in i.

iv. Modular bidirectional converters. These topologies use hybrid connections of the

converters mentioned in i, ii and iii to perform bidirectional power transfer between

dc buses.

2. To develop a complete set of mathematical design equations for the proposed converters to

allow selection of their components based on the desired voltage and power rating.

3. To support the theoretical predictions and demonstrate implementation feasibility. The

topologies have been investigated through design examples for different voltage and power

levels, and through experimental setup of scaled-down laboratory prototypes.

4

1.3 Background

This section reviews existing dc-dc converter topologies and identifies their limitations for high-

voltage and high-power applications. DC-DC converters have long been studied for low-power

(kilowatt range) or low-voltage range (hundreds of volts), but extending their operation to the

megawatt power range at kilovolt voltage levels implies some restrictions. In this section, these

restrictions are outlined for known topologies. Available dc-dc converters in literature can be

classified into major families shown in Fig. 1-1. The following subsections provide more details

on each of these converter families.

1.3.1 Classical PWM Converters

The most popular and widely used dc-dc converters are the buck, boost, buck-boost converters.

The underlying concept of these circuits depends on chopping the input dc voltage with a

specific duty cycle to generate a desired output voltage level. The switching frequency is usually

maintained at constant value and the pulse width (on state duration) is modulated. Fig. 1-2 shows

the buck and boost converter circuits. These circuits are simple in construction but suffer from

DC – DC Converters

1.3.1 Classical PWM converters 1.3.2 Converters with transformers

or couple inductors

1.3.3 Multi-module series parallel

converters

1.3.4 Transformerless switched-

capacitor converters

1.3.5 Voltage multiplier-based

hybrid converters

1.3.6 Transformerless soft-switched

converters

Figure ‎1-2 Basic classification of dc-dc converters

5

limitations preventing their use on high-power and high-voltage applications. These limitations

can be summarized as follows:

For high dc voltage conversion ratio, these converters operate with an extreme value of

duty cycle. This operating mode results in increasing the losses associated with the circuit

components degrading the efficiency [7]. The extreme duty cycle may even cause

malfunction of the semiconductor switches due to the very short conduction time [19].

To realize high voltage switches, series connection of active switches (IGBTs in this

case) is needed. This requires active gate control to ensure equal voltage sharing between

devices at switching instances [16],[17]. Implementing active gate control techniques

results in significant increase in switching losses (up to 36% as in [18] ).

In case of fault conditions, current chopping converters either allow output faults to

propagate to the input source, or require the active switch to interrupt the fault current.

Both scenarios are unacceptable for many high power and high voltage applications.

Several circuits were proposed in literature to overcome the above mentioned limitations. Cuk

and Middlebrook proposed transformerless dc-dc converters with large conversion ratios [26],

shown in Fig. 1-4. Cuk also proposed a family of quadratic dc-dc converters in [28]. These

converters can achieve high conversion ratios at high efficiencies with lower switching stresses

as compared to classical buck-boost and buck-boost converters. For high voltage and high power

applications, these converters would require high voltage valves of series active switches, high

voltage capacitors and have no modular structure.

6

iv

L

S

D

oC

iv

LS

D

ov

ov

(a)

(b)

oC

Figure ‎1-3 Classical dc-dc converters. (a) Boost converter, (b) buck converter

7

iv

L

S D oCov

(a)

(b)

oLC

iv

L

S D oCov

oL

1C

S

2C

Figure ‎1-4 (a)‎Cuk‎converter,‎(b)‎Middlebrook’s‎converter‎[26]

iv

L S

3DoC

ov

oL

C1D

2D

Figure ‎1-5 Quadratic dc-dc converter [28]

8

1.3.2 DC-DC Converters with Transformers or Coupled Inductors

Compared with classical buck, boost and buck-boost circuits, transformer-based converters can

achieve higher conversion ratios with lower losses [5]. The same feature applies to converters

with coupled inductors [7]. The turns ratio of the transformer or the coupled inductors help

realize higher stepping ratios [24]. Fig 1-6 shows a high step-up converter with coupled inductor

[22]. Fig. 1-7 shows an active clamp flyback converter [23].

The main limitation of these converters is the problems related to the transformer. The large

turns ratio and high voltage isolation requirements increases the leakage inductance and parasitic

capacitance of the winding. At switching instants, the transformer parasitics will result in high-

voltage spikes across the switches [7]. Voltage and current spikes lead to increased losses and

reduced reliability, and may damage circuit components [11], [12]. This problem can only be

addressed by connecting snubber circuits to the switches or by utilizing the transformer parasitics

as resonant tank and operating these converters as resonant soft-switched converters.

A comparative theoretical study of three dc-dc topologies can be found in [3]. It shows that

the voltage-fed full-bridge converter (shown in Fig.1-8), can be attractive from the energy

efficiency point of view. The limitation is that this topology incorporates an isolation transformer

and requires snubber capacitors to achieve soft switching. In this converter, there is no suitable

value for the snubber capacitors for the whole operation range [3]. This topology also needs an

output inductor which creates high voltage spikes on the diodes of the output bridge [3]. Finally,

the core losses in the transformer can be significant high at reduced power operation.

9

iv

1L

S

oD

ov

2L

1C

2C

oC2D

1D

Figure ‎1-6 DC-DC converter topology with coupled inductors [22].

iv

1C

aS

1S

Dov

oC1N2N

Figure ‎1-7 An active clamp flyback converter [23]

10

21 :NN sL

ivov

1S

2S

3S

4S

1D 2D

3D 4D

fL

oC

Figure ‎1-8 Voltage fed full Bridge dc-dc converter [3].

Unlike the voltage-fed converters, current-fed resonant converters (shown in Fig.1-9) need no

output inductor or snubber circuits on the switches [12]. Zero-Current Switching (ZCS) can be

achieved for the switches by utilizing the transformer parasitics as a resonant tank. This allows

reductions in voltage and current spikes on the power devices, as well as decreasing the

switching losses. As a result, these converters are more attractive for high voltage dc-dc

conversion. A major limitation of this converter is their sensitivity to the parameters of the

resonant tank in order to maintain ZCS. As the transformer parasitics are used to achieve ZCS,

these converters require relatively high frequency operation (45-150KHz) [12].

11

oviv c

rL

inL

Transformer1S

2S

3S

4S

1D 2D

3D4D

oC

Figure ‎1-9 Current fed full bridge dc-dc converter [12].

For high-power and high-voltage applications in which isolation is not required, the presence

of the transformer will significantly add to the size, weight and cost of the converter. The

converter design problem becomes more complicated in order to address the design issues of the

high-voltage middle-frequency transformer with pre-specified parasitics. These issues include

the values of the leakage inductance and parasitic capacitance of the winding, as well as the high

voltage insulation and magnetic core material [20]. Transformer saturation can have harmful

consequences, like increasing conduction and switching losses of semiconductors. Primary

switch failure caused by large peak currents during saturation is the most harmful threat [20].

These problems make transformer based converters less reliable and unattractive for high-power

and high-voltage applications.

12

1.3.3 Multi-module series-parallel dc-dc converters

Multi-module dc-dc converters consist of identical standardized power modules connected in

series or parallel at the input and output sides [25]-[29]. The advantages of multi-module

series/parallel converters are:

Short design process and lower production cost because of standardized modules.

Enhanced system reliability because of redundancy.

Ease of thermal design, because the total power is divided between the modules.

Scalability and ease of expansion.

Multi-module dc-dc converters can be classified into four architectures. (i) input-series output

series (ISOS) shown in Fig. 1-10 a, (ii) input-series output-parallel (ISOP) shown in Fig. 1-10 b,

(iii) input-parallel output-series (IPOS) shown in Fig. 1-10 c, (iv) input-parallel output-parallel

shown in Fig. 1-10 d. Each module has an isolated dc-dc sub-converter. An example of ISOP

converter is shown in Fig.1-11.

Series modules are connected to the high voltage side of the bus, while parallel modules are

connected to the high-current side of the bus. Thus, a step-down dc-dc converter will utilize the

ISOP architecture, while a step-up dc-dc converter will utilize the IPOS architecture. These

converters are not restricted to dc-dc operation. For example, in [25] the ISOP architecture is

used as a dc/ac converter. To date, none of these converters have been proposed for high-voltage

and high-power dc-dc applications. The IPOP architecture has been widely used in distributed

power systems, power factor correction converters, and uninterruptable power supplies while the

ISOP architecture is used in high-speed train power systems [25], [27]. The main demerit of

these converters is the use of an isolation transformer in each converter module.

13

1iv

1ov

2iv

2ov

miv

mov

iv

+

-

ov

+

-

1iv

1ov

2iv

2ov

miv

mov

iv

ov+

-

+

-

1iv

1ov

2iv

2ov

miv

mov

iv+

-

ov

+

-

1iv

1ov

2iv

2ov

miv

mov

ov+

-iv+

-

(a) (b)

(c) (d)

Figure ‎1-10 Multi-module converters. (a) Input-Series Output-Series, (b) Input-Series

Output-Parallel, (c) Input-Parallel Output-Series, (d) Input-Parallel Output-Parallel

14

rL

iv

fL

ov

11D

12D

11S

12S

13S

14S

oC

rL

fL21D

22D

21S

22S

23S

24S

1C

2C

Figure ‎1-11 Example of an ISOP converter [28]

For high power application, where isolation is not required, the cost and weight of the

submodule isolation transformers is not justified. Additionally, for high voltage applications, the

isolation transformers need to be insulated up to the value of the high voltage rail. Providing

such insulation level requires a special structure and will be costly. Taking into considerations

the demerits mentioned earlier, it is concluded that the multi-module converter topologies may

not be practical for megawatt and kilovolt size applications.

15

1.3.4 Transformerless switched capacitor dc-dc converters

The quest for transformerless dc-dc converters operating at high conversion ratios led to the

development of switched-capacitor and switched-inductor converters [19]. In contrast to

switched-inductor circuits, switched capacitor converters avoid using magnetic elements. This

allows producing compact and light-weight circuits operating at higher temperatures. Fig. 1-12

shows a switched-capacitor multilevel dc-dc converter proposed in [30]. This topology is

proposed for low voltage light power applications and can achieve high efficiency. In [31], the

limitations of this topology for high power applications are summarized as follows: 1) non-

modular structure; 2) relatively complicated switching scheme; 3) difficulty in high frequency

operation and requirement of complicated capacitor voltage balancing scheme; 4) excessive

voltage drop across the switches; 5) lack of bidirectional power management and; 6) no fault

bypass capability. To overcome these limitations, a multilevel modular capacitor-clamped

converter is proposed in [31] and shown in Fig.1-13.

ov

iv1C

1C2C

pS1

pS2

pS3

nS3

nS 2

nS1

Figure ‎1-12 Switched capacitor multilevel dc-dc converter proposed in [30].

16

oviv 1C

2C3C4C

1S2S

3S

4S

5S

6S

7S

8S

9S

01S

Figure ‎1-13 Modular multilevel capacitor clamped converter proposed in [31]

The advantages of this topology are: 1) high frequency operation capability; 2) low

input/output current ripple; 3) low ON-state voltage drop, and bidirectional power flow

management. For high voltage applications, however, this topology has a major limitation. To

ensure equal voltage stress across the switches, capacitors in different modules have to withstand

unequal voltage stress.

A common disadvantage of switched-capacitor converters is the high current spikes resulting

from capacitors switching. Such current spikes are only limited by the equivalent series

resistance between capacitors. For high power applications, this imposes severe stresses on the

switches. To solve this problem, resonant switched-capacitor converters are proposed in [32],

[33] and is shown in Fig. 1-14. This topology includes a resonant inductor Lr in the circuit

allowing ZCS of all switches. The technical feasibility of this topology has been criticized in [34]

as it suffers from poor regulation against load and input voltage variation. [35], [36] also propose

other topologies for switched capacitor converters but they share the same limitations of previous

topologies and are not suitable for high-power and high voltage applications.

ivov

pS1

pS2 pS3 nS3nS 2

nS1

pS4 nS4

1C

2C

3C

4C

5C

rL

Figure ‎1-14 Resonant switched capacitor dc-dc converters [33]

17

1.3.5 Voltage Multiplier-based Hybrid DC-DC Converters

The Cockroft-Walton (CW) circuit (shown in Fig.1-15) was first introduced in 1932. This circuit

operates as a voltage multiplier fed by a pulsating low voltage waveform to generate a high

voltage dc on its output terminal. Its main application is to generate high voltage dc required for

insulation testing generators and particle accelerators. As the multiplication ratio increases, the

CW circuit suffers from poor load regulation resulting in a large voltage drop at its output

terminal. For this reason, the CW circuit needs another converter to provide output voltage

regulation.

In [11] an isolated hybrid dc-dc converter composed of series-resonant and a CW circuit is

proposed for medical-use high-voltage X-ray power generator. In [21] a transformerless

multilevel boost converter (shown in Fig.1-16) is introduced by hybrid connection of CW and a

classical boost converter. The later targets fractional kilowatt renewable power applications.

Both converters in [21] and [11] can provide very large dc voltage step-up ratio at high

efficiency. However, these circuits can not be used for high power applications. They share the

same high current-spike problem resulting from charging/discharging capacitors connected in

parallel. This was the same limitation of the switched-capacitor converter discussed earlier. The

circuit shown in Fig.1-16 also relies on a high-current boost converter at the input stage. This

boost circuit is necessary to provide a pulsating input voltage waveform for the CW circuit, and

provide output voltage regulation through PWM. The presence of this boost circuit is also

unattractive for high power applications. Finally, voltage multiplier hybrid dc-dc converters can

not achieve dc voltage step-down operation.

iv

ov

Figure ‎1-15 Cockroft-Walton voltage multiplier

18

iv

L

S

1C

ov

2C

3C

4C

5C

1D

2D

3D

4D

5D

oC

Figure ‎1-16 A dc-dc multilevel boost converter [21]

1.3.6 Soft-switched Tranformerless DC-DC Converters

The quest for high power dc-dc converters led to developing soft-switched transformerless

topologies using thyristors as active switches [10],[13]-[15],[37]. The soft-switching behavior

eliminates the problems associated with hard current chopping. Avoiding the use of transformers

results in light weight and less expensive circuits. The use of high voltage thyristors instead of

IGBTs reduces the conduction losses considerably.

In [10], a bidirectional converter is proposed and is shown in Fig. 1-17. The circuit relies on

using bidirectional high-voltage thyristor valves, high voltage resonant capacitors and inductors

to achieve dc-dc conversion without an intermediate transformer. The converter can not

interconnect unipolar buses sharing common ground and is only restricted for bipolar buses. The

step-down circuit can not be modeled in closed form mathematical formulas, making the design

hard. The circuit has shoot-through modes leading to possible fault propagation among

19

interconnected buses [15]. Finally, the non-modular structure and the use of high-voltage

resonant capacitor banks imply expensive implementation and large footprint.

In [13] a high power step-down dc-dc converter has been proposed and is shown in Fig. 1-18.

The circuit also avoids the use of transformers or high-current chopping. It can connect both

unipolar and bipolar buses and uses thyristors as active switches. The main limitation, however,

is the unequal voltage stresses on the thyristors. This problem is avoided with the converter

topology of [37] shown in Fig.1-16. This circuit uses lossless capacitive snubbers to ensure equal

voltage distribution on series-connected thyristors. The main limitation, however, is that the

output voltage is floating relative to the input voltage. This makes the circuit unattractive for

many applications. Both converters proposed in [15] and [37] (Fig. 1-18 and Fig.1-19) are only

restricted to dc voltage step-down operation mode.

1s

1s2s

2s

3s

3s

4s

4s

7s

7s8s

8s

5s

5s

6s

6s

rC2

rC2

12 fC

12 fC

2/1fL

2/1fL 2/1L

2/1L

2/2L

2/2L

2/2fL

2/2fL

22 fC

22 fC

2/ov

2/ov

2/iv

2/iv

Figure ‎1-17 Bidirectional high power dc-dc converter of [10]

20

1D 2D 3D4D

5D6D 7D 8D

1C2C 3C

4CinC oC

1L

2L

ivov

1s4s2s 3s

5s

Figure ‎1-18 High-power step down dc-dc converter of [13]

ov

1D

3D

2D

4D

2/iv

2/ivrL

c

c

c

c

1s

4s

2s

3src

oC

Figure ‎1-19 High power step-down dc-dc converter of [37]

21

1.4 Thesis Outline

The next chapters of the thesis are organized as follows:

Chapter 2 presents the structure and operation principle of the proposed converters. This

includes a modular ―step-down‖ converter for unidirectional power transfer between dc

buses, a modular ―step-up‖ converter for unidirectional power transfer between dc buses, a

modular inverting ―step-up, step-down‖ converter for unidirectional power transfer between

dc buses, and finally bidirectional power transfer converters.

Chapter 3 develops a mathematical model of the proposed converters and establishes their

basic design equations.

Chapter 4 points to some practical considerations regarding the implementation of the

proposed converters. It tackles the filter design, loss analysis, fault analysis and practical

realization issues.

Chapter 5 presents a proof of concept of proposed converters through design examples on

several power and voltage levels, and through experimental prototypes.

Chapter 6 concludes the thesis, highlights the contribution and proposes future work.

22

Chapter 2 Structure and Operation Principle

2

2.1 Introduction

In this chapter, the structure of each converter circuit is discussed. This is followed by

presentation of their operating principles at steady-state. Four converter circuits are tackled in

this thesis. They all share the same merits, they (1) depend on modular active switching network,

(2) employ soft-switching and avoid high-current chopping, (3) can be used for interconnecting

both unipolar and bipolar dc buses, (4) do not contain high-voltage capacitors, transformers or

coupled inductors, (5) offer a systematic design procedure based on closed-form mathematical

expressions. The proposed converters therefore avoid the limitations of existing circuits

discussed in the previous chapter, and are attractive for a wide range of high-power and high-

voltage applications.

The structure of the active switching network of each converter contains series identical

power modules operating synchronously. The major advantages of this structure are:

i) shortened design process, ii) lowered manufacturing, production and assembly costs through

use of standardized identical modules , and iii) enhanced system reliability through redundancy.

Soft-switching is employed for all switches. In contrast to hard-switched converters, the

proposed circuits avoid forced chopping of high currents. All active switches have self current

turn-off at zero voltage. This implies; i) lower switching losses, ii) reduced problems resulting

from electro-magnetic interference (EMI), iii) no need for active voltage sharing between

semiconductors, vi) the ability to use thyristors as the main active switches.

The structure of the proposed converters always allows unipolar and bipolar implementations

without using isolation transformers, special grounding or insulation techniques. The absence of

high-voltage active switching valves allows compact implementation using off-the-shelf

semiconductor devices. The proposed topologies avoid using direct series/parallel

interconnection of active switches and therefore do not require active-voltage sharing techniques

between semiconductors.

23

2.2 Structure of the active switching network

The Proposed converters rely on a circuit composed of a single resonant inductor together

with capacitors embedded within an active switching network. Details for the structure of each

converter circuit will be presented later in this chapter. This section presents the structure of the

active switching network shared by all proposed converters. This circuit is shown in Fig. 2-1.

The active switching network consists of identical modules connected in series. Each module

contains a low-voltage ac (non-polarized) capacitor and four identical active switches with a

reverse blocking characteristic. The forward and reverse blocking voltages for each switch equal

to the peak voltage of the low-voltage capacitors. Since capacitors always have equal voltages,

equal blocking voltages among switches is guaranteed. All modules operate synchronously by

sequential switching of S1 and S2. As a result, the active switching network is seen as a single

high voltage rotating capacitor from its terminals as shown in Fig.2-1.

By switching-on S1 (or S2 ), all low-voltage capacitors become connected in series through the

switches S1 (or S2). Turn-on of the switches always occurs at zero current as the proposed

converters operate only in the discontinuous conduction mode (DCM). DCM operation allows

only three switching possibilities shown in Fig.2-2. A resonant inductor (not shown) will play an

important role during switching. This role implies natural current commutation from the active

switching network at zero voltage. This results in self turn-off of all active switches S1 and S2.

Therefore, thyristors can be used to realize the active switches S1 and S2. Other semiconductor

devices can also be used such as, the IGCT or conventional IGBTs with series diodes or RB-

IGBTs which all have reverse blocking characteristics.

Since the active switches S1 and S2 are single quadrant switches, they allow current

conduction only in one direction indicated by the arrow (see Fig. 2-1, Fig. 2-2). This structure

prevents any short circuit scenario to happen across capacitors terminals, regardless of the

switching state. Since only discontinuous conduction mode is allowed, the switching scenarios

(a) and (c) are followed by a zero-current (or non-conduction) period shown in (b). This means

that the switching states follow the (a), (b), (c), (b), (a)… sequence. At the turn-off instants,

moving from (a) to (b) or from (c) to (b), the current commutates from the active switching

network to an external circuit naturally without forced turn-off of the switches. This feature will

be explained for each converter in more details.

24

1s

1s

2s

2s

1rc

1s

1s

2s

2s

nrc

Cell No.1

Cell No.n

ci

ci

cv*

cv

1rcv

rncv

*

cv

Figure ‎2-1 Structure of the modular active switching network

25

1s

1s

1rc

1s

1s

nrc

ci

1rc

nrc

2s

2s

2s

2s

1s

1s

1rc

1s

1s

nrc

1rcv

rncv

2s

2s

2s

2s

ci

ci

ci

(a) (b) (c)

Figure ‎2-2 Different switching schemes of the active switching network

26

2.3 The Modular Step-down Converter.

The proposed step down converter has the generic structure shown in Fig. 2-3. Generally, the

converter is fed from a bipolar input dc bus (vi+ , vi- ) and supplies a bipolar output dc bus (vo+ ,

vo- ) with lower voltage than the input bus. The input is connected to active switching buses

acting as rotating high voltage resonant capacitors (Cr+ , Cr-), as explained earlier. The structure

shown in Fig.2-3 allows bipolar or unipolar power transfer from the input buses.

In contrast to Pulse Width Modulated converters, the proposed circuit is a frequency

controlled converter. Its function is similar to the classical buck converter which can step down

the input voltage to the value of the output voltage without changing the polarity. But unlike the

classical PWM controlled buck converter, the proposed circuit doesn‘t experience forced current

chopping. Current commutation from the active switching network to the diodes occurs at zero

voltage. Also the circuit operates only in the discontinuous conduction mode (DCM) implying

zero current turn-on for the active switches and zero current turn-off for the diodes. As a result,

all semiconductor devices operate at soft-switching mode reducing the switching losses

dramatically.

For each pole, the converter contains a resonant inductor (L r+ or L r-), an integrated resonant

capacitive active switching network (C r+ or C r-) and a diode valve. Details of the operating

principle are shown in Fig. 2-4, Fig. 2-5 and Fig.2-6. For each switching cycle, the circuit

operates in six intervals shown in Fig.2-4, Fig.2-5 with the associated waveforms shown in Fig.

2-6. These intervals can be explained as follows:

a) By firing S1 a sinusoidal input current flows from 0tr to tr , in the series LC

resonant circuit. is defined as the conduction period of S1. During this interval, the

capacitors are charged and their voltages swing from pkcv to pkcv while the diodes

remain reversed biased. pkcv is the steady-state peak voltage of the capacitors. This

interval ends when the summation of the capacitor voltages in the modules reaches the

value of the input bus voltage. At this instant, the forward voltage on S1 becomes zero and

current commutates to the diodes. This interval is shown in Fig.2-4 (a).

27

b) At tr , the summation of the capacitor voltages equals to the input bus voltage and as

a result, the reverse voltage across the diodes becomes zero. At this moment, the diodes

turn on at ZVS, clamping the net capacitor voltage to pkcv . The current commutates to the

diodes and the inductor stored energy is discharged linearly into the output circuit. During

this interval, no current is drawn from the input bus while the output bus receives current

supplied from the resonant inductor. This interval is shown in Fig.2-4 (b).

c) Once the inductor is fully discharged into the output bus, diodes turn-off at zero current

blocking a voltage of vo. After the inductor discharge, both input and output currents equal

to zero. This is the last interval in the first switching half cycle. This interval is shown in

Fig. 2-4 (c).

d) The second switching half-cycle starts by firing S2. Because the inductor was fully

discharged in the previous half-cycle, S2 turn-on occurs with ZCS at the beginning of this

interval, which is shown in Fig.2-5 (d). Another sinusoidal current pulse flows through the

resonant circuit for a time period . During this period, the net capacitor voltage swings

negatively from pkcv to pkcv while the diodes remain reverse biased. This interval ends

when the summation of the capacitor voltages in the modules reaches the value of the

input bus voltage. At this instant, the current commutates to the diodes.

e) At 2/srr Tt , the summation of the capacitor voltages equals to the bus input

voltage and as a result, the reverse voltage across the diodes becomes zero. At this

moment, diodes turn on at ZVS, clamping the net capacitor voltage to pkcv . The current

commutates to the diodes and the inductor stored energy is discharged linearly into the

output circuit. During this interval, no current is drawn from the input bus while the output

bus receives current supplied from the resonant inductor. This interval is shown in Fig. 2-

5 (e).

f) As the inductor is fully discharged in the output bus, diodes turn-off at zero current

blocking a voltage of vo. After the inductor discharge, both input and output currents equal

28

to zero. This is the last interval in the second switching half cycle. This interval is shown

in Fig. 2-5 (f).

iv o

vD

ov

iv

rC

rC

ii

ii

oi

oi

rL

D

rL

Figure ‎2-3 Structure of the modular step-down converter

In contrast to hard commutation in the classical PWM buck converter, current commutation in

this topology occurs at zero voltage. This results in self turn-off of the active switches S1 , S2 at

zero voltage and soft turn-on of the diodes at zero voltage. Because the circuit only operates in

DCM, the active switches (S1 and S2) turn-on at zero current and the diodes turn-off at zero

current as well.

29

iv o

vD

ov

iv

ii

ii

oi

oi

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

iv o

vD

ov

iv

oi

oi

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

iv o

vD

ov

iv

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

(a)

(b)

(c)

-

+

+

-

+

+

-

-

-

-

+

+

Figure ‎2-4 Step-down converter during intervals a, b, c of the first switching half-cycle

30

iv o

vD

ov

iv

ii

ii

oi

oi

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

iv o

vD

ov

iv

oi

oi

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

iv o

vD

ov

iv

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

(d)

(e)

(f)

+

-

+

-

-

+

+

-

+

-

-

+

Figure ‎2-5 Step-down converter during intervals d, e, f of the second switching half-cycle

31

Figure ‎2-6 Ideal steady-state waveforms of the modular step-down converter

(b) (a) (c) (d) (e) (f) tr

0

2

srT srT

rncv

oL ii

2SrnC ii 1SrnC ii

Di

Module

cap

acit

or

volt

age

Induct

or

and o

utp

ut

curr

ent

Curr

ents

in c

apac

itors

and s

wit

ches

S1 , S

2

Dio

de

curr

ent

pkcv

pkcv

0

pkLi

pkLi

pkLi

pkDi

0

32

2.4 The Modular Step-up Converter.

The proposed step down converter also utilizes the switching network of Fig.2-1. Its generic

structure is shown in Fig. 2-7. Similar to the step-down converter discussed earlier, the step-up

converter is fed from a bipolar input dc bus (vi+ , vi- ) and supplies a bipolar output dc bus (vo+ ,

vo- ) with higher voltage than the input bus. The active switching network acts as a rotating high

voltage resonant capacitor (Cr+ , Cr-) as explained earlier. Both unipolar and bipolar power

transfer is possible between input and output dc buses.

The converter is also a frequency controlled circuit. Its function is similar to the classical

boost converter which can step up the input voltage vi to the value of the output voltage vo

without changing the polarity. But unlike the classical PWM controlled boost converter, the

proposed circuit doesn‘t experience forced current chopping during commutation and operates

only in the DCM mode. The converter shown in Fig.2-7 contains a resonant inductor

(L r+ or L r-) on each pole which is directly connected to the input dc bus. In addition, it also has

an integrated resonant capacitive active switching network (C r+ or C r-) and an output diode

valve for each pole. The operating principle, at steady-state, can be explained with the help of

Fig. 2-8, Fig. 2-9 and Fig.2-10. Similar to the step-down converter, this circuit operates in six

intervals during each switching cycle and can be explained as follows:

a) The first interval is shown in Fig.2-8 (a). By firing S1 a sinusoidal current pulse is drawn

from 0tr to tr ,in the series LC resonant circuit. The capacitors are charged

simultaneously and their voltages swing positively from pkcv to pkcv while the diodes

are reversed biased. This interval ends when the summation of the capacitor voltages in

the modules reaches the value of the output bus voltage. At this instant, the forward

voltage on S1 becomes zero and current commutates to the diodes.

b) At tr , the summation of the capacitor voltages equals to the output bus voltage and

as a result, the reverse voltage across the diodes becomes zero. At this moment, diodes

turn on at ZVS, clamping the net capacitor voltage to pkcv . The current commutates to

the diodes and the inductor stored energy is discharged linearly into the output circuit.

This interval is shown in Fig. 2-8 (b).

33

c) When the inductor is fully discharged, diodes turn-off at zero current blocking voltage of

(vo-vi). During this interval both input and output currents equal to zero. This is the last

interval in the first switching half cycle which is shown in Fig. 2-8 (c).

d) The second switching half cycle is similar to the first half-cycle and starts by firing S2.

Because the inductor has fully discharged into the previous half-cycle, S2 turn-on occurs at

ZCS at the beginning of this interval which is shown in Fig.2-9 (d). In this interval,

another sinusoidal current pulse is drawn in the resonant circuit for a time period .

During this period, net capacitor voltage swings negatively from pkcv to pkcv while the

diodes are reverse biased. This interval also ends when the summation of the capacitor

voltages in the modules reaches the value of the output bus voltage. At this instant current

commutates to the diodes.

iv o

v

D

ov

iv

rC

ii

ii

oi

oi

rL

rC

rLD

Figure ‎2-7 Structure of the modular step-up converter

34

e) At 2/Srr Tt , the summation of the capacitor voltages equals to the output bus

voltage and as a result, the reverse voltage across the diodes becomes zero. At this

moment, diodes turn on at ZVS clamping the capacitors ‗voltages to pkcv . The current

commutates to the diodes and the inductor stored energy is discharged linearly into the

output circuit. This interval is shown in Fig. 2-9 (e).

f) When the inductor is fully discharged into the output bus, diodes turn-off at zero current

blocking (vo-vi). During this interval both input and output currents equal to zero. This is

the last interval in the second switching half cycle which is shown in Fig. 2-9 (f).

In contrast to hard commutation in the classical PWM boost converter, current commutation

occurs at zero voltage. This results in natural turn-off of the active switches S1 , S2 at zero

voltage and turn-on of the diodes at zero voltage. Because the circuit only operates in DCM, the

active switches (S1 and S2) turn-on at zero current and the diodes turn-off at zero current as well.

The step-up converter will start injecting power into the output circuit, and operate in steady-

state after capacitors are charged. When the converter starts while all capacitors are discharged,

capacitors voltage build-up process occurs. This process will be referred to as the ―black-start‖

mode. During this mode, no current is injected into the output circuit. The power withdrawn

from the input bus is transferred to the capacitors to charge them. This mode can be explained

with Fig. 2-8, Fig. 2-9, Fig. 2-11 and Fig. 2-12.

Fig. 2-11 shows the terminal voltage of the active switching network (vc*) during the black-

start mode. The waveform labeled vc is the net rotating capacitor voltage shown in Fig. 2-1

which is composed of the series connection of the actual modular capacitors. During this mode,

the converter operates only in intervals (a), (c), (d), (f), (a), … shown in Fig. 2-8 and Fig. 2-9.

After each half-cycle the terminal voltage of the active switching network increases by 2 vi. This

will be discussed in details on Chapter 3 of this thesis. When vc* reaches the output voltage level

(vo), each capacitor is then charged to the voltage level vc pk shown in Fig. 2-10 and the converter

operates in steady-state as discussed earlier.

35

iv o

vD

ov

iv

ii

ii

(a)

(b)

(c)

rL D

1s

2s

nrc

1s

2s

rL

iv o

vD

ov

iv

ii

ii

oi

oi

rL D

1s

2s

nrc

1s

2s

rL

iv o

vD

ov

iv

rL D

1s

2s

nrc

1s

2s

rL

- +

+ -

-+

Figure ‎2-8 Step-up converter during intervals a, b, c of the first switching half-cycle

36

iv o

vD

ov

iv

ii

ii

(d)

(e)

(f)

rL D

1s

2s

nrc

1s

2s

rL

iv o

vD

ov

iv

ii

ii

oi

oi

rL D

1s

2s

nrc

1s

2s

rL

iv o

vD

ov

iv

rL D

1s

2s

nrc

1s

2s

rL

+ -

- +

+-

Figure ‎2-9 Step-up converter during intervals d, e, f of the second switching half-cycle

37

Figure ‎2-10 Ideal steady-state waveforms of the modular step-up converter

tr

srT

2

srT

0 (e) (f) (d) (c) (b) (a)

Dio

de

curr

ent

Curr

ents

in c

apac

itors

and s

wit

ches

S1 , S

2

Induct

or

and o

utp

ut

curr

ent

Module

cap

acit

or

volt

age

Di

2SrnC ii 1SrnC ii

rncv

pkcv

pkcv

pkLi

pkLi

pkDi

pkLi

pkDi

pkDi

0

0

iL ii

38

Figure ‎2-11 Capacitor voltage build-up process during the step-up converter black-start

Figure ‎2-12 Inductor and output currents of the step-up converter during the black-start

process

cv

*

cv

oi

ii

pkLi

ov

ov

39

2.5 The Modular Inverting Converter

The proposed switching network of Fig.2-1 can also be utilized to make a polarity inverting

converter, similar in function to the classical buck-boost PWM converter. The generic structure

of this circuit is shown in Fig. 2-13. Similar to the step-down and step-up converters discussed

earlier, the inverting converter is fed from a bipolar input dc bus (vi+ , vi- ) and supplies a bipolar

output dc bus (vo+ , vo- ) with higher or lower voltage than the input bus but with reversed

polarity. In case of unipolar realization, the input and output buses will have different polarity

and voltage levels. In case of bipolar realization, the converter will share the same function of

either the step-down or step-up circuits discussed earlier.

Similar to previous circuits discussed earlier, the polarity inverting converter is also a

frequency controlled circuit performing power transfer between two dc buses with different

voltages and polarities without current chopping. It enjoys the same soft current commutation

feature and operates only in the DCM mode. For bipolar realization, the circuit needs two active

switching buses (one for each pole), but can utilize only one resonant inductor. However, the

converter shown in Fig.2-13 contains two inductors to allow single pole power transfer, if

needed. The steady-state operating principle can be explained with the help of Fig. 2-14,

Fig. 2-15. Corresponding waveforms during step-down mode and step-up mode are shown in

Fig. 2-17, Fig.2-18 respectively. This circuit also operates in six intervals during each switching

cycle as follows:

a) By firing S1 a sinusoidal current pulse is drawn from 0tr to tr, in the series LC

resonant circuit. The capacitors are charged and their voltages swing positively from

pkcv to pkcv while the diodes are reversed biased. This interval ends when the summation

of the capacitor voltages in the modules reach the value of (vo+vi). At this instant, the

forward voltage on S1 becomes zero and current commutates to the diodes. This interval is

shown in Fig.2-15 (a).

b) At tr, the summation of the capacitor voltages equals (vo+vi) and as a result, the

reverse voltage across the diodes becomes zero. At this moment, diodes turn on at ZVS

clamping the net capacitor voltage to pkcv . The current commutates to the diodes and the

40

inductor stored energy is discharged linearly into the output circuit. During this interval,

no current is drawn from the input bus while the output bus receives current supplied from

the resonant inductor. This interval is shown in Fig.2-15 (b).

c) When the inductor is fully discharged into the output bus, diodes turn-off at zero current

blocking vo. During this interval both input and output currents equal to zero. This is the

last interval in the first switching half cycle which is shown in Fig. 2-15 (c).

d) The second switching half cycle starts by firing S2. Because the inductor has fully

discharged during the previous half-cycle, S2 has turned on at ZCS at the beginning of this

interval which is shown in Fig.2-16 (d). In this interval, another sinusoidal current pulse is

drawn in the series LC resonant circuit for a time period and the net capacitor voltage

swings negatively from pkcv to

pkcv while the diodes remain reverse biased. This interval

ends when the summation of the capacitor voltages in the modules reaches (vo+vi). At this

instant, the current commutates to the diodes.

iv

ov

ov

iv

rL

rC

rC

ii

ii

oi

rL

D

D

oi

Figure ‎2-13 Structure of the modular inverting converter

41

e) At 2/srr

Tt , the summation of the capacitor voltages equals (vo+vi) and as a

result, the reverse voltage across the diodes becomes zero. At this moment, diodes turn on

at ZVS clamping the capacitors ‗voltages to - pkcv . The current commutates to the diodes

and the inductor stored energy is discharged linearly in the output circuit. During this

interval, no current is drawn from the input bus while the output bus receives current

supplied from the resonant inductor. This interval is shown in Fig. 2-16 (e).

f) As the inductor is fully discharged in the output bus, diodes turn-off at zero current.

During this interval both input and output currents equal to zero. This is the last interval in

the second switching half cycle which is shown in Fig. 2-16 (f).

In contrast to hard commutation in the classical PWM buck-boost converter, current

commutation occurs at zero voltage. This results in self turn-off of the active switches S1 , S2 at

zero voltage and soft turn-on of the diodes at zero voltage. Because the circuit only operates in

DCM, the active switches (S1 and S2) turn-on at zero current and the diodes turn-off at zero

current as well. In the step-up mode, the converter will start injecting power into the output

circuit, and operate in steady-state after capacitors are charged. This also similar to the step-up

converter discussed earlier. When the converter starts while all capacitors are discharged,

capacitors voltage build-up process occurs as shown in Fig 2-14.

Figure ‎2-14 Capacitor voltage build-up of the inverting converter in step-up mode

cv *

cv

oi vv

oi vv

42

iv

ov

D

ov

iv

ii

ii

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

(a)

(b)

(c)

iv

ov

D

ov

iv

oi

oi

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

iv

ov

D

ov

iv

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

+

-

-

+

+

-

-+

-

+

+

-

Figure ‎2-15 Inverting converter during intervals a, b, c of the first switching half-cycle

43

iv

ov

D

ov

iv

ii

ii

rL

D

rL

1s2s

nrc

1s

2s1s

1s 2s

2s

nrc

(d)

(e)

(f)

iv

ov

D

ov

iv

oi

oi

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

iv

ov

D

ov

iv

rL

D

rL

1s

2s

nrc

1s

2s1s

1s 2s

2s

nrc

-

+

+

-

+

-

+

-

-

-

+

+

Figure ‎2-16 Inverting converter during intervals d, e, f of the second switching half-cycle

44

Figure ‎2-17 Ideal steady-state waveforms of the inverting converter during step-down

(b) (a) (c) (d) (e) (f) tr

0

2

srT srT

rncv

Li

2SrnC ii 1SrnC ii

Di

Module

cap

acit

or

volt

age

Induct

or

and o

utp

ut

curr

ent

Curr

ents

in c

apac

itors

and s

wit

ches

S1 , S

2

Dio

de

curr

ent

pkcv

pkcv

0

pkLi

pkLi

pkLi

pkDi

0

45

Figure ‎2-18 Ideal steady-state waveforms of the inverting converter during step-up

tr

srT

2

srT 0

(e) (f) (d) (c) (b) (a)

Dio

de

curr

ent

Curr

ents

in c

apac

itors

and s

wit

ches

S1 , S

2

Induct

or

and o

utp

ut

curr

ent

Module

cap

acit

or

volt

age

Di

2SrnC ii 1SrnC ii

oL ii

rncv

pkcv

pkcv

pkLi

pkLi

pkDi

pkLi

pkDi

pkDi

0

46

2.6 Modular Bidirectional Converters

A bidirectional dc-dc converter, also referred to as a ―dc transformer‖ allows bidirectional power

transfer between two dc buses with different voltage levels. This feature can be obtained by a

hybrid connection of a step-up and a step-down converter. Fig. 2-19 shows the structure of this

converter. In this figure it is assumed that (vi+ , vi-) is the dc bus with lower voltage than the (vo+ ,

vo-). The converter contains two bipolar separate sub-converters, namely: a modular step-up

converter and a modular step-down converter. The step-up subconverter consists of the resonant

inductors (Lr up+ , Lr up-), the active switching networks (Cr up+ ,Cr up-) and the diode valves (Dup+

,Dup-). The step-down subconverter consists of the resonant inductors (Lr dwn+ ,

Lr dwn-), the active switching networks (Cr dwn+ ,Cr dwn-) and the diode valves (Ddwn+ ,Ddwn-). Each

converter can operate independently according to the operating principles described earlier in

this chapter.

LVv HVv

upD

HVvLVv

uprC

uprL

uprC

uprLupD

dwnrC

dwnrC

dwnD

dwnD

dwnrL

dwnrL

Figure ‎2-19 Structure of the modular bidirectional converter

47

The structure of Fig. 2-19 uses two separate inductors; one for the step-up function and one

for the step-down function. Alternatively, it is also possible to use one inductor for both

functions on each pole. In this case, the structure of Fig.2-19 can be simplified as shown in

Fig.2-20. In this structure, only one converter operates at a given time according to the operating

principle described earlier in this chapter. This converter bears resemblance to the 2-quadranct

chopper circuit.

LVv HVv

upD

HVvLVv

uprC

dwnuprL /

uprC

dwnuprL /

upD

dwnrC

dwnrC

dwnD

dwnD

Figure ‎2-20 Structure of the single-inductor modular bidirectional converter

48

Bidirectional converters can also be made from hybrid connection of two modular inverting

converters. Fig. 2-21 shows the structure of two modular inverting converters connected in anti-

parallel connection with separate inductors to make a bidirectional inverting converter. Both

step-up and step-down operations operate independently for the converter of Fig.2-21. It is also

possible to assemble the same converter with a single inductor for both step-up and step-down

operations and for both poles. This is shown in Fig.2-22. In this case only one converter operates

at a given time.

upD

uprC

uprC

upD

dwnD

dwnD

uprL

dwnrC

dwnrC

dwnrL

LVv

LVvHVv

HVv

Figure ‎2-21 Structure of the inverting modular bidirectional converter

49

LVv

HVv

HVv

LVv

upD

uprC

uprC

upD

dwnD

dwnD

rL

dwnrC

dwnrC

Figure ‎2-22 Structure of the single-inductor inverting modular bidirectional converter

50

2.7 Summary

In this chapter, the basic structure and operating principle of the proposed converters were

presented. Resemblance between the classical dc-dc converters (buck, boost, buck-boost) and the

proposed circuits can be observed. But, unlike classical circuits, the proposed converters do not

require forced current chopping. Instead, all circuits enjoy natural current commutation at zero

voltage.

The proposed converters utilize modular active switching networks composed of low-voltage

single-quadrant switches and low-voltage capacitors. High voltage capacitor banks are not

needed in the proposed topologies. All capacitors are enclosed inside their modules and require

no special short circuit protection.

The proposed converters are scalable and allow redundant modules to be added. These

structural features result in suitability for a wide range of high-power applications at high

reliability and low cost.

It is concluded that despite the different functions of the various proposed converters, their

operating principles show great similarity. This can be observed when comparing the six

conduction intervals of the converters of section 2.3, 2.4 and 2.5. For the inverting converter, we

conclude that it‘s step-up and step-down waveforms are similar to the non-inverting step-up and

step-down circuits. A basic difference, however, is the peak voltage swing of the capacitors and

hence, the number of required modules.

The observed resemblance in the operating principles of the converters allows unified

mathematical analysis, design procedure, and control to be conducted in the subsequent chapters.

51

Chapter 3 Converter Modeling and Design

3

3.1 Introduction

After presenting the operating principles for the converters proposed in the previous chapter, this

chapter studies these converters analytically. This is done by performing steady-state

mathematical modeling. The objective is to derive a set of closed form mathematical expressions

describing the behavior of each converter circuit. These expressions are primarily useful to

design the converters and select their components.

Before starting the design process, identifying the function of the converter (step-up, step-

down, etc.), and the desired power rating is essential. This is followed by determining the

operating voltage stepping ratio. Given the converter‘s power, and its terminal voltages, the

design process will result in:

1. Determining the value of the resonant capacitors in the active switching network.

2. Determine the value of the resonant inductor to guarantee DCM operation.

3. Choosing proper ratings of the power semiconductor devices.

To tackle the above mentioned points, this chapter starts by studying the energy transferred

through each converter following each switching pulse. Then, the voltage and current relations in

the resonant elements are studied analytically. Finally, the current and voltage requirements of

the power semiconductor devices are studied.

Secondary design considerations will be discussed in the next chapters. These considerations

include semiconductors power losses, design of the filtering capacitors and the effects of the

circuit non-idealities.

52

3.2 Assumptions

To model the proposed converters, ideal components will be assumed. This condition will be

relaxed in the next chapter, taking into consideration the non-idealities associated with each

component individually. Unless otherwise stated, the discussion in this chapter assumes the

following:

1. All semiconductor devices have zero conduction losses (i.e. no voltage drop during the

on-state intervals).

2. All semiconductor devices have ideal switching behavior with zero turn-on and turn-off

switching losses.

3. Stray inductances and capacitances associated with bus-bars are negligible.

4. Resonant capacitors are identical and lossless.

5. Resonant inductors are identical and lossless.

6. Input and output dc buses have constant voltage with negligible dynamics.

In the previous chapter, the structures proposed for all converter circuits assume double

polarity multi-cell realization as a general case. It was shown that each converter can also

connect single polarity buses without special insulation techniques maintaining a common

ground return for both input and output dc buses. Throughout this chapter, single polarity single

cell realization of all converter circuits will be assumed. Without loss of generality, this

assumption helps reduce the number of variables in the derived equations. The single polarity

topologies are shown in Fig. 3-1. Analytically, this use of single polarity implies the following

relations to the topologies presented in the previous chapter:

iii vvv (3.1)

ooo vvv (3.2)

rrr LLL (3.3)

53

rrr CCC (3.4)

N

n rn

rr

c

CC

1

1

1

(3.5)

where N is the number of series interconnected converter cells.

ivov

1s

1s

2s

2s

rL

cv

*

cv

oiii

D

ivov

1s

1s2s

2s

rC

rLcv

*

cv

oiii

D

ivov

1s

1s2s

2s

rL

cv

*

cv

oiii

D

(c)

(b)

(a)

rC

rC

Figure ‎3-1 Simplified structure of (a) step-down, (b) step-up and (c) inverting converters

54

3.3 Resonant capacitors design

The fundamental relations describing the behavior of the proposed converter are the energy and

power relations. This section derives these relations for the step-up, step-down and inverting

converters. Since the bidirectional converter represents a hybrid connection between step-down

and step-up converters, the same relations apply to it.

3.3.1 Step-down converter

In Section 2.3, the structure and operating principle of the step-down converter were presented

with the help of the ideal steady-state waveforms of Fig.2-6. From Fig. 2-4 and Fig.2-5, we note

that each switching cycle extracts two current pulses from the input bus, the energy associated

with each current pulse is:

2/

0

*

Ts

iii dtivw (3.6)

This input current pulse passes through both the input and output sources and flows into the LC

series resonant circuit. This describes intervals (a) and (d) shown in Fig. 2-4 to Fig. 2-6. Thus

equation (3.6) can be re-written as:

2/

0

*

Ts

cii dtivw (3.7)

This current pulse charges (or discharges) the resonant capacitors causing voltage swing between

vc = vc pk and vc = -vc pk , where vc pk = vi . Thus equation (3.7) yields:

i

i

v

v

ircrii vCdvCvw 2* 2 (3.8)

And the input energy associated with the whole switching cycle becomes:

Ts

iriii

i

vCdtivw0

24 (3.9)

The average input power can then be described by the relation (3.10) as:

55

24 isr

s

ii vfC

T

wP (3.10)

where fs is the switching frequency of the switches S1 and S2. Finally, the design equation of the

resonant capacitor is:

24 is

ir

vf

PC (3.11)

3.3.2 Step-up converter

The structure and operating principle of the step-up converter were presented in Section 2.4. The

ideal steady-state waveforms were shown in Fig.2-10. Fig.2-8 and Fig.2-9 show that each

switching cycle withdraws two current pulses from the input source. The energy associated with

each current pulse is expressed as:

2/

/

/

0

2/

0

*

Ts

iiii

Ts

iii

o

o

dtivdtivdtivw

(3.12)

In contrast to step-down converter, the input source supplies current in two stages, the first is

before the conduction angle while the second is after it. The first stage of the input current

pulse passes from the input bus supplying the LC series resonant circuit during the

interval ot /0 . This interval is shown in Fig. 2-8 (a). The second stage of the input

current pulse flows from the input bus through the resonant inductor supplying the output bus

during the interval 2// so Tt which is shown in Fig. 2-8 (b). Thus equation (3.12) can

be re-written as:

2/

/

/

0

*

Ts

oicii

o

o

dtivdtivw

(3.13)

Where ic is the resonant capacitor current and io is the output current.

56

Similar to the step-down converter, the first stage of the input current pulse charges/

discharges the resonant capacitors causing its voltage to swing between vc = vc pk and vc = -vc pk ,

where vc pk = vo in this case. Thus equation (3.13) yields:

2/

0

2/

/

* 2

Ts

oioir

Ts

oi

v

v

crii dtivvvCdtivdvCvw

o

o

o

(3.14)

The energy contained in the output energy pulse is expressed in (3.15).

2/

0

*

Ts

ooo dtivw (3.15)

Assuming a lossless converter, *

iw can be equated to *

ow leading to:

io

roii

vv

Cvvw

2* 2

(3.16)

Thus the output energy per full cycle is:

io

roii

vv

Cvvw

24 (3.17)

and the average input power expression would be

io

sroii

vv

fCvvP

24 (3.18)

Finally, the capacitor design equation for the step-up converter is:

soi

ioir

fvv

vvPC

24

(3.19)

57

3.3.3 Inverting converter

The inverting converter was discussed in Section 2.5, and its operating principle was explained

with the help of Fig.2-15, Fig.2-16. Similar to the step-up and step-down converters, each

switching cycle withdraws two current pulses from the input bus. The energy associated with

each current pulse is given by the expressions of (3.6) and (3.7). This input current pulse passes

from the input bus and flows into the LC series resonant circuit. This situation describes intervals

(a) and (d) shown in Fig. 2-15 and Fig. 2-16. This current pulse charges the resonant capacitors

causing voltage swing between vc = vc pk and vc = -vc pk , where vc pk = vi + vo. Thus, the input

energy associated with each half-cycle is:

)(

)(

2

2/

0

* 2oi

oi

vv

vv

oiircri

Ts

iii vvvCdvCvdtivw (3.20)

And the input energy associated with the full switching cycle becomes:

oiir

Ts

iii vvvCdtivw 2

0

4 (3.21)

while the average input power would be:

oiisr

s

ii vvvfC

T

wP 24 (3.22)

and the capacitor design equation for the inverting converter would be:

oiis

ir

vvvf

PC

24 (3.23)

58

3.3.4 Comments

The analysis presented in sections 3.3.1-3.3.3 developed mathematical expressions for the energy

and power of each converter circuit. From these expressions, the primary design equations of the

resonant capacitors were presented. In contrast to classical circuits, the proposed converters show

different behaviour as follows:

For a given converter transferring power between input and output dc sources,

expressions (3.10), (3.18) and (3.22) show that the input power is controlled only through

the switching frequency fs .The relation between the steady state power and the switching

frequency is linear.

The power and energy relations do not contain the resonant inductance. Therefore, for a

given switching frequency the value of the resonant inductor doesn‘t influence the power

supplied by the converter, provided that DCM operation is maintained. Section 3.6 will

tackle the inductor sizing in detail.

The value of the resonant capacitor is determined based on the required power and

voltage rating of a converter, at a specified maximum switching frequency.

The peak voltage of the resonant capacitors is: vi for the step down converters, vo for the

step-up converter and vi + vo for the inverting converter. In modular realization, this

voltage is shared equally between all capacitors in the active network cells. All active

switches of each cell will have a forward and reverse blocking voltage.

To choose the current ratings of the semiconductor devices, and the value of the resonant

inductor, current and voltage relations of each converter circuit will be derived in the next

section.

59

3.4 Current and voltage in resonant elements

To understand the behavior of the proposed converters and how to determine the value of the

resonant inductor and the semiconductor ratings, it is essential to derive the mathematical

relations governing voltages and currents in the resonant elements. The inductor should

guarantee DCM operation up to the maximum power rating of the converter. For these

converters, DCM operation is a special case of CCM operation. For this reason, CCM operation

will be assumed in this section for the sake of deriving the required mathematical relations in

general forms. Fig. 3-2 shows the basic continuous conduction waveforms for step-down

operation while Fig 3-3 shows the same waveforms for step-up operation.

Figure ‎3-2 Basic waveforms for step-down operation during continuous conduction

cv

cov

ii

Li

oI

tr

Volt

age

wav

eform

of

the

reso

nan

t ca

pac

itor

Curr

ent

wav

eform

of

the

reso

nan

t in

duct

or

pkcv

pkcv

0

0 2/sT

pkLi

60

Figure ‎3-3 Basic waveforms for step-up operation during continuous conduction

For all converters proposed operating in the interval tr0 , the LC resonant elements are

connected in series together with an external voltage source exv as shown in Fig. 3-4. This

external source is (vi – vo) for the step down converter, (vi ) for the step-up and inverting

converters. This remains for a duration tr . The general solution to this second order

circuit is:

ttCL

vvtIti rr

rr

coexrorL 0,sin

/cos

(3.24)

tdt

diLvtv r

Lrexrc 0, (3.25)

where ocv is the initial voltage of the capacitor and oI is the initial current of the inductor.

tr

ii

Li

oI

2/sT

cv

Volt

age

wav

eform

of

the

reso

nan

t ca

pac

itor

Curr

ent

wav

eform

of

the

reso

nan

t in

duct

or

pkLi

pkcv

pkcv

0

0

61

exvrC

oI

rL

+

-cov

0t

Figure ‎3-4 Equivalent circuit of the converters when the active switches are conducting

For each of the proposed converters, (3.24), (3.25) yield the following:

For the step-down converter:

ttCL

vvtIti rr

rr

oirorL 0sin

/

2cos (3.26)

ttvvtCLIvvtv rroirrrooirc 0cos2sin/ (3.27)

For the step-up converter :

ttCL

vvtIti rr

rr

oirorL 0sin

/cos (3.28)

ttvvtCLIvtv rroirrroirc 0cossin/ (3.29)

For the inverting converter :

ttCL

vvtIti rr

rr

oirorL 0sin

/

2cos (3.30)

ttvvtCLIvtv rroirrroirc 0cos2sin/ (3.31)

62

where tr0 represents intervals (a) in Fig. 2-3, Fig. 2-8, Fig. 2-15. Similar relations hold

for the intervals (d).

The inductor discharge equations apply after the swing equations from 2/sr Tt which

represents intervals (b) in Fig. 2-3, Fig.2-8, Fig. 2-15. Similar relations applies for interval

srs TtT 2/ . The inductor discharge equations are as follows:


2/sin/

2cos sr

rr

o

rr

oiorL Ttt

L

v

CL

vvIti

(3.32)

irc vtv

2/sr Tt (3.33)

For the step-up converter:

2/sin/

cos sr

rr

oi

rr

oiorL Ttt

L

vv

CL

vvIti

(3.34)

orc vtv

2/sr Tt (3.35)

For the inverting converter:

2/sin/

2cos sr

rr

o

rr

oiorL Ttt

L

v

CL

vvIti

(3.36)

oirc vvtv

2/sr Tt (3.37)

63

3.5 The conduction angle

In order to design the resonant inductors, the conduction angle needs to be calculated. This can

be done by equating (3.27) and (3.33) for the step-down converter, (3.29) and (3.35) for the step-

up converter, (3.31) and (3.37) for the inverting converter. At DCM (Io=0), this yields the

following:


io

o

vv

v

2cos 1 (3.38)


io

oi

vv

vv1cos (3.39)


io

o

vv

v

2cos 1 (3.40)

From the above relations, we note that all proposed converters operate at oo 18090 .

For the inverting converter, the step-down operation occur at oo 47.10990 , while the step-

up operation occur at oo 18047.109 . The conduction angle is an internal un-controlled

variable depending only on the input and output voltages. Fig. 3-5, Fig. 3-6, Fig. 3-7 show the

variation of the conduction angle with the voltage gain (vo / vi) for the step-down, step-up and

inverting converters respectively.

64

Figure ‎3-5 The voltage gain vs. the conduction angle for the step-down converter

Figure ‎3-6 The voltage gain vs. the conduction angle for the step-up converter

Figure ‎3-7 The voltage gain vs. the conduction angle for the inverting converter

Conduct

ion a

ngle

(d

eg.)

C

onduct

ion a

ngle

(d

eg.)

Voltage gain (vo / vi )



Conduct

ion a

ngle

(d

eg.)

65

3.6 Resonant inductor sizing

The value of the resonant inductor is chosen to maintain discontinuous operation for rated power

at maximum switching frequency. Equations (3.32), (3.34) and (3.36) are used by applying the

following conditions:

0oI

0Li at 2

sTt

This implies operating at the boundary between DCM and CCM. It yields the following:


02

1sin

/

2

rr

sr

o

rr

oi CLfL

v

CL

vv (3.41)


02

1sin

/

rr

sr

oi

rr

oi CLfL

vv

CL

vv (3.42)


02

1sin

/

2

rr

sr

o

rr

oi CLfL

v

CL

vv (3.43)

By substituting the value of the conduction angle from (3.38)-(3.40), equations (3.41)-(3.43)

are solved to give the value of the inductor that guarantees operation at the boundary between

DCM and CCM at maximum switching frequency.

66

3.7 Semiconductors current ratings

The inductor current relations of (3.26), (3.28) and (3.30) can be used to determine the peak

current in the active switches S1, S2 and its maximum rate of change at the turn-on instant. By

substituting for the conduction angle value from (3.38), (3.39) and (3.40), the diodes‘ peak

currents can also be determined. Finally, the diode current rate of change at its turn-off instant

can be determined from (3.33), (3.35) and (3.37). All these relations, during discontinuous

conduction mode, can be summarized as follows:


rr

oipkS

CL

vvi

/

2 (3.44)

r

oion

S

L

vv

dt

di

2| max (3.45)

sin/

2

rr

oipkD

CL

vvi

(3.46)

r

ooff

D

L

v

dt

dimax| (3.47)


rr

oipkS

CL

vvi

/

(3.48)

r

oion

S

L

vv

dt

di max| (3.49)

sin/ rr

oipkD

CL

vvi

(3.50)

r

oioff

D

L

vv

dt

di max| (3.51)

67


rr

oipkS

CL

vvi

/

2 (3.52)

r

oion

S

L

vv

dt

di

2| max (3.53)

sin/

2

rr

oipkD

CL

vvi

(3.54)

r

ooff

D

L

v

dt

dimax| (3.55)

The average current in the active switches and diodes for all converters can be expressed as:

cos1 rrspkSavS CLfii (3.56)

max

2

|offD

spkD

avD

dt

di

fii

(3.57)

The relations (3.44) to (3.57) allow the selection of proper semiconductor current ratings and

the calculation of switching losses associated with them. The voltage rating of the active

switches (S1, S2) will be discussed in the next section. Finally, it should be noted that the

switching losses associated with turning-on and turning-off the active switches (S1, S2) are

negligible as the turn-on occurs at ZCS, due to DCM operation, and the turn-off occurs at zero-

voltage. The stray inductance will limit the rate of change of the turn-on current of the diodes

and the turn-off current of the active switches (S1, S2). This will be discussed in the next chapter

in greater detail.

68

3.8 Semiconductors voltage ratings

This section complements the previous section, by studying the current and voltage waveforms

of the power semiconductor devices. This is useful in order to quantify the losses and specify the

suitable devices accordingly. Fig. 3-8 shows the voltage and current waveforms of the switches

and diodes, for the step-down converter and for the inverting converter operating in the step-

down mode. Fig. 3-9 shows the same waveforms for the step-up converter and for the inverting

converter operating in the step-up mode.

By examining the current and voltage waveforms of the devices, we note that each active

switch starts conducting at zero current following a sinusoidal curve peaking at iL pk. Section 3.7

gives the value of the maximum current rate of change and its peak. Then the switch current

naturally drops to zero and the current commutates to the diode abruptly. The switch voltage and

the diode voltage at the commutation instant equal to zero. We refer to this as zero voltage

commutation. After commutation, the diode current decreases linearly with a rate of change

given in section 3.7 for each converter. The diode turns off at zero current blocking a voltage

vD off. From the figures we note that the switches are required to have a peak forward blocking

voltage vs f with a rate of rise in the off-state dvs /dt|off and peak reverse blocking voltage vs r,

while the diode would be required to have to turn off at vD off and withstand a peak blocking

voltage of vD pk. Quantifying these values is important to select proper devices. With reference to

Fig. 3-8 and Fig. 3-9, and the capacitor voltage equations of section 3.4, the semiconductor

voltage ratings can be expressed as follows:


ipkcrsfs vvvv (3.58)

rr

oioff

s

CLN

vv

dt

dv

2| max (3.59)

ooffD vv (3.60)

ipkD vv 2 (3.61)

69


opkcrsfs vvvv (3.62)

rr

oioff

s

CLN

vv

dt

dv max| (3.63)

iooffD vvv (3.64)

opkD vv 2 (3.65)


oipkcrsfs vvvvv (3.66)

rr

oioff

s

CLN

vv

dt

dv

2| max (3.67)

ooffD vv (3.68)

oipkD vvv 22 (3.69)

70

Figure ‎3-8 Voltage and current waveforms of the switches and diodes during step-down

operation

Curr

ent

wav

eform

s of

the

swit

ches

and d

iodes

V

olt

age

wav

eform

s of

the

swit

ches

V

olt

age

wav

eform

of

the

dio

de

offDv

pkcv

pkLi

pkcv

0

2Si

ON

S 2 tr

1Si

Di

1Sv 2Sv

Dv

0offSv

0

pkDv

ON

D

ON

S1 ON

D

0 2/sr T sr T

offft offrt

0tr

71

Figure ‎3-9 Voltage and current waveforms of the switches and diodes during step-down

operation

Curr

ent

wav

eform

s of

the

swit

ches

and d

iodes

V

olt

age

wav

eform

s of

the

swit

ches

V

olt

age

wav

eform

of

the

dio

de

offDv

pkcv

pkLi

pkcv

0

2Si

ON

S 2 tr

1Si

Di

1Sv 2Sv

Dv

0offSv

0

pkDv

ON

D

ON

S1 ON

D

0 2/sr T sr T

offft offrt

0tr

72

3.9 Summary

In this chapter, the proposed converters have been analytically studied and the basic design

equations have been derived. A fundamental feature of the proposed converters is the linear

relationship between the power and the switching frequency. The value of the resonant capacitor

is specified by identifying the power, voltage and frequency ratings of each converter.

The converters operate only in DCM and the only control variable is the switching frequency.

The conduction angle is an uncontrolled internal variable depending on the terminal voltages of

the converter. This is a major difference between the proposed converters and the classical buck,

boost and buck-boost topologies. The conduction angle is found to vary nonlinearly with the

voltage stepping ratio.

The value of the resonant inductor is chosen to guarantee discontinuous operation at

maximum power and frequency ratings of the converters. The semiconductor current and voltage

ratings have been identified analytically. Table 3-1 shows a summary of the basic design

parameters discussed in this chapter.

73

Parameter Step-down converter Step-up converter Inverting converter

rC 24 is

i

vf

P

soi

ioi

fvv

vvP24

oiis

i

vvvf

P

24

io

o

vv

v

2cos 1

oi

oi

vv

vv1cos

io

o

vv

v

2cos 1

rL 02

1sin

/

2

rr

sr

o

rr

oi CLfL

v

CL

vv 02

1sin

/

rr

sr

oi

rr

oi CLfL

vv

CL

vv 02

1sin

/

2

rr

sr

o

rr

oi CLfL

v

CL

vv

avSi

cos1rrspkS CLfi

pkSi rr

oi

CL

vv

/

2

rr

oi

CL

vv

/

rr

oi

CL

vv

/

2

max|onS

dt

di

r

oi

L

vv 2

r

oi

L

vv

r

oi

L

vv 2

pkcrsfs vvv

iv

ov

oi vv

max|offs

dt

dv

rr

oi

CLN

vv 2

rr

oi

CLN

vv

rr

oi

CLN

vv 2

avDi

max

2 |/ offD

spkDavDdt

difii

pkDi sin/

2

rr

oi

CL

vv sin

/ rr

oi

CL

vv sin

/ rr

oi

CL

vv

max|offD

dt

di

r

o

L

v

r

oi

L

vv

r

o

L

v

pkDv

iv2

ov2

oi vv 22

Table ‎3-1 Summary of basic design parameters derived in chapter 3

74

Chapter 4 Practical Aspects

4

4.1 Introduction

Having presented the structure and performed basic mathematical analysis of the proposed

converters in the previous chapters, this chapter discusses practical considerations regarding

implementing the proposed converters to interconnect dc buses. The discussion presented in the

previous chapters was theoretical containing numerous ideal assumptions. This chapter bridges

the gap between theoretical discussions and the practical implementations presented in chapter 5.

This chapter starts by studying the impact of interconnecting dc buses with the proposed

converters on network fault propagation. In this context, it is important to understand whether a

fault at one converter terminal will be supplied from the other terminal, through the converter,

and whether this fault could result in shoot-through modes of the active switching networks. The

switching and conduction losses of the semiconductor devices are also studied in this chapter,

not only for the benefit of estimating the semiconductor losses of the converters, but also to

facilitate engineering of the thermal circuit.

Since the input and output power of the proposed topologies are pulsed, filtering capacitors

are added to the converters‘ terminals. Section 4.4 presents the design equations of the filtering

capacitors. In section 4.5, the black-start mode during the step-up operation is studied in order to

derive an expression for the minimum black-start time. Section 4.6 studies the effect of the

equivalent series resistance (ESR) on limiting the step-up voltage ratio. Section 4.7 studies the

effect of the stray inductance on the operation of the proposed converters. In section 4.8, the

minimum thyristor turn-of time is studied as it limits the maximum switching frequency. The

chapter concludes by presenting systematic design steps for the proposed converters and the

design trade-offs, taking into consideration the discussed practical aspects.

75

4.2 Fault propagation

This section studies the effect of interconnecting dc buses, using the proposed converters, on the

fault propagation among these buses. It is important to understand whether a fault at one dc bus

will be fed from the other dc bus, through the converter, and whether this fault could result in

shoot-through modes in the active switching networks. The worst-case scenario of having a zero-

impedance fault at the terminals of the converter will be considered. Fig. 4-1 shows a redraw of

the simplified topologies of Fig.3-1, having a short circuit at the input terminals (vi = 0). Fig. 4-3

show the same topologies having a short circuit at the output terminals (vo = 0).

4.2.1 Input terminal faults

Since the step-down, step-up and inverting converters only allow unidirectional power flow,

from the input source to the output source (as shown in Fig. 3-1), a fault on the input side will

not be fed from the output side.

Fig.4-1 shows the converters during the first switching interval while S1 is closed. Since S1

allows current to flow only in the direction indicated by the arrow, the input side fault current

will be blocked by S1 in case of the step-down converter (Fig. 4-1 a). For the step-up converter

(Fig. 4-1 b), the fault current will be blocked by the output diode valve D. The same applies to

the inverting converter (Fig. 4-1 c), where the fault current is also blocked by the diode. This

scenario is valid if the fault occurs during any of the other switching intervals.

From the above discussion, we conclude that the fault current at the input terminals of the

converters will not be fed from the output bus. This conclusion remains valid in case of

symmetrical or asymmetrical faults of bipolar converters.

It should be noted, however, that in case of the inverting converter (Fig. 4-1 c), the input fault

current will be fed from the stored energy of the resonant LC circuit. This is demonstrated in

Fig.4-2. If the firing signals are not stopped, each switching instant will allow the faulted

terminals to be supplied by discontinuous current pulses having half-sinusoid waveforms

described by:

76

tCL

vti r

rr

corL sin

/

(4.1)

where vco is the initial capacitor voltage at the beginning of each switching instant which equals

(-vi – vo) for the first pulse and (-vo) at steady-state. Equation (4.1) shows that this current will

have lower peak current than nominal current given by (3.53), as shown in Fig.4-2. This current

can simply be suppressed by stopping the firing signals.

4.2.2 Output terminal faults

4.2.2.1 Step down converter

In case of faults at the output side, the behavior of the converters varies. Fig.4-3 (a) shows a

fault at the output terminals of a step-down converter while S1 is closed. This fault current is

supplied from the input bus through the resonant LC circuit. If the fault occurs before S1 closes,

upon closing the switch the initial fault current pulse equals to the inductor current and is

described by:

tCL

vti r

rr

irL sin

/

2 (4.2)

Equation (4.2) only describes the first pulse of the fault current and shows that it will have

slightly higher peak current than nominal current given by (3.45); as described in Fig.4.4. It is

important to note that this current will commutate from S1 to D when the capacitor voltage is

charged to the value of the input voltage vi. The capacitor voltage will remain charged to vi after

the current commutation, therefore the current of the switch S1 will naturally drop to zero. As a

result, no shoot-through occurs to S1 after the fault instant. This is well demonstrated in Fig.4-4.

The fault current will remain circulating in the output circuit through the diode but will not be

fed from the input bus.

77

ov

1s

1s

2s

2s

rL

faulti

D

ov

1s

1s2s

2s

rC

rL

faulti D

ov

1s

1s2s

2s

rLfaulti

D

(c)

(b)

(a)

rC

rC

-

+

+-

-

+

Figure ‎4-1 Zero impedance input fault condition for the (a) step down, (b) step up and (c)

inverting converters

78

Figure ‎4-2 Voltage and current waveforms of the inverting converter during a zero

impedance input fault condition during the step up mode

Cap

acit

or

volt

age

wav

eform

In

duct

or

curr

ent

wav

efo

rm

Sw

itch

es c

urr

ent

wav

eform

s

pkLi

1fpkLi

2fpkLi

1fpkLi

2fpkLi

pkLi

pkcv

fpkcv

fpkcv

pkcv

Fault instant

0

cv

Li

2si

1si

During Fault Pre-fault tr

79

iv

1s

1s

2s

2s

rL

faultiii

D

iv

1s

1s2s

2s

rC

rL

faultiiiD

iv

1s

1s2s

2s

rL faultiii

D

(c)

(b)

(a)

rC

rC

-

+

+-

-

+

Figure ‎4-3 Zero impedance output fault condition for the (a) step down, (b) step up and (c)

inverting converters

80

Upon detecting the fault, gating signals should be suppressed. Otherwise, the fault current will

increase after each switching signal as shown in Fig.4-4. In this case, equation (4.2) does not

apply as the converter operates in the CCM. At CCM, the inductor current after each switching

instant will be described by (4.3).

tCL

vtIti r

rr

irorL sin

/

2cos (4.3)

where Io is the initial current of the inductor before switching. Even during CCM, after each

switching instant, the switch current will always turn-off naturally as the current commutates to

the diode with no shoot through mode.

If the fault occurred after commutation while the inductor (and the diode) is conducting, the

converter enters CCM after the first switching instant. In this case, the fault current follows

equation (4.3) where Io is the initial current of the inductor before switching. The switch current

will also turn-off naturally as the current commutates to the diode with no shoot through mode.

From this discussion we conclude that a fault at the output terminals of the step-down

converters can be prevented from propagation to the input bus by suppressing the gating signals,

and will not result in shoot-through modes in the switches.

4.2.2.2 Step-up converter

In case of a fault at the output terminal of the step-up converter shown in Fig. 4-3 (b), we note

that this fault will be fed directly from the input bus through the diode valve. Unlike the case

with the step-down converter where the fault current pass through the LC resonant circuit, the

fault current of the step-up converter only passes through the inductor. This means that the

current will continue increasing linearly charging-up the inductor uncontrollably.

This shows that a fault at the output terminal of a step-up converter will propagate to the input

bus even if the gating signals are stopped. An exception to this would happen if a high

impedance fault occurs resulting in a fault voltage, at the output terminals, higher than the input

voltage of the converter. In this case stopping the gating signals will stop supplying the fault

current.

81

4.2.2.3 Inverting converter

In case of the inverting converter shown in Fig. 4-2 (c) having a fault at its output terminal

while S1 is closed, we note that the fault current is supplied from the resonant inductor, but has

no direct connection to the input bus. Initially upon closing S1 after the fault instant, the inductor

current is described by:

tCL

vvti r

rr

coirL sin

/

(4.4)

where vco is the initial capacitor voltage at the beginning of the switching instant which equals to

(-vi - vo) for the first pulse and (-vi) at steady-state. Equation (4.4) shows that this initial current

will have the same peak value as the nominal current given by (3.53). It is important to note that

this current will commutate from S1 to D at the instant tr when the capacitor voltage is

charged to the value of the input voltage vi. The capacitor voltage will remain charged to vi after

the current commutation. Therefore the current of the switch S1 will naturally drop to zero.

Similar to the step-down converter, no shoot-through occurs to S1 after the fault instant. This is

well demonstrated in Fig.4-5. The fault current will remain circulating in the output circuit

through the diode but will not be fed from the input bus. Upon detecting the fault, gating signals

should be suppressed to prevent increasing the fault current by another current pulse. If gating

signals did not stop, the fault current would increase after each switching signal as shown in

Fig.4-5. In this case, equation (4.4) does not apply as the converter operates in the CCM. At

CCM, the inductor current after each switching instant will be described by (4.3) similar to the

step-down converter. Even during CCM, after each switching instant, the switch current will

always turn-off naturally as the current commutates to the diode. If the fault occurred while the

inductor (and the diode) is conducting, the converter enters CCM after the first switching instant.

In this case, the fault current follows equation (4.3) where Io is the initial current of the inductor

before switching. The switch current will also turn-off naturally as the capacitor voltage is

charged to the value of the input voltage and no shoot through occurs to the switches.

From this discussion we conclude that a fault at the output terminals of the step-down converters

can be prevented from propagation to the input bus by suppressing the gating signals, and will

not result in shoot-through modes in the switches.

82

Figure ‎4-4 Voltage and current waveforms of the step-down converter during a zero

impedance output fault condition at its terminal

Cap

acit

or

volt

age

wav

eform

In

duct

or

curr

ent

wav

efo

rm

Sw

itch

es c

urr

ent

wav

eform

s

pkLi

1fpkLi

2fpkLi

1fpkLi

2fpkLi

pkLi

pkcv

pkcv

Fault instant

0

cv

Li

2si 1si


83

Figure ‎4-5 Voltage and current waveforms of the inverting converter during a zero

impedance output fault condition at its terminal

Cap

acit

or

volt

age

wav

eform

In

duct

or

curr

ent

wav

efo

rm

Sw

itch

es c

urr

ent

wav

eform

s

pkLi 1fpkLi

1fpkLi

pkLi

pkcv

pkcv

Fault instant

0

cv

Li

2si

1si


84

4.3 Semiconductors power losses

The efficiency for proposed converters can be estimated by calculating the losses of various

components. In this section, we focus on the losses associated with active and passive switches.

These losses vary depending on the type of the switch, but are generally composed of conduction

and switching losses. An estimate to these losses can be obtained by examining the voltage and

current waveforms of the ideal switches discussed in the previous chapter, and the loss

information obtained from the manufacturers‘ datasheets and application notes [38]-[41]. In this

chapter, thyristors will be used as active switches.

4.3.1 Thyristor losses

An estimate for the thyristor losses can be obtained using the information given in the device‘s

datasheet, these losses consist of the following [38]-[40]:

1. On-state losses, during thyristor conduction.

2. Off-state losses, due-to the leakage current while the device is off.

3. Turn-on losses.

4. Turn-off losses.

The on-state losses depend on the voltage drop across the thyristor (VT) and the current

through it (IT) when the device is on. For EUPEC T1503N, the on-state voltage is between

2.8 – 3 V. It can be estimated approximately from the following linear relation [40]:

TTTT IrVV 0 (4.5)

where the slope resistance (rT) and the threshold voltage (VTO) are given in the datasheet.

Alternatively, a more precise function to calculate the on-state voltage is [40]:

TTTT IDICIBAV 1ln (4.6)

where the parameters A,B,C,D are given in the data-sheet. The on-state losses (WON-State) per

switch per cycle can then be expressed as:

85

r

dtiVW sTStateON

/

0

(4.7)

where is is the thyristor current (IT in the datasheet), and vs = VT when the device is on.

The off-state losses depend on the off-state forward and reverse leakage currents (il) which

equal to 600 mA for EUPEC T1503N at rated off-state forward and reverse voltages (vrated) and

maximum temperature. The off-state losses (WOFF-State) can be calculated by considering a linear

relation between the leakage current (il) and the off-state forward and reverse voltages and can be

expressed as:

offfoffr tt

rated

slStateOFF dt

v

viW

0

2

(4.8)

The turn-on losses (WTurn-ON) in a thyristor are generated after triggering. When the thyristor

is triggered, the anode to cathode voltage starts to drop dynamically till it reaches the static on-

state voltage VT. During this initial conduction time, the thyristor voltage will be higher than the

static voltage, generating extra losses. Some manufacturers ignore these losses from their

datasheets [40]. Others [39] provide curves for turn-on energy per cycle, for different rates of

rise of the on-state currents. In this thesis, light triggered thyristors (LTT) are assumed and the

manufacturer ignores their turn-on losses from the datasheets [40].

The turn-off losses (WTurn-OFF) in a thyristor arise from the reverse recovery phenomenon.

Similar to all minority carrier devices, when a thyristor turns off, a reverse-recovery current is

generated. Its amplitude depends primarily on the rate of current decrease. Therefore, thyristor

current becomes momentarily negative reaching a peak value of IRM before returning to zero

during the recovery phase. A simple diagram of this phenomenon is shown in Fig.4-6. From this

figure, the reverse recovery energy loss (WTurn-OFF) per cycle is expressed as:

offSRM

t

ssOFFTurn vtI

dtviW2

2

0

2

(4.9)

86

From the manufacturer‘s datasheet, the peak reverse recovery current IRM and the reverse

recovery charge Qrr are obtained. Using these data, with the simple model of Fig.4-8, t1 and t2

can be calculated from the following relations:

1tdt

diI RM (4.10)

2

21 ttIQ RM

rr

(4.11)

0

0

1t 2t

dtdi/

RMI

rrQ

offSv

Sv

Si

Tv

Figure ‎4-6 Linear model to estimate the reverse recovery losses

Since thyristors turn off at zero voltage (i.e. vS off = 0), the reverse recovery losses are ideally

zero. During the reverse recovery a thyristor acts as a current source. Practically, an RC snubber

circuit may be connected parallel to high voltage thyristors to dissipate the reverse recovery

charge and avoid ringing in the circuit [42]. In this case, the losses associated with the snubber

circuit would be taken into consideration.

87

4.3.2 Diode losses

Similar to the thyristor, a diode will have the four types of losses mentioned above. The on-state

losses can be calculated from (4.7) after calculating the diode on-state voltage using either (4.5)

or (4.6). The off-state losses can be calculated from (4.8) knowing the reverse leakage current

and the reverse voltage of the diode. The turn-off losses due to reverse recovery can be estimated

from (4.9) using the same technique for the thyristor. The turn-on losses (WTurn-ON) per cycle can

be estimated from the following relation [42]:

2

6

1fr

DFRMONTurn t

dt

diVW (4.12)

where VFRM is the peak forward recovery voltage at the turn-on current rate of change, and tfr is

the time constant of VFRM. When turned on with a high current rate of change, the initial forward

voltage of the diode experiences an overshoot. This overshoot originates from the fact that

conductivity of the diode is reduced, because the number of free charge carriers available is

much lower than in the steady-state. The device needs time to build up the required electron and

hole concentration, within the bulk of the silicon [42]. In the diode data sheet, VFRM is given as a

curve against the current gradient per wafer unit area.

88

4.4 Filtering capacitors

In the previous discussions, ideal input and output voltage sources were connected to the input

and output terminals of the proposed converters. In practice, input and output filtering capacitors

will replace these voltage sources. The design of these capacitors depends on a pre-specified

values for the amplitude of the input and output voltage ripples Δvi , Δvo. after each switching

instant. From (3.8), (3.17) and (3.21), sizing the filtering capacitors can be done as follows:


i

irinputf

v

vCC

2 (4.13)

oo

iroutf

vv

vCC

22 (4.14)


iio

orinputf

vvv

vCC

22 (4.15)

oio

oiroutf

vvv

vvCC

2 (4.16)


ii

oiirinputf

vv

vvvCC

2 (4.17)

oo

oiiroutf

vv

vvvCC

2 (4.18)

89

4.5 Black-start during step-up operation

Upon starting the step-up converter or the inverting converter (in the step-up mode) while the

resonant capacitors are discharged, a voltage build-up process takes place. During this process,

power is withdrawn from the input bus to charge the capacitors but no current is injected in the

output bus. This process was explained in the previous chapter with the help of Fig.2-11,

Fig. 2-12 and Fig. 2-14. In this section, we are interested to study the start-up dynamics in order

to obtain a relation for the black-start time. From (3.24) and (3.25), the DCM inductor current

and capacitor voltage during the start-up process can be described as follows:

ttCL

vvti rr

rr

coirL 0sin

/ (4.19)

tvvvtv rociirc cos. tr0 (4.20)

Where cov is the resonant capacitor‘s initial voltage at the instant of switching. The peak value of

the inductor current occurs at 4/rTt which yields:

rr

coirr

rr

coipkL

CL

vvT

CL

vvi

/4/sin

/

(4.21)

and the peak capacitor voltage occurs at 2/rTt which yields

coirrcoiipkc vvTvvvv 22/cos (4.22)

The expression in (4.22) means that each switching instant (i.e.half-switching cycle) results in

charging the capacitor and amplifying its voltage by iv2 . Since the converter‘s voltage build-up

process ends when the capacitor‘s voltage equals ov for the step-up converter and oi vv for the

inverting converter, their black-start time can be expressed by (3.62) and (3.63) respectively:

si

os

i

oBS

fv

vT

v

vT

422 (4.23)

si

ois

i

oiBS

fv

vvT

v

vvT

422

(4.24)

90

4.6 The ESR effect on the maximum step-up ratio

The analysis done in the previous section assumed loss-free converter. As a result, no boundary

on the maximum voltage stepping ratio has been identified. In practice, the LC resonant circuit

experiences a degree of damping. This damping is caused by the resistances of the components

in the resonance path. This includes the equivalent series resistance (ESR) of the resonant

inductor and capacitors as well as the collective resistance of the switches. Taking this damping

into consideration will allow us to derive an expression for the maximum voltage stepping ratio

at DCM. Considering a lumped resistance r in the resonant circuit, the inductor current and

capacitor voltage relations will be given by:

teL

rIvvti d

t

r

ocoi

d

L

sin1

(4.25)

rtietvvvtv L

t

d

dcoi

d

oic

1tancos (4.26)

where vco is the initial capacitor voltage at the beginning of the switching instant. During the

situation of a maximum stepping ratio, rotating the resonant capacitor doesn‘t yield any voltage

step-up. Mathematically this is expressed by the following condition

max,2

vvvT

tat cocr (4.27)

Substituting (4.27), (4.25) into (4.26) and neglecting 2/rL Ti yields:

D

D

v

v

od

od

i

max

(4.28)

Where D is a negative quantity equal to:

r

rr

rrr

r

dr

rrd

T

d

rd

L

CrT

L

r

cLL

r

L

CrTe

TD

r

22,

4

12

,4

12

,tan2

cos2

2

21

At this condition, no current reaches the output circuit and all the input power is dissipated into

the lumped resistance r.

91

4.7 Effect of the stray inductance

As part of the circuit non-idealities, a stray inductance Lc in the commutation circuit will

influence the operation of the converters. The stray inductance Lc exists due to the bus-bars

inductance, the inductance of the switches, capacitor and diodes. The effect of this inductance

appears during commutation. In the ideal converters, the commutation event is an instant in

which the current of the resonant inductor commutates abruptly to the output circuit. Any

inductance in series with the diode, or with the active switching network will oppose this abrupt

commutation by elongating it. The result appeared as a ―soft‖ switching for the diode turn-on and

the switches turn-off, as the current will have finite slope during commutation. Fig. 4-7 and

Fig. 4-8 show how the commutation inductance influences the waveforms during step down

operation, while Fig. 4-9 and Fig. 4-10 show its influence on the step-up operation. The

waveforms are generated for an exaggerated value of the stray inductance to ease demonstrating

its effect. By examining the above figures, the following comments can be made about the

influence of the stray inductance on commutation:

The stray inductance Lc elongates the commutation period and reduces the active switch

turn off time.

By elongating the commutation period, resonant capacitors are overcharged.

The converter‘s power increases for a given switching frequency.

As the peak capacitor voltage increases, the peak inductor current increases.

The switches should block a higher peak capacitor voltage and withstand higher peak

inductor current.

The peak blocking voltage of the diode increases, and its peak current increases as well.

The diode and switches will have lower current rate of change during commutation.

The turn-off voltage of the switches has a non-zero value

The turn-off voltage of the diode is unaffected.

92

c

Figure ‎4-7 The influence of the commutating inductance on the current and voltage

waveforms during step-down operation

Res

onan

t ca

pac

itor

volt

age

Res

onan

t in

duct

or

curr

ent

Curr

ents

of

the

swit

ches

and d

iodes

pkcv

pkLi

pkcv

0

tr

cc Lwithoutv

pkLi

Commutation period with Lc

*

pkcv

*

pkcv

*

pkLi

pkLi

*

pkLi

pkcv

cc Lwithv

cLwith

cL Lwithi

cLwithout

cL Lwithouti

Commutation instant without Lc 0

93


waveforms of the switches and diodes during step-down operation

Curr

ents

of

the

swit

ches

and d

iodes

Volt

age

wav

eform

s of

the

swit

ches

V

olt

age

wav

eform

of

the

dio

de

offDv

pkLi

0

tr

Dv with Lc

Sv without Lc

0

*

pkDv

Sv with Lc

Dv without Lc

pkDv

pkDv

pkDv


Commutation instant without Lc

cLwith cLwithout

pkLi

*

pkLi

0

94


waveforms during step-down operation

Res

onan

t ca

pac

itor

volt

age

Res

onan

t in

duct

or

curr

ent

Curr

ents

of

the

swit

ches

and d

iodes

pkcv

pkLi

pkcv

0

tr

cc Lwithoutv

pkLi


*

pkcv

*

pkcv

*

pkLi

pkLi

*

pkLi

pkcv

cc Lwithv

cLwith

cL Lwithi

cLwithout

cL Lwithouti


pkLi

0

95


waveforms of the switches and diodes during step-down operation

Curr

ents

of

the

swit

ches

and d

iodes

Volt

age

wav

eform

s of

the

swit

ches

V

olt

age

wav

eform

of

the

dio

de

offDv

pkLi

0

tr

Dv with Lc

Sv without Lc

0

*

pkDv

Sv with Lc

Dv without Lc

pkDv

pkDv

pkDv



cLwith

cLwithout

pkLi *

pkLi

0

96

We conclude that the influence of the stray inductance would have some advantages by

increasing the converter‘s power density and lowering the current derivatives. This comes with

the cost of higher blocking voltage for the semiconductors and higher losses. Quantifying these

influences are done through simulation models, as obtaining closed mathematical relations can

be quite complex. For example, with the effect of the stray inductance, the diode current for the

step-up converter appears as:

rccco

c

rrcc

rcr

coi

rr

oi

rcr

coiD

tvvL

Ct

CLL

vv

tL

vv

CLL

vvi

/sin/cossin/)(

sin/)(

(4.29)

where vco is the capacitor initial voltage, cv is the capacitor voltage at and rcc CL/1 .

97

4.8 Thyristors turn-off time

In case of using thyristors as active switches, upon commutation a finite time delay must

elapse before the device can again be positively biased maintaining its off-state. This minimum

delay is called the circuit commutated turn off time (tq). During the design stage, the thyristor

turn off time at maximum power should be higher than tq. This will put a constraint on the

maximum switching frequency of the converter. From Fig. 3-7, Fig. 3-8 this implies that tr off ≥ tq.

From equations (3.27), (3.29), (3.31) this issue can be considered by ensuring the following

conditions are met:


oi

i

rr

srrq

vv

v

CL

TCLt 1cos

2 (4.30)


oi

i

rr

srrq

vv

v

CL

TCLt

2cos

2

1 (4.31)


oi

i

rr

srrq

vv

v

CL

TCLt

2cos

2

1 (4.32)

98

The conditions (4.30), (4.31) and (4.32) imply an absolute maximum switching frequency for

each converter as follows:


oi

i

io

o

rr

q

rr

abss

vv

v

vv

v

CL

tCL

f

11

max

cos2

cos2

1|

(4.33)


oi

i

oi

oi

rr

q

rr

abss

vv

v

vv

vv

CL

tCL

f

2coscos2

1|

11

max (4.34)


oi

i

io

o

rr

q

rr

abss

vv

v

vv

v

CL

tCL

f

2cos

2cos2

1|

11

max (4.35)

The designer should ensure that the chosen switching frequency be lower than the maximum

values given in the above relations. If switches other than thyristors are used, such as

symmetrical IGCTs, or RB-IGBTs then the above frequency constraints are not necessary. The

converter‘s frequency will only be limited by the critical electrical limits of the voltage and

current gradients of the devices, the thermal limits of the circuit, and the switching losses.

99

4.9 Design steps

The design process usually includes several trade-offs between the component cost, size, losses

and availability. A simplified design flow-chart is shown in Fig. 4-11. Generally, the following

design steps can be followed to design any of the proposed converters:

1. Determine the maximum power and terminal voltages of the converter.

2. Choose an active switch and the output diode. The active switch should at least withstand

half the average current of the low-voltage side. The diode should withstand the average

current of the high-voltage side. If the converter power is too high, consider dividing this

power among paralleled interleaved converters, or paralleled components.

3. Determine the size of the capacitor from (3.11) or (3.20) or (3.24). To do this, choose a

value for the maximum switching frequency below (fs = 1/2tq ).

4. Determine the size of the inductor from (3.42) or (3.43) or (3.44). To do this, calculate

the value of the conduction angle from (3.39) or (3.40) or (3.41).

5. Adjust the value of the inductor and/or the switching frequency to satisfy the conditions

(4.30) or (4.31) or (4.32). Repeating steps 3 and/or 4 might be required.

6. Calculate the critical current and voltage parameters of the semiconductors from sections

3.7 and 4.4; also determine the number of converter cells and series diodes. Finally,

estimate the converter losses from section 4.5.

7. Estimate the value of the stray inductance and simulate its effects on the circuit if it is

higher than 2% of the resonant inductance.

8. Calculate the value of the capacitor of each converter cell from (3.5).

100

Interleaved?

Select Devices

oii vvP ,,

√

avDavS ii ,

sf

rC

iP

losses

rL

qt

End

√

√

*

*

Figure ‎4-11 Simplified design flow-chart

101

4.10 Design trade-offs

In this section we briefly discuss the design trade-offs associated with some design objectives.

Lower converter size/weight: this can be done by operating the converter at the highest possible

frequency. This however will imply using fast turn-off thyristors or switches other than

thyristors. In both cases this implies higher on-state losses and higher current and voltage rate of

change.

Lower on-state current: This can be achieved either by paralleled interleaved converters, or by

paralleled thyristors. In either case, this results in higher number of components and higher size/

weight of the converter.

Lower peak currents: The peak currents can be reduced by increasing the size of the resonant

inductor, or effectively by reducing the maximum switching frequency. This results in higher

size and weight for inductor and also higher value of the resonant capacitors.

Lower current derivatives: This can be reduced by increasing the size of the resonant inductor

and adding a commutating inductor. The trade-offs of both solutions has been discussed in the

previous point and section (4.7) respectively.

Using low on-state voltage drop thyristors: This leads to lower on-state losses but usually have

also higher switching losses and turn-off times.

Using parallel switches or diodes: This will naturally result in higher number of components to

reduce the on-state current. This will result in higher off-state losses but won‘t change the on-

state losses considerably.

102

4.11 Summary

In this chapter numerous practical considerations have been studied to complement the

discussion in the precious chapters. The study of the zero-impedance faults at the output

terminals of the converter show that no shoot-through modes can occur to the active switches

during the fault. With the exception of the step-up converter, faults at the output terminals of the

step-down converter and the inverting converters can be prevented from propagating to the input

terminal of the converter by suppressing the gating signals.

Expressions for the conduction and switching losses of the semiconductors have been derived

in this chapter. This will be used in the next chapter to quantify the semiconductor losses for

each of the proposed topologies.

The design equations for the dc filtering capacitors have been derived. Expressions for the

black-start time for the step-up converter and the inverting converter (in the step-up mode) have

been derived.

Studying the behavior of the step-up converter and the inverting converter (in the step-up

mode) taking into consideration the ESR, revealed an expression for the maximum theoretical

voltage step-up ratio. The stray inductance of the circuit was also studied in this chapter. It was

found that this inductance will limit the rate of change of the diode current and the active

switches current during commutation. It will contribute to charging the resonant capacitor and

would result in higher blocking voltages on the power semiconductors.

In case of using thyristors as active switches, it was found their minimum turn-off time would

limit the maximum switching frequency of the proposed converters. Expressions for the absolute

maximum switching frequency were presented.

The chapter concludes with a set of systematic design steps for the proposed converters and

highlights the major design trade-offs.

103

Chapter 5 Design Examples and Experimental Prototyping

5

5.1 Introduction

In order to prove the concept of the proposed converters for high voltage and high power dc-dc

conversion, this chapter presents design examples and experimental prototyping. While the

experimental prototype is limited in voltage and power ratings, the design examples are done for

the targeted power and voltage range of the proposed converters. Four design examples are

presented for the following ratings:

1. 6 MW converters connecting ±1.5, ±7.5 kv dc buses.

2. 30 MW converters connecting ±7.5, ±33 kv dc buses.

3. 120 MW converters connecting ±33, ±150 kv dc buses.

4. 30 MW converters connecting ±7.5, ±150 kv dc buses.

For each design example, full design and analysis will be done for the step down, step up and

inverting converters and the results will be compared. Appendix D extends the discussion to

bidirectional single inductor converters. These designs yield components sizing, determination of

critical parameters and loss analysis in the semiconductor devices. The main objective of these

examples is to understand the limitations of the proposed converters for high voltage and high

power ratings, and to compare the losses and the required number of power semiconductors

devices for each converter topology. During the design, a safety factor of (at least) 200% is

considered for the semiconductors voltage ratings. Light triggered thyristors (LTT) are used as

active switches. This ensures synchronized firing between the thyristors, eliminating the need for

complex design of the gate firing circuits. The diodes will be of the ―fast recovery‖ class. Table

5.1 and Table 5.2 show several currently available thyristors and diodes. The diodes listed in

Table 5.2 are primarily designed as freewheel diodes for high voltage GTOs and IGCTs. They

are optimized for low switching losses and can withstand high switching transients [41].

104

Parameter pkrSpkfS vv

avSi

RMSSi

max|onS

dt

di

max|offs

dt

dv

maxTv

qt

Unit V A A A/ µs V/ µs

V µs

T553N

7200 550 1200 300 2000 2.65 650

T1503N 7700 1770 3900 300 2000 3 550

T2563N 7700 2520 5600 300 2000 2.95 550

T4003N 5400 3480 7820 300 2000 1.8 500

Table ‎5-1 Comparison between the ratings of light triggered thyristors

Parameter pkDv

avDi

RMSDi maxonDv

maxrrE

Unit V A A V J

5SDF 07F4501

4500 650 1000 2.7 1

5SDF 13H4501 4500 1200 1900 2.5 1.25

5SDF 10H6004 6600 1100 1700 3 5

5SDF 05F4502 4500 435 685 4.7 3.1

5SDF 10H4502 4500 810 1270 4.85 4.5

5SDF 10H4503 4500 1100 1740 3.8 9.5

5SDF 10H4502 4500 1440 2260 3.8 9.5

5SDF 16L4503 4500 1650 2590 4.51 9

5SDF 04F6004 5500 380 600 5.2 3.5

5SDF 08H6005 5500 585 920 6.85 6.5

Table ‎5-2 Comparison between the ratings of fast recovery diodes

105

5.2 Converters design

5.2.1 Switch selection

A lower converter weight/space would result if the switching frequency is maximized. From

Table 5-1, we note that the T553N switch has the highest minimum turn-off time (tq) and would

result in a lower switching frequency and higher converter weight/space. Therefore, T553N will

not be selected. The T4003N switch has the lowest turn-off time (tq), but has much lower voltage

and very high current ratings. If the T4003N is selected, this will result in a larger number of

converter cells and lower current utilization for the switch. Therefore, T4003N will not be

selected as well. The T1503N and T2563N switches have mid-range current rating, high voltage

rating and relatively low turn-off time (tq). Therefore these switches are more suitable to choose

from to design the proposed converters.

In the design, an initial switching frequency of 700Hz will be used to design all the proposed

converters. This switching frequency is selected to be below 1/2tq to ensure a minimum turn-off

time for the switches well above tq, as determined from (4.39)-(4.41).

Table 5-3 to Table 5-6 show the fundamental parameters of the proposed converters for all of

the design examples. By examining the value of the maximum average switch current at 700Hz

(iS av max), we note that it can be as low as 200A for the step down converter and as high as 1000A

for the inverting step-up converter. The T1503N switch is rated for an average current of 1770A

while T2563N switch is rated for 2520A. If used, the T2563N will result in higher cost, lower

current utilization but lower conduction losses. The T1503N switch will be initially selected to

minimize the converter cost.

5.2.2 Resonant capacitance

The resonant capacitance is determined from (3.11) or (3.20) or (3.24). The maximum

switching frequency was initially chosen in the previous step as 700Hz for all the converters.

Tables 5-3 to 5-6 give the value of the resonant capacitance per pole ( ), rr CC for each

converter.

106

5.2.3 Converter cells

The number of converter cells for each converter is chosen such that a minimum safety factor

of 200% for the thyristor peak voltage is guaranteed. This means that the designed peak voltage

of any power devices does not exceed half the peak voltage in the datasheet. Based on this, the

value of the capacitance of each cell rnc is determined. Design results are given in Table 5-7.

5.2.4 Diode selection

From Tables 5-3 to 5-6, we note that the average diode current for step-down converters is

always higher than 1400A, whereas it is lower than 500A for the step up converters. By

examining Table 5-2, we choose the diode 5SDF 13H4501 for all converters as it has low turn-

on voltage and low energy recovery at relatively high average current of 1100A.

For the step-up converters, diode valves of series units composing one string will be used. For

the step-down converters and diode valves of three parallel strings will be used for the step-down

converters.

The stray inductance of the circuit will be assumed to limit the rate of change of the diode

turn-on current to 1000 A/ µs. This low stray inductance will introduce significant forward

recovery turn-on losses in the diode valves but will ensure negligible reverse recovery turn-off

losses on the thyristors. From the diode‘s datasheet, the peak forward recovery voltage VFRM will

be 85 V/ diode.

The number of series diode units in each string will be chosen such that a minimum safety

factor of 200% for peak voltage rating is guaranteed. Table 5-7 shows the number of series

diodes for each design example.

107

5.2.5 Inductor sizing

The inductors are sized to allow a minimum of 100 µs discontinuous current interval at the

maximum operating frequency of 700Hz. This is done by introducing a design parameter

δ = 100 µs in the inductor design relations of (3.41)-(3.43) to yield (5.1)-(5.3):


02

1sin

/

2

rr

sr

o

rr

oi CLfL

v

CL

vv (5.1)


02

1sin

/

rr

sr

oi

rr

oi CLfL

vv

CL

vv (5.2)

For the inverting converters:

02

1sin

/

2

rr

sr

o

rr

oi CLfL

v

CL

vv (5.3)

5.2.6 Design results

Table 5-7 gives the following details for each converter: (i) the number of active switching

cells per pole, (ii) the number of diodes in each diode valve per pole (nd), (iii) the value of the

capacitance in each cell (crn) and its peak voltagerncv , which is the peak voltage of each thyristor

unit. The semiconductor losses of each converter have been analytically calculated and are

shown in Table 5-8. The loss analysis includes: (i) the total conduction losses in the thyristors

and diodes (W Cond) which includes the on-state losses WOn-State from (4.31) and the off-state

losses WOn-State from (4.32). (ii) the turn–on losses of the diodes (W Turn-ON), (iii) the turn-off

losses of the diodes (W Turn-OFF), and (iv) the percentage of the total semiconductor losses. The

switching losses of the thyristors are neglected, as they turn on at zero current and turn off at

zero voltage.

108

Converter Parameter

6 MW converters connecting ±1.5, ±7.5 KV dc buses

Step-down Step-up Inv. Step-up Inv. Step-down

Ai avi 400 2000 2000 400

Ai avo 2000 400 400 2000

FCC rr , 19.046 76.19 79.36 15.873

rad 1.6821 2.3 2.3664 1.6618

mHLL rr , 0.1754 0.4238 0.4246 0.1493

Ai avL 2000 2000 2400 2400

Ai RMSC max 1200 2262 2752 1313

Ai RMSS max 849 1600 1946 929

Ai avS max 200 800 1000 200

KAi pkS 4.448 3.816 4.539 5.379

sAdt

dion

S /| max 77 21 25 111

)/(| max sVdt

dvoff

s

117 25 19 113

Ai RMSD max 2153 861 905 2642

Ai avD max

1600 400 400 2000

KAi pkD

4.42 2.845 3.177 5.357

sAdt

dioff

D /| max

8.5 14.1 17.7 10

max|abssf (Hz)

815 806 692 866

Table ‎5-3 Design parameters for the converters of the first design example

109

Converter Parameter

30 MW converters connecting ±7.5, ±33 KV dc buses


Ai avi 455 2000 2000 455

Ai avo 2000 455 455 2000

FCC rr , 4.8 16.726 17.636 4.008

rad 1.6994 2.2519 2.3288 1.673

mHLL rr , 0.8615 1.8565 1.867 0.7215

Ai avL 2000 2000 2455 2455

Ai RMSC max 1278 2234 2794 1415

Ai RMSS max 904 1580 1976 1001

Ai avS max 227 771 997 227

KAi pkS 4.421 3.844 4.665 5.478

sAdt

dion

S /| max 68 22 26 102

)/(| max sVdt

dvoff

s

100 26 24 124

Ai RMSD max 2116 941 999 2668

Ai avD max

1545 455 455 2000

KAi pkD

4.384 2.986 3.388 5.45

sAdt

dioff

D /| max

8.7 13.7 17.7 10.4

max|abssf (Hz)

806 841 698 861

Table ‎5-4 Design parameters for the converters of the second design example

110

Converter Parameter

120 MW converters connecting ±33, ±150 KV dc buses


Ai avi 400 1818 1818 400

Ai avo 1818 400 400 1818

FCC rr , 0.952 3.376 3.548 0.7806

rad 1.6947 2.2644 2.3384 1.67

mHLL rr , 4.1925 9.298 9.339 3.5245

Ai avL 1818 1818 2218 2218

Ai RMSC max 1142 2037 2530 1262

Ai RMSS max 807 1440 1789 893

Ai avS max 200 709 904 200

KAi pkS 4.023 3.487 4.21 4.956

sAdt

dion

S /| max 64 20 23 94

)/(| max sVdt

dvoff

s

88 26 25 132

Ai RMSD max 1928 836 886 2420

Ai avD max

1418 400 400 1818

KAi pkD

3.993 2.681 3.0329 4.931

sAdt

dioff

D /| max

7.8 12.6 16 9.4

max|abssf (Hz)

808 831 697 862

Table ‎5-5 Design parameters for the converters of the third design example

111

Converter Parameter



Ai avi 100 2000 2000 100

Ai avo 2000 100 100 2000

FCC rr , 0.238 4.524 4.534 0.226

rad 1.596 2.702 2.712 1.595

mHLL rr , 0.9625 8.285 8.28 0.92

Ai avL 2000 2000 2100 2100

Ai RMSC max 605 2377 2496 615

Ai RMSS max 428 1680 1765 435

Ai avS max 50 950 1000 50

KAi pkS 4.6 3.68 3.86 4.82

sAdt

dion

S /| max 304 19 19.93 334

)/(| max sVdt

dvoff

s

496 21 21 520

Ai RMSD max 2354 309 313 2453

Ai avD max

1900 100 100 2000

KAi pkD

4.6 1.57 1.97 4.82

sAdt

dioff

D /| max

7.8 17.2 13.4 6

max|abssf (Hz)

878 660 641 897

Table ‎5-6 Design parameters for the converters of the fourth design example

112

Converter

Parameter



No. Cells / pole 2 2 3 3

No. series diodes

7 7 8 8

Fcrn 38.092 152.38 238.08 47.619

kvvrnc

3.75 3.75 3 3

Converter

Parameter



No. series diodes

30 30 36 36

Fcrn 43.2 150.534 194 44.088

kvvrnc

3.67 3.67 3.68 3.68

Converter

Parameter


No. Cells / pole 39 39 48 48

No. series diodes

134 134 163 163

Fcrn 37.128 131.664 170.304 37.47

kvvrnc

3.85 3.85 3.81 3.81

Converter

Parameter


No. Cells / pole 39 39 41 41

No. series diodes

267 267 280 280

Fcrn 9.282 176.436 185.894 9.266

kvvrnc

3.85 3.85 3.84 3.84

Table ‎5-7 Comparison between design parameters of the proposed converter for the four

design examples

113

Converter loss

Parameter



KWPcond

73.5 87 135 112.5

KWP ONTurn

5.4 2.17 3.2 8.9

KWP OFFTurn 0.9 1.1 1.4 0.9

% Losses 1.3 % 1.5 % 2.3 % 2 %

Converter

Parameter


KWPcond

304 340 540 488

KWP ONTurn

11.4 10 16.3 41.6

KWP OFFTurn 4.2 4.8 6.2 4.2

% Losses 1.1 % 1.2 % 1.9 % 1.8 %

Converter

Parameter


KWPcond

1278 1450 2300 1954.5

KWP ONTurn

85 38.2 58.2 155.2

KWP OFFTurn 18.6 21.9 28.2 18.6

% Losses 1.1 % 1.2 % 2 % 1.8 %

Converter

Parameter


KWPcond

1273 1640 1850 1402

KWP ONTurn

112 13 21 129

KWP OFFTurn 4.2 26.7 28.1 4.2

% Losses 4.63 % 5.6 % 6.33 % 5.12 %

Table ‎5-8 Loss analysis of the proposed converters for the four design examples

114

From the design results presented in the last section, the following comments can be made:

Semiconductor Losses:

Step up converters (inverting or non-inverting) have higher conduction losses in the

active switches than step down converters. This is because the active switches in step-up

converters carry higher average current and therefore contribute higher than the diodes to

the semiconductor power losses. To enhance the efficiency of the step-up converters,

thyristors with lower conduction losses can be used (e.g. T2563N instead of T1503N).

This is important especially for the step-up converters working at high voltage stepping

ratios.

The diodes of the step down converters (inverting or non-inverting) have higher average

current than the active switches. As a result the diodes contribute higher than the active

switches to the semiconductor power losses. To enhance the efficiency of the step-down

converters, diodes with lower conduction losses can be used, or additional parallel valves

of series diodes can be added. This is important especially for the step-down converters

working at high voltage stepping ratios.

The inverting converters (step up and step down) have higher semiconductor losses than

non-inverting converters. This is observed for both conduction and switching losses. This

is because they require higher number of semiconductor components to withstand higher

peak voltages.

For the same power rating and maximum switching frequency, converters with higher

stepping ratios suffer from higher losses. This is also because they require higher number

of semiconductor components.

The switching losses of all converters are generally much smaller than the conduction

losses, for this range of switching frequencies. The switching losses are mainly in the

diode valves due to the forward and reverse recovery losses.

115

Switching frequency:

The choice of a maximum frequency of 700 Hz was a bit conservative for the step-down

converters (both inverting and non-inverting). As can be observed from the results, these

converters can theoretically operate at frequencies above 800 Hz, for the selected

components, without violating the minimum turn-off time of thyristors. Appendix E

shows the final design parameters of the step-down converters operating at higher

switching frequency.

The choice of a maximum frequency of 700 Hz for the non-inverting step-up converters

of the first three design examples (with low voltage stepping ratio) was also conservative

as these converters can theoretically operate at frequencies above 800 Hz for the selected

components. Another round of design with higher frequency than 700Hz has been carried

out and given in Appendix E.

For the non-inverting step-up converter of the 4th

design example (with high voltage

stepping ratio), the switching frequency should be lowered than 700 Hz in order to

guarantee adequate minimum turn-off time for the thyristors. This converter has been

redesigned and is shown in Appendix E.

For the inverting step-up converters (at moderate and high voltage stepping ratios), a

lower switching frequency than 700 Hz for all the design examples is needed in order to

guarantee adequate minimum turn-off time for the thyristors. These converters are

redesigned and are shown in Appendix E.

Size of resonant capacitors and inductors:

For the same power rating, terminal voltages and maximum switching frequency, step-up

converters require larger values for the resonant inductors and capacitors than step-down

converters. The passive energy storage elements of the step-up converters help ―pump‖

the current from the low-voltage side to the high voltage side.

The values of the resonant components of the inverting step-up converter are higher than

those of the non-inverting converter. The opposite is valid for the step-down converters

where the resonant components have higher values in the non-inverting converter.

116

Inductors and capacitors current rating:

The average current of the resonant inductors are the same for both step-up and step-

down converter of similar power ratings. This means that if the copper losses of the

inductors are considered in the losses, step-down converters will have lower losses as

they require much lower inductance value than step-up converters. This point is also valid

for the inverting step-up and step-down converters.

Since the inductors have high peak currents and voltages. Air core inductors are preferred

in order to avoid saturating the core material.

The RMS and peak current ratings of the capacitors are equal to or slightly less than the

RMS and peak input current of the converters.

Semiconductors current ratings:

Step down converters have lower average current in the active switches than step-up

converters. This is because the active switches require conducting for shorter time in the

step down converters.

Step down converters have higher average current in the diodes than step-up converters.

Parallel diode connections might be necessary of high power step-down converters.

Step down converters have higher current and voltage rate of change in the active

switches. The opposite can be observed for the diodes, where the current rate of change is

lower in the step down converter.

The ratio between peak and average currents in the switches and diodes for all the

converters is high. This means that all semiconductors have low current utilization as a

consequence of DCM operation which is essential to avoid excessive switching losses.

The active switches remain off for half switching period. This causes their average

current to be half the input current (for the step-down and inverting converters) and less

than half the input current for the step-up converter. This also reduces current utilization

of the switches.

117

Converters limitations:

The designed converters have a range of semiconductor losses between 1-2 % for voltage

stepping ratios around 5. They have a range of semiconductor losses around 4-6 % for

voltage stepping ratio of 20. Therefore, the higher the voltage stepping ration, the more

semiconductor losses exist in the converters.

When thyristors are used as active switches, the maximum switching frequency is limited

by the minimum turn-off time of the thyristors. Inverting step-up converters are more

sensitive than other converters to this limitation.

Step down converters with high stepping ratio suffer, at turn-on instant, from high current

rate of change in the active switches, which can exceed the datasheet‘s critical values as

in the fourth design example. This is addressed by increasing the value of the resonant

inductor and running the converter at lower switching frequency despite the fact that no

violation to the minimum turn-off time of the thryrisotrs occurred. This can be observed

from the final design values of the fourth design example in Appendix E.

As per table 5.3 the switches carry an RMS current that is up to 20 times higher than their

average current. This is an obvious cost of using a resonant as opposed to a hard switched

topology. This is an obvious tradeoff between reducing the switching losses through soft-

switching, and increasing the conduction losses. This also imposes limitations on the

design of the resonant inductors and the selection of the resonant capacitors.

118

5.3 Graphical Comparisons

Results of the analytical study are summarized in tables 5.3 through 5.8. Data is very hard to

extract from tabulated data in the previous section. For this purpose, comparative summary is

offered in this section. The data was taken for the final design parameters of Appendix E.

Figure ‎5-1 Comparison between the resonant inductance values (units are in m.H per pole)

119

Figure ‎5-2 Comparison between the resonant capacitance values (units are in µ.F per pole)

120

Figure ‎5-3 Comparison between the semiconductor losses

121

Criteria Step-up Inverting step-up

avii Similar

avoi Similar

rr CC , Higher by 20% for low stepping

ratio and 5% for high stepping ratio

Lower by 20% for low stepping


Very close

rr LL , Higher by 20% for low stepping


Lower by 20% for low stepping


avLi avii avoavi ii

RMSCi Lower than RMSii RMSii

maxavSi 2

avoavi ii

2

avii

pkSi lower higher

max|onS

dt

di High and exceeds limits for high stepping ratios

max|offs

dt

dv

low

maxavDi

similar

pkDi

lower higher

max|offD

dt

di

lower higher

max|abssf

Higher than 700 Hz for low

stepping ratio.

Lower than 700 Hz for high

stepping ratio

Lower than 700 Hz

Losses lower higher

Table ‎5-9 Comparison between inverting and non-inverting step-up converters

122

Criteria Step-down Inverting step-down

avii Similar

avoi Similar

rr CC , Lower by 5% for low stepping ratio Higher by 5% for low stepping ratio

Very close for high voltage stepping ratios

Lower by 3% for low stepping ratio Higher by 3% for low stepping ratio

Very close for high voltage stepping ratios

rr LL , Very close

avLi avii avoavi ii

RMSCi RMSii RMSii

maxavSi Similar

pkSi lower higher

max|onS

dt

di low

max|offs

dt

dv

low

maxavDi

aviavo ii avoi

pkDi

lower higher

max|offD

dt

di

lower higher

max|abssf

higher than 800 Hz higher than 800 Hz

Losses lower higher

Table ‎5-10 Comparison between inverting and non-inverting step-up converters

123

5.4 Experimental prototyping

In this section, experimental prototypes of the step-up and step-down converters are built for a

5KW scaled down system running on terminal voltages of 115V, 620V. Unipolar modular

topologies are implemented using two active switching cells. Fig. 5-1 shows the switching cells.

Each cell uses SKM200GBD123D modules to implement the active switches. Each switch

consists of an IGBT in series with a diode. The series diode is needed to give the switch reverse

blocking characterestics. The 115V dc side (low voltage terminal) is a dc generator. The 620V

terminal (high voltage terminal) is implemented by rectifying an ac voltage using the rectifier

shown in Fig.5-1. A resistive load bank is employed on the 620V bus to ensure the bus can either

source or sink power as required. The ac voltage is regulated with the adjustable transformer

shown in Fig. 5-3.

The converter diodes are implemented with two series units of CS241210. Fig. 5-2 shows a

picture of the diodes and the measurement devices connected to the converter modules. The

input and output power is calculated by multiplying the average voltage and the average current.

The average voltage is measured with a dc voltmeter. The average current is measured by a

milli-voltmeter measuring the voltage drop of a small series resistance ―a shunt‖.

Fig. 5-4 shows schematics of the converters. Table 5-11 shows the design parameters of the

implemented converters. A Litz-wire ferrite-core variable inductor with low core losses is used

in the experimental prototypes. The objective of the experimental prototype is to verify the

following:

Voltage is being shared equally between the two switching cells for both step-down

and step-up operations.

Theoretical waveforms of the converters are validated experimentally.

Loss estimation of the converters is validated.

124

Figure ‎5-4 Picture showing two active switching cells

Rectifier circuit Active switching cell

Control and

measurements

125

Figure ‎5-5 Picture showing the diodes and measurement units

Figure ‎5-6 Picture showing the transformer of the high voltage side

Current

Measurement

Voltage

Measurement Diode

Adjustable

Transformer

Starting

resistors

Circuit breaker

126

1s

1s2s

2s

F5

1s

1s2s

2s

F5 rL

H500

2x C

S241210

iv

115 V

ov

620 V

SKM200GBD123D

ivov

1s

1s

2s

2s

F20

rL

1s

1s

2s

2s

Cell 1

Cell 2

F20

H500

SK

M2

00

GB

D1

23

D

2x CS241210

115 V 620 V

Figure ‎5-7 Schematics of the experimental (a) Step-down and (b) step-up converters

127

Converter Parameter

5 KW converters connecting +115, +620 V dc buses

Step-down Step-up

Ai avi 8 44

Ai avo 43.5 8

FCr 2.5 10

rad 1.6732 2.3283

mHLr 0.5 0.5

Ai avL 43.5 44

Ai RMSC max 23 56

Ai RMSS max 16 40

Ai avS max 4 18

Ai pkS 80 104

sAdt

dion

S /| max 2.25 1.47

)/(| max sVdt

dvoff

s

15.9 5.2

Ai RMSD max 43.5 20

Ai avD max

35.5 8

Ai pkD

79 75.5

sAdt

dioff

D /| max

0.23 1.24

sf (Hz)

1300 1450

Table ‎5-11 Design parameters of the experimental converters

128

In contrast to iron core inductors, this inductor has low core losses (25 W or 0.5% at full load)

for the parameters shown in Table 5-11. In contrast to air-core inductors, this inductor uses less

amount of copper to give the same dc resistance. The inductor has a dc resistance of 15 mΩ and

uses Litz wire to minimize the skin and proximity effects. The inductor‘s dc resistance

contributes to 0.6 % of the converter‘s losses at full load.

The capacitors used are SCRN245R which has film-paper dielectric. Each capacitor unit has a

capacitance of 10 µF and rated for 100A RMS, 6.5 KVA. Several capacitor units are connected

into banks to give the required capacitance. These capacitors have over-rated values in order to

yield low losses.

Fig. 5-5 to Fig. 5-7 show the experimental waveforms obtained for the step-down converter.

Fig. 5-8 to Fig. 5-10 show the waveforms for the step-up converters. Table 5-12 show the

semiconductors parameters and Table 5-13 presents the loss analysis for both converters.

Figure ‎5-8 Step-down converter experimental waveforms. The figure shows the inductor

current on Ch1, the diode current on Ch4, the voltage of the capacitor of the first cell on

Ch2 and the voltage of the capacitor of the second cell on Ch3.

Li

Di

1Cv

2Cv

129

A good matching is observed between the experimental waveforms and theoretical ones

(presented in Chapter 2). We also note a small influence of the stray-inductance on the

waveforms as expected from section 4.7 in chapter 4. By inspecting the cell capacitors voltage of

Fig. 5-5 (for the step-down converter) and Fig. 5-8 (for the step-up converter), we note that the

total voltage is divided among the two switching cells equally. This means that the voltage stress

is shared equally between the switches of the converters. This can also be verified by observing

the voltage waveforms of the switches shown in Fig.5-6 (for the step down converter) and

Fig.5-9 (for the step-up converter).

The peak values of the voltages and currents are slightly higher than those stated in

Table 5-11 due to the stray inductance as expected. This can also be observed by inspecting the

limited rate of change in the diode current at switch-on instants, the limited rate of change of the

switches currents at turn-off instants (Fig.5-6, Fig.5-9), and the voltage across the active

switching networks (Fig. 5-7, Fig. 5-10) at these instants.


current on Ch1, the capacitors current on Ch4, the switch voltage vs1 on Ch2 and the switch

voltage vs2 on Ch3

Li

Ci

1Sv

2Sv

130

The high-frequency oscillations appearing on the voltage of the switches (Fig. 5-6, Fig. 5-9)

and diode voltage waveforms (Fig. 5-7, Fig. 5-10), are due to ringing between the output

capacitance of the diodes, and the stray inductance during the diode reverse recovery. As the

diodes have non-zero turn-off voltage, the reverse recovery charge causes these oscillations.

They are more obvious on the step-up converter as the diodes block higher voltage at turn-off

instants. These oscillations however, are almost negligible on the current waveforms of the

diodes due to the slow rate of change of the diode current at turn-off instants. These oscillations

can practically be damped with tuned diode snubber circuits, if required. This phenomenon is

reduced by using fast recovery diodes.

It is also noted that these oscillations do not appear at the turn-off instants of the switches

(despite having higher current rate of change at turn-off instants). This is because the active

switches experience zero voltage switching at turn-off. With this observation we conclude that

snubber circuits on the switches are not necessary.


current on Ch1, the diode current on Ch4, the diode voltage on Ch2 and the voltage of the

active switching network vc* on Ch3.

Li

Di

Dv

*

Cv

131

Figure ‎5-11 Step-up converter experimental waveforms. The figure shows the inductor

current on Ch4, the diode current on Ch1, the voltage of the capacitor of the first cell on

Ch3 and the voltage of the capacitor of the second cell on Ch2.

Semiconductor device VTO (V) rT (mΩ)

IGBT 1.75 14.125

IGBT‘s series diode 1.2 5.5

Equivalent per active switch 2.95 19.625

Converter‘s diode valve 1.2 18

Table ‎5-12 Semiconductor parameters for the conduction losses calculations

Li

Di

1Cv

2Cv

132


current on Ch4, the capacitors current on Ch1, the switch voltage vs1 on Ch3 and the switch

voltage vs2 on Ch2

Converter’s‎loss‎parameter Step-down Step-up

condp (active switch) (W) 97 476

condp (diode) (W) 65.5 11

Lp (copper losses) (W) 28.5 29

Total 191 516

% Efficiency (calculated) 96.2 % 89.7 %

Efficiency (experimental) 95.5 % 88.7 %

Table ‎5-13 Loss analysis of the converters

Li

Ci

1Sv

2Sv

133


current on Ch4, the diode current on Ch1, the diode voltage on Ch2 and the voltage of the

active switching network vc* on Ch3.

Li

Di

Dv

*

Cv

134

Figure ‎5-14 The efficiency of the experimental prototypes

Table 5-13 shows the loss analysis of the implemented converters. We note close matching

between the calculated losses and the experimental losses measured in the laboratory. The slight

deviation can be due to the unmodeled losses (switching losses, wiring losses, inductor core

losses, capacitor losses). Fig. 5-11 shows the efficiency curves against loading for the

experimental setups.

By observing the losses in Table 5-13, we note that the step-down converter has higher

efficiency than the step-up converter. This can be explained by noting that the average current in

the switches for the step-down converter is much lower than in the step-up converter. Since the

active switches in the experimental setup contribute to the majority of the converter losses, this is

to be expected.

135

Chapter 6 Conclusions and Future Work

6

6.1 Conclusions

In this thesis, a new family of dc-dc converters has been proposed for high voltage and high

power applications. The structure and operation principle was presented in chapter 2. It is

concluded that the proposed converters show structural modularity in the active switching

network with resemblance to classical (buck, boost, buck-boost) converters. The proposed

converters do not contain isolation transformers or coupled inductor and can be designed for

single or double pole dc systems. The converters operate only in DCM and enjoy self current

commutation, with potential use of thyristors as active switches. Active switches turn-off at zero

voltage, and turn-on at zero current to reduce switching losses. Common benefits of the entire

class converters are the utilization of both ZCS and ZVS through modular structure and equal

voltage distribution among the converter modules.The above combination of features is not

available in any other dc-dc converter topologies to date.

Mathematical analysis of the proposed converters was carried out. This resulted in a set of

design equations allowing accurate sizing of the resonant elements and semiconductor devices. It

was shown that the converters are frequency controlled with a linear relationship between the

frequency and average power. The value of the resonant capacitors was found to depend

particularly on the required power rating of the converter, at given values for the terminal

voltages and maximum allowable switching frequency. The value of the resonant inductor is

determined such that DCM operation is guaranteed at maximum switching frequency. The

switches and diodes in the proposed converters experience the same peak current and voltage

regardless of the average power throughput (or the operating frequency).

Several design examples were studied for the proposed converters. It was shown that, when

thyristors are used as active switches, the maximum operating frequency will be limited by the

minimum turn-off time of the thyristors (tq). This was found to influence the step-up converters

(especially the inverting step-up) more than the step-down converters especially at high voltage

step-up ratios. The step-down converters, however, experience higher rate of change at thyristors

136

turn-on instant, especially at high voltage step-down ratios. This can be limited by using higher

value for the resonant inductor, which would result in reducing the switching frequency.

It was observed that the non-inverting step-up and step-down converters (of similar power

rating) will have the same average inductor current. This shows that the inductor‘s copper losses

will be lower for the step down converter as smaller inductance is needed. The inverting step-up

and inverting step-down converters also have the same average inductor current but is higher

than the non-inverting converters. The current and voltage stresses for the inverting converters

were found to be higher than the non-inverting converters. This results in higher losses for the

inverting converters.

Experimental prototyping was implemented and studied in chapter 5. It is concluded that the

conduction losses are much higher than switching losses and have a major impact on the

efficiency of the proposed converters. The efficiency of the step-up converter is mainly affected

by the conduction losses of the active switches. This is due to the higher average current in the

active switches of the step-up converters. It is also concluded that the efficiency of the step-up

converters can be increased by choosing active switches with low conduction losses. The

efficiency of the step-down converters is affected by the losses in the diodes more than the active

switches. This is because the diodes carry higher average current.

The step-up converters can theoretically achieve high voltage stepping ratios. This ratio was

found to be limited by the resistive damping in the resonant circuit. It is also concluded that,

when high voltage stepping ratios are desired, lower efficiencies are achieved. This is because of

the higher semiconductor losses resulting from the use of larger number of power semiconductor

devices. This limits the practical voltage stepping ratio.

In general, the switching losses are much lower than the conduction losses in the proposed

converters. When thyristors are used as active switches, the range of semiconductor losses can be

lower than 2% for voltage stepping ratios of 5. When the voltage stepping ratio reaches 20, the

range of semiconductor losses can reach 6%. These losses were calculated for semiconductor

voltage utilization of at most 50%. These losses can be lowered by increasing the voltage

utilization of the semiconductor devices.

137

The impact of the stray inductance was studied. If the value of the stray inductance is low

(less than 2% of the resonant inductance), its impact is considered positive.

This is because it limits the rate of change of the diode‘s turn-on current and the thyristor‘s turn-

off current without significant impact on the performance. The stray inductance generally

elongates the commutation period. If its value is excessively high, this will increase the turn-off

voltage for the active switching increasing their switching losses. High stray inductance also

results in higher peak voltages and currents in the semiconductor devices.

Faults on the input side of the converters will not be supplied from the output side, as the

converters are power unidirectional devices. With the exception of the step-up converter, faults

at the output terminals of the step-down converter and the inverting converters can be prevented

from propagating to the input terminal of the converter by suppressing the gating signals.

The converters may utilize air-core inductors, iron-core inductors or ferrite-core inductors.

The use of air-core inductors implies much larger size than iron-core or ferrite-core inductors but

no core-losses. It is understood that mechanical design aspects for this type of pulsed-current

inductors is challenging, compared with CCM hard-switched converters.

6.2 Thesis Contributions

The major original contributions of this thesis:

1. New family of dc-dc converters for high power and high voltage applications was

developed. Namely: modular step-down converter, modular step-up converter, modular

inverting converter, and several modular bidirectional converters derived from these

topologies. The converter‘s switches turn-off at zero voltage and require no active

voltage sharing during switching.

2. Design equations for the proposed converters were derived to size the semiconductor and

resonant devices.

138

The following minor contributions have been presented in this thesis:

1. Quantifying the influence of the minimum turn-off time of thyristors on limiting the

switching frequency of the converters.

2. Semiconductor loss analysis of the proposed converters.

3. The effects of the circuit non-idealities were studied.

4. Experimental validation of the modularity concept in dividing the voltage stresses

between low-voltage capacitors and active switches.

6.3 Suggested Future Work

Table 6.1 draws general comparisons between all available dc-dc converters families. The

proposed topologies belong to the transformerless soft-switched converters. To move this study

from theory to practice, the following work is suggested for the future as an extension to this

thesis:

1. Develop small signal dynamic model for each of the proposed converters.

2. Study the effect of the proposed converters on the dynamic stability of the dc grids.

3. Study the feasibility of using the proposed converters on specific high power and high

voltage applications (e.g. high power drives, off-shore wind farm, and HVDC power

taps).

4. Implement the proposed converters on higher power and voltage ratings using light

triggered thyristors.

139

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144

Appendix A

Voltage gain for passive loads

The modeling done in the thesis assumed the converters operate with a constant voltage stepping

ratio. This ratio is fixed and is determined by the voltage level of the input and output buses. To

relax this condition, a passive network can replace the output voltage source as seen in

Fig.A-1.

outfC ovov

+

-

LRDC-DC

Converter

DC-DC

Converter

Figure A-1 Connecting the converter terminals to a passive network

For the network in Fig. A-1, the power injected into the load is expressed as:

L

oL

R

vp

2

(A.1)

where RL represents the load resistance. The capacitor Cf out shown in Fig.A-1 is an output

filtering capacitor. Equating (A.1) with (3.10), (3.18) and (3.22) gives expressions of the voltage

ratios for the step-down, step-up and inverting converters as follows:

145


srL

i

o fCRv

v2 (A.2)


Lsri

i

o RfCvv

v41 (A.3)


kkkv

v

i

o 122 (A.4)

where srL fCRk , and that vi and vo have opposite polarities. From the previous relations, the

following comments can be made:

In case of passive output buses, the voltage gain of the proposed converters varies with

the load; linearly for the step-up converters and nonlinearly for the step-down and the

inverting converters.

Voltage regulation of a passive output network is achieved by varying the switching

frequency to maintain the product RL fs constant.

Suppressing the gating signals (i.e. fs = 0) blocks power transfer from the input to the

output buses ONLY for the step-down and the inverting converters. In case of step-up

converters, suppressing the gating signal will maintain the input voltage at the load

terminals.

146

Appendix B

Derivation of the maximum step-up ratio

The maximum theoretical voltage step-up ratio (of step-up dc-dc converters) depends on the

damping in the resonant circuit. In this case, the resonant circuit (composed of series RLC)

operates in the under-damping mode and the inductor‘s current will be given by:

teCteCti d

t

d

t

L sincos)( 21

(B.1)

where rr

ood

r CLL

r 1,,

2

22 , C1 and C2 are constants can be evaluated

from the circuit‘s initial conditions as follows:

1)0( CIi oL (B.2)

teCteC

teIteIdt

tdi

dd

t

d

t

dd

t

od

t

oL

cossin

sincos)(

22

(B.3)

From (B.3) the inductor‘s initial voltage can be expressed as:

2)0( CILv doL (B.4)

And from the circuit configuration, the same voltage can be expressed as:

rIvvv ocoiL )0( (B.5)

and the constant C2 can be evaluated from (B.4) and (B.5) as:

L

rIvvIC ocoi

o

d

12 (B.6)

Also the expression of the damped resonant capacitor‘s voltage can be expressed from the circuit

configuration as:

147

ridt

diLvv L

Lic (B.7)

Substituting from (B.3) into (B.7) gives:

riteICLteCILvv Ld

t

dod

t

doic sincos 22 (B.8)

Since the converter operates in DCM, 0oI , this yields the following:

L

vvC coi

d

12 (B.9)

teCi d

t

L sin2

(B.10)

Substituting (B.9), (B.10) into (B.8) and re-arranging yields:

rietvvvv L

t

d

dcoi

d

oic

1tancos (B.11)

at max,0,2

vvvriT

t cocLr

Dvvvv i

d

oi .maxmax

(B.12)

and the maximum voltage stepping ratio would be:

D

D

v

v

od

od

i

max

(B.13)

Where D is a negative quantity equal to:

r

rr

rrr

r

dr

rrd

T

d

rd

L

crT

L

r

cLL

r

L

crTe

TD

r

22,

4

12

,4

12

,tan2

cos2

2

21

148

Appendix C

The stray inductance

The influence of the stray inductance was presented in section 4.7 of chapter 4 through

simulation models. Here we will analytically study the influence of the stray inductance and

derive the diode current expression of (4.29). For this purpose, we will consider the non-

inverting step-up converter of Fig. C-1. Generally the stray inductance exists as a resultant of the

inductances of the bus-bars, capacitors, semiconductor devices, etc. The major part of this

inductance results from the active switching network. For this purpose Fig. C-1 places a series

inductance Lc in series with the active switching network to model the stray inductance. The

corresponding waveforms of the resonant capacitor voltage and the currents in the switches are

shown in Fig. C-2. We note that the commutation period lasts from tr to tr . For this

circuit during the interval tr0 :

t

C

LL

vvi r

r

cr

coii sin

(C.1)

tvvvv rcoiic cos

(C.2)

tvvLL

Lv rcoi

cr

rrL cos

(C.3)

tvvLL

Lv rcoi

cr

ccL cos

(C.4)

where rcr

rCLL

1

.

149

ivov

rL

ii

D

rC

cL

oi

Figure C-1 Step-up converter with a stray inductance in series with the active switching

network

Figure C-2 Current and voltage waveforms of the converter with the stray inductance

Curr

ents

of

the

swit

ches

and d

iodes

R

esonan

t ca

pac

itor

volt

age cov

0

cov

pkSi

tr

0

cv

150

During the interval tr :

orLi vvv

(C.5)

ccLo vvv

(C.6)

Equation (C.5) yields the following:

dt

diLvv i

roi

(C.7)

which can be solved to give the expression of the input current as follows:

rr

oi

r

cr

coii t

L

vv

C

LL

vvi

sin

(C.8)

Equation (C.6) yields the following:

02

2

r

icc

C

i

dt

diL

(C.9)

which can be solved to give the expression of the capacitor current as follows:

r

cco

c

r

r

c

r

cr

coic tvv

L

Ct

C

LL

vvi

sincossin

(C.10)

where cv is the capacitor voltage at and rcc CL/1 ..The final expression of the diode

current results from subtracting the capacitor current of (C.10) from the input current (C.8) and

results in:

151

rccco

c

rrcc

rcr

coi

rr

oi

rcr

coiD

tvvL

Ct

CLL

vv

tL

vv

CLL

vvi

/sin/cossin/)(

sin/)(

(C.11)

In case of significant stray inductance, or the insertion of intentional commutating inductance,

the voltage increase on the capacitor due to commutation over-charge will cause significant

increase in the converter‘s power. As a result, the power relations of (3.10), (3.19) and (3.23) and

the value of the filtering capacitors in (4.13)-(4.18) can be re-written as follows:


ipkcsri vvfCP *4 (C.12)

i

pkcr

inputfv

vCC

*2

(C.13)

io

pkcir

outfvv

vvCC

*2

(C.14)


io

pkcoisr

ovv

vvvfCP

*4 (C.15)

ioi

pkcor

inputfvvv

vvCC

*2

(C.16)

ioo

pkcir

outfvvv

vvCC

*2

(C.17)

152


ipkcsri vvfCP *4 (C.18)

i

pkcr

inputfv

vCC

*2

(C.19)

io

pkcir

outfvv

vvCC

*2

(C.20)

153

Appendix D

Bidirectional single-inductor converter design

The design of this converter starts by specifying the values of the capacitors and the inductor

for the step up operation. The maximum switching frequency of the step up converter should

maintain adequate turn-off time for thyristors, if used. Next, the step down converter will be

designed starting from the value of the inductor specified earlier. Given the inductor value, the

capacitors and the maximum switching frequency can be specified. In this case, the switching

frequency for step down operation will be different from the step up operation for the same

power. Table 5-9 shows the design results for a 120 MW bidirectional converter connecting ±33,

±150 kv dc buses.

LVv

HVv

HVv

LVvupD

uprC

uprC

upD

dwnD

dwnD

rL

uprC

uprC

LVfC

LVfC

HVfC

HVfC

Figure D-1 Bidirectional single inductor converter topology

154

Converter Parameter

120 MW bidirectional converter connecting ±33, ±150 KV dc

buses

up down

No. Cells / valve 48

No. series diodes/ valve

163

Lr (mH) 20.58

rad

2.3384 1.67

Fcrn 91.714 91.1

kvvrnc

3.81 3.81

fs (Hz) 650 288

Ai avS max 904 200

KAi pkS 4.21 4.52

sAdt

dion

S /| max 20.98 33

Ai avD max

400 1818

KAi pkD

2.99 4.5

sAdt

dioff

D /| max

14.58 3.2

Table D-1 Design parameters of the bidirectional converter

From observing the above parameters, we note that the values of the resonant capacitor per

converter cell for both converters are very close. Because a single inductor is used for both

converters running at the same power rating, the rated switching frequency is different for both

converters. Generally, the step-down converter will have to operate at much lower frequency

than the step up converter when they share the same resonant inductor.

155

Appendix E

Final design parameters

Converter Parameter 6 MW converters connecting ±1.5, ±7.5 KV dc buses


Ai avi 400 2000 2000 400

Ai avo 2000 400 400 2000

FCC rr , 17.78 71.11 85.47 13.889

rad 1.6821 2.3 2.3664 1.6618

mHLL rr , 0.1599 0.3864 0.468 0.1247

Ai avL 2000 2000 2400 2400

Ai RMSC max 1200 2262 2752 1313

Ai RMSS max 849 1600 1946 929

Ai avS max 200 800 1000 200

KAi pkS 4.554 3.91 4.487 5.3822

sAdt

dion

S /| max 84.4 23.3 35.26 132.33

)/(| max sVdt

dvoff

s

137 9 17 137

Ai RMSD max 2153 861 905 2642

Ai avD max

1600 400 400 2000

KAi pkD

4.526 2.91 3.14 5.36

sAdt

dioff

D /| max

10.24 16.9 16 12.2

sf (Hz) 800 800 650 850

max|abssf (Hz)

828 820 678 873

Table E-1 Design parameters for the converters of the first design example

156

Converter Parameter



Ai avi 455 2000 2000 455

Ai avo 2000 455 455 2000

FCC rr , 4.304 14.635 18.993 3.301

rad 1.6994 2.2519 2.3288 1.673

mHLL rr , 0.7194 1.55 2.0578 0.5537

Ai avL 2000 2000 2455 2455

Ai RMSC max 1278 2234 2794 1415

Ai RMSS max 904 1580 1976 1001

Ai avS max 227 771 997 227

KAi pkS 4.524 3.935 4.611 5.674

sAdt

dion

S /| max 81.3 26.13 23.32 132.7

)/(| max sVdt

dvoff

s

117 30 22 156

Ai RMSD max 2116 941 999 2668

Ai avD max

1545 455 455 2000

KAi pkD

4.487 3.06 3.35 5.64

sAdt

dioff

D /| max

10.4 16.45 16 13.54

sf (Hz) 800 800 650 850

max|abssf (Hz)

820 851 685 870

Table E-2 Design parameters for the converters of the second design example

157

Converter Parameter



Ai avi 400 1818 1818 400

Ai avo 1818 400 400 1818

FCC rr , 0.8333 2.9545 3.8213 0.6429

rad 1.6947 2.2644 2.3384 1.67

mHLL rr , 3.498 7.76 10.29 2.704

Ai avL 1818 1818 2218 2218

Ai RMSC max 1142 2037 2530 1262

Ai RMSS max 807 1440 1789 893

Ai avS max 200 709 904 200

KAi pkS 4.121 3.571 4.162 5.134

sAdt

dion

S /| max 76.33 23.58 20.98 123.16

)/(| max sVdt

dvoff

s

127 31 23 166

Ai RMSD max 1928 836 886 2420

Ai avD max

1418 400 400 1818

KAi pkD

4.09 2.756 2.99 5.11

sAdt

dioff

D /| max

9.4 15.08 14.58 12.2

sf (Hz) 800 800 650 850

max|abssf (Hz)

822 842 682 872

Table E-3 Design parameters for the converters of the third design example

158

Converter Parameter



Ai avi 100 2000 2000 100

Ai avo 2000 100 100 2000

FCC rr , 0.238 5.278 5.291 0.2442

rad 1.596 2.702 2.712 1.595

mHLL rr , 0.9625 10.125 10.114 1.011

Ai avL 2000 2000 2100 2100

Ai RMSC max 605 2377 2496 615

Ai RMSS max 428 1680 1765 435

Ai avS max 50 950 1000 50

KAi pkS 4.6 3.596 3.774 4.778

sAdt

dion

S /| max 304 15.55 16.314 304

)/(| max sVdt

dvoff

s

496 17 17 477

Ai RMSD max 2354 309 313 2453

Ai avD max

1900 100 100 2000

KAi pkD

4.6 1.53 1.57 4.77

sAdt

dioff

D /| max

7.8 14 14.83 7.4

sf (Hz) 700 600 600 650

max|abssf (Hz)

878 627 607 895

Table E-4 Design parameters for the converters of the fourth design example

159

Converter

Parameter




No. series diodes

7 7 8 8

Fcrn 33.334 133.334 256.41 41.667

kvvrnc

3.75 3.75 3 3

Converter

Parameter



No. series diodes

30 30 36 36

Fcrn 38.736 131.715 104.464 36.311

kvvrnc

3.67 3.67 3.68 3.68

Converter

Parameter


No. Cells / pole 39 39 48 48

No. series diodes

134 134 163 163

Fcrn 32.5 115.2255 91.714 30.858

kvvrnc

3.85 3.85 3.81 3.81

Converter

Parameter


No. Cells / pole 39 39 41 41

No. series diodes

267 267 280 280

Fcrn 9.282 205.45 216.931 10

kvvrnc

3.85 3.85 3.84 3.84

Table E-5 Comparison between design parameters of the proposed converter for the four

design examples

160

Appendix F

Power controller design

From the analysis in chapter 3, the steady-state power was proven to vary linearly with the

switching frequency. This is demonstrated by the relations (3.10), (3.18) and (3.22). In practice,

controlling the frequency may require the use of phase locked loop (PLL) which adds complexity

to the system. Alternatively, the DCM operation allows regulating the discontinuous off delay

interval of the inductor‘s current as an indirect way to control the frequency.

Fig. F-1 shows a schematic to the firing signal modulator of the switches. A timer is used to

apply the required off delay interval to the inductor‘s current. This timer is triggered by the

falling edge of the inductor current signal. The system may require a start up signal which is

generated independently till the black start-up process ends. Upon the detection of a fault

condition, a fault signal is generated to stop firing the switches.

The discontinuous off delay interval t0 can be calculated every half switching period

according to the required power reference. From the inductor‘s current relations in (3.32), (3.34),

(3.36), and the power relations in (3.10), (3.18), (3.22), the following expressions are derived:

Timer

Switches

Driver

Start-up

signal gen.

Reset

Li

Off delay interval

Fault Signal

0t

Figure F-1 Firing signal modulator

161


io

o

io

o

o

oirr

refo

irref

vv

v

vv

v

v

vvCL

P

vCt

2cos

2cossin

22 112

0 (F.1)


oi

oi

oi

oi

io

oirr

refoio

oirref

vv

vv

vv

vv

vv

vvCL

Pvv

vvCt 11

2

0 coscossin2

(F.2)


io

o

io

o

o

oirr

refo

oiirref

vv

v

vv

v

v

vvCL

P

vvvCt

2cos

2cossin

22 11

0 (F.3)

Equations (F.1)-(F.3) assumes lossless converter. An additional feedback current regulator

can be used to compensate for the losses and improve the transient dynamics of the system. This

is shown in Fig.F-2, where Gc is based on either (F.1), (F.2) or (F.3). A saturation block is added

to the regulated off delay time in order to satisfy the conditions (4.30), (4.31) and (4.32). A low

pass filter is used to produce the average output current and reduce the switching harmonics. A

PID controller is tuned to regulate the output current dynamics.

oi

refot+

+-

+

LPF

refoP

ov

1PID

cG

refoi

ot

Figure F-2 Power controller schematic

162

iv

ov

ov

iv

rL

rC

rC

ii

ii

oi

rL

D

D

oi

fL

fL

outfC

outfC

Figure F-3 The inverting step-up converter with an output filter

Fig. F-3 shows the inverting step-up converter circuit including an output filter. This circuit is

simulated with the controller proposed earlier. The simulation parameters are shown in table F-1.

The parameters of the circuit are based on the third design example of table E.3 (120 MW

converters connecting ±33, ±150 KV dc buses). Simulation results are shown in Fig. F-4. The

reference power was given as a step of 120 MW. This corresponds to a reference output current

of 400A. A fault with a resistance of 1 Ω is applied on the output terminals of the converter at

t = 0.016 sec. after the output current has reached steady-state.

By inspecting Fig. F-4, we note that the output current dynamics has been successfully

regulated by the controller and reached steady-state at t = 0.013 sec. This can be verified by

inspecting the controller input and output of Fig. F-5. The regulated off-delay time to is also

shown in Fig. F-5 and can be observed by noticing the frequency variation of the input current

and capacitor cell voltage of Fig. F-4.

Upon the application of the fault, a rapid rise in the output current and a decay for the output

filtering capacitor voltage can be observed. The controller responds by suppressing the firing

signals of the switches. This causes the input current to reach zero at t = 0.018 sec. Therefore,

the output fault is not supplied from the converter‘s input.

163

Figure F-4 Simulation results for the (a) output current, (b) filtering capacitor voltage, (c)

input current and (d) cell capacitor voltage

Outp

ut

curr

ent

(A)

Fil

ter

capac

itor

volt

age

(V)

Input

curr

ent

(A)

Cel

l ca

pac

itor

volt

age

(V)

outfCv

oi

ii

crnv

164

Figure F-5 Simulation results of the (a) error signal of the controller, (b) controller output

and (c) the continuous off-delay interval to

Cf out + / Cf out - 38 µF Proportional gain 1.2 *10-6

Lf + / Lf - 12.5 mH Integral gain 98*10-6

Controller sample time 50 µs Derivative gain 0

Table F-‎6-1 Simulation parameters

Contr

oll

er i

nput

(err

or

signal

) C

ontr

oll

er o

utp

ut

Off

-del

ay t

ime

ot

A NEW FAMILY OF TRANSFORMERLESS MODULAR … A New Family of Transformerless Modular DC-DC Converters...

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Transcript of A NEW FAMILY OF TRANSFORMERLESS MODULAR … A New Family of Transformerless Modular DC-DC Converters...