IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 36, NO. 5, MAY 1989 695

A Neural Net Approach to Discrete Hartley and Fourier Transforms

ANDREW D. CULHANE, MARTIN C. PECKERAR, MEMBER, IEEE, AND C. R. K. MARRIAN

Abstracr-In this paper we present an electronic circuit, based on a neural (i.e., multiply connected) net to compute the discrete Fourier transform. We show both analytically and by simulation that the circuit is guaranteed to settle into the correct values within RC time constants (on the order of hundreds of nanoseconds), and we compare its performance to other on-chip DFT implementations.

I. INTRODUCTION HE discrete Fourier transform (DFT) is encountered T frequently in signal processing, and in general, the

faster one can do it, the better. Sequential techniques, such as a brute force DFT or the more efficient fast Fourier transform (FFT), regardless of whether they are imple- mented in hardware, software, or firmware, have the limi- tation that they usually do not operate on the entire vector of sampled data simultaneously. As vector length N in- creases, so does processing time. A brute force DFT is O ( N * ) and the FIT is O ( N log, N ) . Even when imple- mented in a parallel architecture, such algorithms are still sequential in that their performance consists of step fol- lowing step following step, etc. The architecture of the neural net suggests that a DFT net could operate on entire vectors simultaneously, and, therefore, each component of the transformed vector might be made to settle into its correct value with a simple RC time delay. A neural net designed to perform DFT’s would, therefore, reach a solu- tion in a time determined by RC time constants, not by algorithmic time complexity, and would be straightforward to fabricate.

We were led to consider neural nets to perform the DFT by the work of Tank and Hopfield [1], and that of Marrian and Peckerar [2]. Tank and Hopfield showed that a neural net could perform linear programming, that is, minimizing a cost function subject to a constraint. They showed that a linear programming neural net has associated with it an “energy function,’’ which the net always seeks to minimize. The energy function decreases until the net reaches a state

Manuscript received Jul 13, 1988; revised October 27, 1988. This paper was recommended 8y Guest Editors R. W. Newcomb and N. El-Leithy.

A. D. Culhane is with the U.S. Department of Defense, Fort Meade, MD 20755.

C. R. K. Marrian is with the U.S. Naval Research Laboratory, Wash- ington, DC 20375.

M. C. Peckerar is with the US. Naval Research Laboratory, Washing- ton, DC 20375, and also with the University of Maryland, College Park, MD 20742.

IEEE Log Number 8826716.

where all time derivatives are zero. Marrian and Peckerar then showed that this energy function could be manipu- lated so that, in minimizing the energy function, the net acted to solve the deconvolution problem, that is, recon- structing the original value of data convolved with a known system transfer function. This was essentially a net which solved a linear system. Since the known data could be corrupted by noise, they included a regularizer based on the concept of maximum entropy, to improve the solution.

We have investigated how to modify this deconvolution net so that it will calculate DFT’s. We have made use of the discrete Hartley transform (DHT) [3], which can be implemented in Marrian and Peckerar’s net. This is possi- ble because the Hartley transform matrix is not only guaranteed to be nonsingular, it equals a constant times its own inverse, as will be shown. The DFT and the DHT are equivalent representations of the frequency-domain behav- ior of a signal. From either, one can derive the other.

We note that it has been suggested that neural nets are inadequate both for deconvolution in general and for the Fourier transform in particular [4]. In arriving at this conclusion, Takeda and Goodman [4] included four key assumptions: (1) each time a neural net is used, it must spend some time in a learning phase before computing its answer; (2) numeric representation in a neural net must be done within the same limitations as numeric representation in a digital computer; (3) because of (2), the final outputs of the artificial neurons must be either 0 or 1; and (4) neural nets operate in a discrete mode, and must be simulated as such. These assumptions lead naturally to the concept of “programming complexity,” which implies that a Fourier transform neural net would spend so much time in its learning phase that it could not perform a transform with adequate speed. Inherent in these assumptions is a view of neural nets as digital systems. By considering nets as analog systems, we avoid these assumptions, and we do not encounter the problem of “ programming complexity.”

The circuit we will present is composed of two blocks, as shown in Fig. 1. The first block is a neural net which computes the DHT, and the second block is a bank of adders which compute the DFT from the output of the first block. A brief outline of the paper follows. In Section 11, we present mathematical preliminaries to an under- standing of the DFT circuit. We define the Hartley trans- form, paying particular attention to the characteristics of the Hartley transform matrix D. We also show how to

0098-4094/89/0500-0695$01.00 01989 IEEE

696 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 36, NO. 5, MAY 1989

S i g d plane consnaint plane

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(b) Fig. 1. (a) Block 1 using N = 2. (b) Block 2.

derive the DFT from the DHT and vice versa. In Section 111, we show the circuit for computing the DHT, and from it the DFT. For the ideal case, we give a proof that the neural net portion of the circuit is guaranteed always to settle into a value arbitrarily close to the correct DHT of the input data, and we gve expressions for the conver- gence time and the error. We then investigate the non-ideal case, concentrating on the departures from ideality that we can expect in a VLSI implementation, and we show that under reasonable conditions, a very good solution is still guaranteed. In Section IV, we give results from simulations of the net which demonstrate the speed and accuracy with which it settles into the correct results. In Section V, we contrast our results with those of other on-chip DFT implementations, and we discuss tradeoffs of our imple- mentation. In Section VI, we summarize the paper, draw conclusions, and consider future work.

11. MATHEMATICAL PRELIMINARIES In this section, we review the definition and characteris-

tics of the DHT, and its relation to the DFT. We also review the behavior of the Tank and Hopfield linear programming neural net, and, as an introduction to Sec- tion 111, we briefly discuss why the DHT is so easy to evaluate using this net.

A . The Discrete Hartley Transform

where

N number of sampled points, r v b the sampled data, U the DHT of b

a discrete variable representing time, a discrete variable representing frequency,

and we use Hartley's cas function, defined as cas(x) =

cos(x)+sin(x). The DHT and the inverse DHT can be expressed as

matrix products, by writing

U = D-'6 and b = Du (2)

where D = the matrix with Dij = cas(2lrij/N). ( D is thus an N-by-N matrix, whose indexes i, j run from 0 to N - 1.) There are three characteristics of this matrix that we will find useful. First, notice that D = DT since i j = ji. Second, due to the orthogonality condition

N - l 2 m i j 2mijf cas - cas - = NS,,,

N N i = O

given in [4], D 2 = NI, where I is the N by N identity matrix. To see that this is so, observe that element mn of the matrix D 2 is

N - 1 2lrmj 2lrnj cas-cas-

j = O N N

which is simply N if m = n and 0 otherwise. Third, the matrix D has only two distinct eigenvalues: *fi. If we let z be an eigenvector of D, then the corresponding eigenvalue A can be found as follows:

Dz = Az D2z = ADZ = A2z

N I ~ = A ~ ~ ; :. A ~ = N ; :. ~ = k f i

where we again make use of the property D 2 = NI. T h s also means that 11D112 =fi and that )1D-1112 =

I/n, which we will use when we investigate the non-ideal case.

Finally, given the DHT, the DFT can be uniquely derived from it, and vice versa. The DHT can be broken into two parts, called E ( v ) and O(v) (meaning even and odd, respectively), as follows:

U( V ) + U( N - V ) E ( v ) = ( 3 4

The DHT of a set of sampled data, and its inverse, are - u(Y)+ u ( N - Y )

2 (3b) defined as follows: o(v) =

(la) Since u(v) is clearly periodic in v with period N, we have u(N) = u(0). Noting that the cas(.) function has the prop-

N - 1

b ( 7 ) = 1 u(v)cas v = o

erties that

2mij 2 m ( N - i ) j 2mij = 2cos -

N cas - + cas N N

CULHANE et al. : HARTLEY & FOURIER TRANSFORMS 691

-ao -al -a2 -bo -b1 -b,

vo v1 v2 $ 0 $ 1 $ 2

Fig. 2. The linear programming neural net.

and

2Tij 2 ~ ( N - i ) j 2Tij - cas - + cas = -2sin -

N N N

and noting that the DFT of a function b ( r ) is defined by

jsin - N

it is easy to see that E ( v ) is the real part of f(v) and that O ( v ) is the imaginary part. That is, if we know the DHT of b, then

f(v) = E ( v ) + j O ( v ) ( 4 4

and conversely, if we know the DFT of b, then

We will use all of these characteristics of the DHT when we describe the time evolution of the neural net block of the circuit. We next review the Tank and Hopfield linear programming neural net.

B. The Linear Programming Neural Net The Tank and Hopfield linear programming neural net,

It has been shown by Tank and Hopfield [ l ] and by Pati from [l], is shown in Fig. 2.

et al. [ 8 ] that t h s network minimizes the expression

( 5 )

f constraint amplifier function, F indefinite integral of f, g signal amplifier function,

' i output voltage of signal amplifier i , a and b input currents to signal and constraint planes, RI resistance at input of signal amplifier i .

The first term in the expression represents a cost. The second term represents a measure of constraint violation. The third term can be tailored by manipulating the ampli- fier function g. It can be made negligible as in [ l ] , or it can be used to include a regularization term as in [2] and [8 ] .

A brief summary of the net's behavior is: (1) E is bounded from below and ( 2 ) E is nonincreasing (i.e., dE/dt G 0), with dE/dt = 0 only when dul/dt = 0 for all i . Therefore, E must reach a minimum. If the second term in the expression is positive, and if the third is negligible, then the net acts to minimize the cost term whde trying to push the constraint violation to zero.

It is this second term that attracts our attention for solving the Hartley transform. It is, in a way, a norm of the vector Du - b. The net tries to drive this norm as close to zero as possible, essentially solving the matrix equation Du = b. We know that a unique solution exists because we know that D-' exists. This suggests that if we can make the other two terms in the expression zero or small, then the neural net will compute the DHT. We now demon- strate how to do that.

111. IMPLEMENTATION As stated in Section I, our circuit consists of two blocks,

shown in Fig. 1. Block 2 is simply a bank of adders, whose purpose is to form the even and odd parts of the DHT (hence the real and imaginary parts of the DFT) from the outputs of Block 1. Block 1 is the neural net, whose operation we now describe.

A . Block 1: The DHT Neural Net We begin with Tank and Hopfield's linear programming

neural net, shown in Fig. 2, and our goal is to manipulate its energy function so that it will compute DHT's. First, following the example of Marrian and Peckerar, we use our transform kernel D (from Section 11-A) as the inter- connect conductance matrix. We use the vector b of sam- pled data as the constraint amplifier input currents. We set a to zero. For the signal amplifiers, we use g( U ) = f lu ( P is dimensionless, U has units of voltage). For the constraint amplifiers, we use f ( z ) = az ( a has units of resistance, z has units of current). This gives F ( z ) = ( a / 2 ) z 2 , so that the energy function is now

with all Ri's set to the same value R . The first term is minimized as U approaches the solution

Dutme = b. At that unique vector, the first term in ( 6 )

698 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 36, NO. 5, MAY 1989

-Doi -D -D -D vi= pui Kirchoffs current law gives

C - = - ( R + F D , , , i . dui ui dt 0, 0 , 0 N 4 0,,

-ai -s-, (4 Expressing this in matrix notation, using D = D', and

observing that the vector I+ = a(Du - b ) , we have

-O0 -01 -

+ or, equivalently

du 1 a p N a (7) _ - - - ( E + 7) u + Z D b

dt

where we have used D 2 = N I (in units of conductance2) and Iu = U. This system has an exact solution, which is

Fig. 3. (a) The input to signal plane amplifier i . (b) The implementation of weights.

equals zero. The second term is minimized as R or p becomes large or as U becomes small.

We now have a circuit which seeks a minimum near the solution vector utne. We next prove that the circuit will always converge to a vector arbitrarily close to utNe.

Note that we have sidestepped the first, second, and third of the assumptions mentioned in Section I. The interconnect matrix D is not dynamic. Once fabricated, it does not change, so the net has no learning phase. (We point out that this is no disadvantage-the net has no learning phase because its architecture is such that it always "knows" how to perform a DFT, an extremely useful operation.) Also, we use the simple numeric repre- sentation that the ith signal voltage equals the ith point in the solution vector. This means that each neuron's output can take on any value in the range Juil G fi (assuming that b is normalized so that lbil d 1).

B. Block 1: Dynamic Circuit Behavior 1) The Ideal Case: We now analyze the continuous behavior of the net,

noting that this allows us to avoid the fourth of the assumptions noted in Section I.

Fig. 3(a) shows the input to signal amplifier i. We introduce the notation +j for the output voltage of con- straint amplifier j , thus +, = f(CiDjiui - b,) = a(CiDjiuj - bj). As in (6), we let all Ri's equal the same value R . Also, we point out that the Di,'s are not meant as simple conductances, but rather as weights.'

a U f i n a ~ = 1 Db

a p N + - R

where uo is the initial state of U. The time constant of this equation is

For apNR >> 1, ths simplifies to r = ( C / a b N ) (where, again, N has units of conductance2, since it comes from the product D 2 ) . This is an intriguighg time constant. First, it does not depend on the input resistor R if R is large. Second, as N , the number of sampled points goes up, 7 goes down.2 Solution time will actually be faster when transforming longer vectors, because the matrix product D 2 gives us a factor of N in the denominator.

Now, as t becomes large, U settles into the vector uf ind . Therefore, using D = ND-' and utNe = D-'b = 1 / N Db, we know that u ( t ) = p u ( t ) settles into the vector urinal = Pufind, whch is

(9) Upl. T

R

Finally, the error between ufinal and U,,, is

*This may seem counter-intuitive, but it is a straightforward conse- quence of viewing the net as an RC circuit. The higher we make N , the more parallel resistances we connect to each amplifier's input, the lower we make the effective resistance, and the smaller we make the RC time constant. It is worth commenting that this derivation is based on the ideal assumption that the constraint amplifiers have no delay. In any real circuit, they will have delay, and we can't make the solution settle faster than the fastest amplifier. In the next section we will derive bounds for the time constants in the non-ideal case.

iThe distinction is this: a conductance between +, and A weight D,,~lfrom voltage +, to v;ltage carries a current D,, (4 -

injects a current D t~ into the node whose voltage is U,. A circuit realization of this Co'ddPt is shown in Fig. 3(b). The virtual ground input of the additional amplifier cause all D,i's to be connected between +j and ground. The high input impedance of the amplifier causes the resulting currents to flow into the RC pair.

CULHANE et al.: HARTLEY 8z FOURIER TRANSFORMS 699

which can be made arbitrarily small by using large enough a, p, or R . Qualitatively, increasing a increases the weight given to the first term in (6) and increasing p or R decreases the weight given to the second term. Quantita- tively, increasing any of these has the effect of moving the minimum of the E function closer to the vector qme. Note that the convergence and the error do not depend on u0.

2) The Non-Ideal Case - Theory There are two important departures from ideality which

we can expect when we fabricate a neural net on an integrated circuit. First, a real constraint plane will have an RC delay. Second, the conductance matrix will not exactly match D .

To account for these non-ideal conditions, we first intro- duce the following notations.

R g , C g

R,, C,

Dg, D,

pg, p,

ug, U,

ug, U,

Resistor and capacitor at the signal amplifier input. Resistor and capacitor at the constraint ampli- fier input. Approximations to D at the signal and con- straint planes, respectively. Signal and constraint amplifier gains, respec- tively. Signal and constraint amplifier input voltages, respectively. Signal and constraint amplifier output voltages, respectively.

Just as there are two sources of non-ideality, there are two important consequences. First, since the neural net is a feedback system, it may oscillate instead of settling into a final result. Second, even if it does settle, the error due to the non-ideality may be unacceptable. Accordingly, we will first demonstrate a sufficient condition for non-oscillation. We will then derive an expression for the error in the result.

Using the notation given above, it is easy to see that the non-ideal neural net, in partitioned matrix form, is a linear system with the following differential equation:

where r, = R,C, and rg = RgCg, and we assume that r, << ?S.

It is a well-known fact of linear systems that if the eigenvalues of the system matrix M (the 2N by 2N matrix above) are all real and positive (i.e., the matrix is positive definite), then the net will settle into a solution rather than oscillating (see e.g., [9, theorem 4.11). We will now show

that if the matrix product DgD, is positive definite, then so is the system matrix.

We consider the matrix A , which is defined as follows:

12N is the 2N by 2 N identity matrix and 0 is the N by N zero matrix. Clearly if A, is an eigenvalue of A , then A, = (l/r,)(l + A,) is an eigenvalue of M .

Now let [ ;] be an eigenvector of A with eigenvalue A,. Then

Solving for z, in terms of zg and substituting back in gives the equation

This means that z, is an eigenvector of DgD,, and that the lengthy product on the right is the corresponding eigenvalue. We have already assumed that all the eigen- values of DgD, are real and positive. Therefore, A; + A,(l- ( r f / rg) ) < 0, and it follows that - (1 - ( r,/rg)) < A, < 0, and, therefore, A, lies in the range ( l / r g , l / r f ) . Therefore, the system is non-oscillatory and exponentially settles into a solution. (It is also worth noting that this clarifies that no element of the solution vector can have a time constant faster than the fastest amplifiers, i.e., no A is greater than l/~,. So while we expect solution time to improve with increasing N , as seen in the previous section, there is a limit).

Now knowing that the system does not oscillate, it is simple to find its final state, by just solving for [ :] when

( d / d t ) [ :] = 0. The result is

4 q D g 1 - I

- 1

and the inverse is guaranteed to exist since zero is not an eigenvalue of the matrix. Using the theory of partitioned inverses, we have

700 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 36, NO. 5 , MAY 1989

where c a 2"' N

(and since DgDJ is positive definite, so is DJDg, and therefore both X and W exist). Finally, since vg = &ug, this gives

- 1 = ( D + 1 D i ' ) b

' / f i g R / R g

and the error between the true result and the computed result is

In this case where the product PfPgRJRg is very large, the error is approximately 11D-l- D;'11211bl12. If we write Df = D + A j , and assume that AJ is small, then D;' =

( I + D - ' A j ) - W 1 = ( I - D-'Af )D- ' , giving an error of

IIVtrue - ugfindl12 = 11D-'AJD-111211b112

G IID-'ll:(IAJl1211b112

1 G ~ l l A J l 1 2 1 1 b 1 1 2

so the error in the Df matrix is effectively damped by a factor of N, while the error in the Dg matrix (as with Dj, we write Dg = D + A g ) is irrelevant.

There are two important points to note about this error result: (1) it is not dependent on the exact ratio rf /rg, but only requires that the ratio be less than 1 (so we only need the constraint plane to be faster than the signal plane-it doesn't matter how much faster); (2) the requirement that DgDJ be positive definite is reasonable. In the ideal case, DgD, = NI has only one eigenvalue, N. In the non-ideal case where DgDJ = NI + A , A would have to have eigen- values < - N for the sum not to be positive definite. In that case, the Df and Dg would be so poor that we would never consider using the circuit. In Section IV, we will see that a straightforward "best guess" at D is simple to

Fig. 4. Hartley's cas function.

Input line j

output line i

X

Fig. 5. Conductor array at intersection of output line I with input line j .

fabricate and guarantees that DgDJ is positive definite.

3) The Non-Ideal Case - Practice Exactly how do we expect DJ and Dg to differ from D?

Pragmatically, we except a limit on how many different conductances we can fabricate on one chip. That raises an obvious question: how many different values of D,, are there when D is N by N? If we require N to be divisible by 8, then as can be seen in Fig. 4, there are only (N/4) + 1 unique values of DIJ, due to symmetry of the cas curve. Negative DIJ's are actually implemented using positive D,,'s connected to negative voltages, and the D,, values on one side of the point cas(-) =a are identical to those on the other. But one of these values is zero, and a conduc- tance of zero simply means no connection at all. So we only need to be able to fabricate N/4 different conduc- tances. Even this may not be exactly possible, of course, since the N/4 values are not simple multiples of each other. We propose a design shown in Fig. 5, where there is a template of 4 X 4 equal-valued conductances at each intersection of an input line with an output line. At a given intersection i j , we connect between 0 and 16 of the con- ductors between the two lines, so as to best approximate DIJ. The results of this approach are given in Section IV.

C. Block 2: Deriving the DFT from the DHT Block 2 of the circuit is simply an implementation of

(3a) and (3b). The voltage vector E = [E, ; . -, E N ] is the real part of the DFT, and the voltage vector 0 = [ O,,, . . . , O N ] is the imagmary part.

CULHANE et al.: HARTLEY & FOURIER TRANSFORMS 701

v,in volts

O. ' Y 0.04 . I . I , I , I , I . I

0.0 0.2 0.4 0.6 0.8 1 .O 1 .2

Time (in nanoseconds)

(b) Fig. 6. (a) Data to be transformed. (b) Speed/accuracy improvement of

U,, with increasing N .

IV. SIMULATION RESULTS We have simulated our circuit using the program

HSPICE running on a VAX 8650. We used P, = 1, P, = 1, R, = R , = 1 ka, Cg = 1 pF, and C, = 1 fF, and ran simula- tions using N = 8, 16, and 32.' We have simulated both perfect and imperfect D matrices.

Fig. 6 shows how error and solution time both improve as N increases, using ideal D. The data to be transformed is a simple unit down-step shown in Fig. 6(a). It is high (1 V) at half of the sampled points, and low (0 V) at half. The time behavior of voltage uo, the first element of the transformed vector, is shown in Fig. 6(b), for nets with N = 8, 16, and 32. The correct value is uo = 0.5. Notice that as N increases, not only does the final value of uo get nearer to 0.5, but the time which it takes to reach its final value decrease^.^

Fig. 7 shows the DFT results with N = 32 for both perfect and imperfect D , using the same input data as for Fig. 6. Fig. 7(a) shows the correct transform, whch we computed via matrix multiplication. Fig. 7(b) shows the result of the simulated net using ideal D. Fig. 7(c) shows the result using a best guess based on the approach of Section 111-C. Each conductor has a value of 0.090 909

3We chose these values for convenience, because they allow us to illustrate the effect of increasing N on both the error and the solution time. On the other hand, they give unrealistically small time constants. More realistic resistor values, such as R , = R , =lo0 kQ would give better time constants, but would make the net's error so small that we could not graphcally illustrate it. A more realistic capacitance, such as C, = 0.1 pF would affect the solution time as well, but would not affect the4 error. This also shows why we did not use a more realistic resistance, such as

100 kfl. From (lo), we can predict that we would have found an error of 1 percent of the error illustrated in Fig. 6(b). The three curves would have been indistinguishable once they settled into their final values.

Real part Imaginary part

Evaluated

matrix 0 2 using ideal 0 1

0 0 0 31

0 5

041 Evaluated

quantized matrix 0 1

00

(c) -0 F==! 2

Fig. 7. Comparison of true, ideal net, and quantized net transforms.

mmhos, and the ijth component of Df (or 0,) is chosen as close as possible to Dij . This gives a DgDf with eigenvalues in the range 26-38, ensuring non-oscillation. We note that it is very difficult to tell the three figures apart.

V. CONTRASTS AND TRADEOFFS There are three advantages of our implementation: its

speed, its simplicity, and its tolerance of inaccuracies in the D matrix. Also noteworthy is that as N increases, the error and the solution time both decreases. How does this circuit compare with other implementations?

In our experience, most on-chp DFT's have been per- formed by implementing the fast Fourier transform or some other algorithm in hardware. The literature does not usually give the actual time these devices take to reach a solution. Usually a time complexity (such as O( N log, N ) ) or an operation count (such as number of adds and multi- plies) is given instead. Because our approach specifically does not implement a sequential algorithm, comparison with such measures would not be meaningful.

Some authors, however, have given solution times for their implementations. Reference [5] details an implemen- tation which will perform a DFT of 840 complex numbers in 100 ms. Whle we have not addressed complex sampled data, our design could accommodate complex numbers by simply having two nets operate in parallel, one transform- ing the real part, the other transforming the imaginary part. An additional bank of adders would be required to compute the final result.

Reference [6] describes an implementation which will perform a complex FFT with N = 512 in 276.5 ps, and [7] gives a time of 95 ps with N = 1024.

702 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 36, NO. 5 , MAY 1989

If we use the more realistic values R f = R, = 100 kQ, and C, = 0.1 pF in our net, then its time constants are in the interval 10 ns < 7 <lo0 ns. While we expect the time constants themselves to improve with increasing N , the bounds are independent of N , and therefore the solution time (say 5 time constants, just as an arbitrary measure)

In the future, we intend to investigate ways to perform an inverse transform with incomplete information by using a regularizer. We also intend to fabricate a prototype chp with N = 32.

ACKNOWLEDGMENT

The authors wish to thank Professor P. S. Krishnaprasad of the University of Maryland for bringing the Hartley transform to their attention, Y. C . Pati, both for helpful insight into the deeper meanings of energy functions and for the circuit of Fig. 3(b), and C . T. Yao for h s insight into the physical realities of making the interconnect ma- trix D.

will never be worse than 500 ns, nor better than 50 ns. However, it is also worth observing that we have only

simulated up to N = 32, and we have not considered any transmission line or RC tree effects of the conductance matrix as N becomes large. In Fig. 5, for example, we may assume that both conductors are of very low resistance, but there is definitely a parasitic capacitor where they cross. If we assume each parasitic capacitor has an area of 3 pm by 3 pm, a plate separation of 1 pm of SiO, (relative permittivity 3.9), then each parasitic is approximately 0.311 REFERENCES fF. If N=1024, then ignoring the coupling from these capacitors, there is a total of 0.318 PF of stray capacitance on each amplifier. We still have 7, < T~ (since each has been hcreased by the Same amount), and the time con- stant now ranges from 10.32-100.32 ns.

N , which we share with every other implementation: space.

[l] D. W. Tank and J. J. Hopfield, “Simple ‘neural’ optimization networks: An A/D converter, signal decision circuit, and a linear programming circuit,” IEEE Trans. Circuits Syst., vol. CAS-36, pp. 533-5413 May 1986.

(21 C. R. K. Marrian and M. C. Peckerar, “Electronic ‘neural’ net algorithm for maximum entropy deconvolution,” in Proc. IEEE First Ann. Conf. on Neural Networks, San Diego, CA, June 1987.

[3] R. N. Bracewell, The Hartley Transform. New York: Oxford Univ. Press, 1986.

[4] M. Takeda and J. W. Goodman, “Neural networks for computation: Numerical representations & programming complexity,” Appl. Opt., vol. 25, no, 18, p. 3033,1986,

[51 R. M. Owens and J. Ja’Ja’, “A VLSI chip for the Winograd/prime factor algorithm to compute the discrete Fourier transform,” IEEE Trans. Acomt., Speech, Signal Processing, vol. ASSP-34, Aug. 1986.

[6] R. E. Owen, “A 15 nanosecond complex multiplier-accumulator for FFTs,” presented at the IEEE Conf. Acoustics, Speech, and Signal Processing, 1986.

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[8] Y. C. Pati, D. Friedman, P. S. Krishnapras?!, C. T. Yao, M. C. Peckerar, R. Yang, and C. R. K. Marrian, Neural networks for tactile perception,” in Proc. 1988 IEEE Conf. Robotics and Automa- tion, Philadelphia, PA. J. K. Hale, Oscillations in Nonlinear Systems. New York: McGraw- ~ 1 1 , 1963.

We also recognize another limitation imposed by large

Our design is not modular, so the number of sampled points we can transform is limited by the space available on a chip. If we use N=1024, and if we assume that in Fig. 5, each line and each spacing between fines is 3 pm, then an area of approximately 3.4 cm by 3.4 cm is needed to contain the conductance array. Additional space would be needed for the amplifiers themselves, and the input and output data would of necessity be multiplexed.

In short, the advantage of Our implementation is its speed and its robustness in the face of uncertainty in the elements of the D matrices. The drawback is its lack of modularity, limiting the range of N which it can handle.

[9]

VI. SUMMARY AND CONCLUSIONS

We have presented a circuit whch computes DFT’s within a few time constants. T h s is accomplished by using a neural net to calculate the DHT, a task for which the linear programming neural net is ideally suited. Because the Hartley matrix satisfies D = DT and D-’ = ND, we are able to find a closed-form solution of the time evolution of the net, and to prove that the net will find a result arbitrarily close to the correct one. In the case where we have some approximation matrices Df and Dg, we still find in simulations that the neural net converges to a vector close to the true DHT, so long as D, is a good approxima- tion of D.

The additional circuitry to compute the DFT from the DHT simply amounts to a few adders.

Whde data are not bountiful on the performance of other on-chip DFT implementations, our circuit settles into its solution in a matter of hundreds of nanoseconds, which seems very favorable, although our non-modular design cannot accommodate the large N ’ s of some other

Andrew D. Culhane received the B.S.E.E. and M.S.E.E. degrees from the University of Notre Dame in 1980 and 1981. Since January 1985, he has been working toward the Ph.D. degree in Electrical Engineering at the University of Mary- land at College Park, specializing in microelec- tronics.

From 1978 to 1982, he worked for the MITRE Corporation programming simulations of wargaming and of communications networks. Since October 1982. he has been with the De-

implementations. partment of Defense, Fort Meade, MD.

CULHANE et U / . : HARTLtY & FOURIER TKANSFOKMS 703

Martin C. Peckerar(M 79-CXf 8hireceired the B S degree froni SUKY Stonc Brook in 1968 and the hf S And Ph D degrees from the Unirersitv of Manland in 1971 and 1975, respectivelc

He 13 currently head of the Microelectrorucj Processing Facilit) at the Nakal Research Labo- ratory His main research interest 15 in the appli- cation of solid state and materials technolog\ to problems in image processing and computation He is the inventor of the deep-deplction CCD for x-ray and UV imaging and the I ax r high-

bnghtncss source for x-ray lithographv He is co-author (wi th Prof S P Murarka, RPI) of the textbook Clecrrom Llurerruis m d Procec5ing. (Academic Press, 1988) He is also part-time profmsor of electrical engineenng at the University of Manland

C. R. K. Manian received the B.A. degree in engineering and the Ph.D. degree in electrical engineering in 1973 and 1978, respectively, from Cambridge University, England.

He subsequently spent nearly three years at CERN in Switzerland working on an Avalanche chamber used in a quark search experiment. In 1980 he joined the Surface Physics Branch at the Naval Research Laboratory. At NRL he has continued his studies of tungsten-based thermionic emitters. Darticularlv under condi-

tions of nonideal vacuum. More recently. he has become interested in the limits of lithographc technique for microfabrication.