A Methodology for A Methodology for Interconnect Interconnect Dimension Dimension

DeterminationDeterminationBy:By:

Jeff CobbJeff CobbRajesh GargRajesh Garg

Sunil P KhatriSunil P KhatriDepartment of Electrical and Computer Department of Electrical and Computer

Engineering,Engineering,Texas A&M University, College Station, TX-Texas A&M University, College Station, TX-

7784077840

OutlineOutline

IntroductionIntroduction Previous WorkPrevious Work ObjectiveObjective ApproachApproach

Cross-bar Bandwidth (CBB)Cross-bar Bandwidth (CBB) Power-adjusted CBBPower-adjusted CBB

Experimental ResultsExperimental Results Conclusions Conclusions

IntroductionIntroduction

New fabrication process developmentNew fabrication process development WidthWidth SpacingSpacing HeightHeight Inter-layer heightsInter-layer heights

Traditionally, fabrication team determinesTraditionally, fabrication team determines

these values, and design team uses the these values, and design team uses the valuesvalues

This may lead to This may lead to sub-optimal designsub-optimal design

IntroductionIntroduction Minimum dimension wires lead to increased Minimum dimension wires lead to increased

scale of integration. However…scale of integration. However… This leads to a large number of wiresThis leads to a large number of wires Inter-wire parasitic capacitance may increaseInter-wire parasitic capacitance may increase Overall circuit speed may decreaseOverall circuit speed may decrease

Increasing inter-layer dielectric heightsIncreasing inter-layer dielectric heights Reduces capacitance between wiresReduces capacitance between wires Increases via resistance and reduces via reliabilityIncreases via resistance and reduces via reliability

Recently, wire delay dominates the logic delayRecently, wire delay dominates the logic delay Hence the problem of interconnect sizing is Hence the problem of interconnect sizing is

importantimportant

IntroductionIntroduction

Design team would provide several Design team would provide several sets sets of acceptable wiring dimensionsof acceptable wiring dimensions

Fabrication team selects the set which Fabrication team selects the set which maximizes both maximizes both yieldyield and and manufacturabilitymanufacturability

This process may be iterated.This process may be iterated. Designers Designers needneed some some metricsmetrics to come to come

up with the sets of wiring dimensionsup with the sets of wiring dimensions We propose two metrics to guide the We propose two metrics to guide the

process of selecting wiring dimensionsprocess of selecting wiring dimensions

Previous WorkPrevious Work Analytical Methods Analytical Methods

Simplifying assumptionsSimplifying assumptions need to be made need to be made Deodhar et. al. assume that grounding wires Deodhar et. al. assume that grounding wires

on present on either side of an interconnecton present on either side of an interconnect Davis et. al. considered Davis et. al. considered stochastic stochastic

interconnect distributioninterconnect distribution to compute to compute interconnect sizing which minimizes power interconnect sizing which minimizes power consumptionconsumption

Li et. al. proposed metrics Li et. al. proposed metrics onlyonly for global for global interconnect optimizationinterconnect optimization Only wire width and spacing are consideredOnly wire width and spacing are considered

ObjectiveObjective

Optimal wiring configuration depends Optimal wiring configuration depends upon several non-linear parametersupon several non-linear parameters A closed form model is not feasibleA closed form model is not feasible

Want to develop metrics that model Want to develop metrics that model delaydelay and and power power of any interconnect of any interconnect configurationconfiguration Cross-bar bandwidth (CBB)Cross-bar bandwidth (CBB) Power-adjusted cross-bar bandwidth (PCBB)Power-adjusted cross-bar bandwidth (PCBB)

Should be applicable to Should be applicable to anyany interconnect interconnect layerlayer

Approach - overviewApproach - overview

Define two metrics -- CBB and PCBBDefine two metrics -- CBB and PCBB Extract resistance and capacitance Extract resistance and capacitance

for various wiring configurationsfor various wiring configurations Evaluate CBB and PCBB for different Evaluate CBB and PCBB for different

wiring configurationswiring configurations Vary wire height, width, spacing and Vary wire height, width, spacing and

inter-layer dielectric in a feasible rangeinter-layer dielectric in a feasible range Select the optimal wiring Select the optimal wiring

configuration empiricallyconfiguration empirically

ApproachApproach

Cross-bar bandwidthCross-bar bandwidth Bandwidth of a wire times the number of wires in an Bandwidth of a wire times the number of wires in an

average size rectangleaverage size rectangle Higher CBB value implies higher maximum data Higher CBB value implies higher maximum data

transfer ratetransfer rate Power-adjusted CBBPower-adjusted CBB

Weighted sum of CBB and power consumption of Weighted sum of CBB and power consumption of interconnects in a rectangular areainterconnects in a rectangular area

We perform sizing of METAL1 through METAL4 We perform sizing of METAL1 through METAL4 conductorsconductors However, this approach can be used for any metal However, this approach can be used for any metal

layerlayer

ApproachApproach

Interconnect dimensions used in our Interconnect dimensions used in our studystudy

ApproachApproach

Wiring configuration for METAL1 and Wiring configuration for METAL1 and METAL2METAL2

Similar configuration is used for Similar configuration is used for METAL3 and METAL4METAL3 and METAL4

ApproachApproach

To evaluate CBB To evaluate CBB or PCBB for any or PCBB for any metal layer metal layer ii, we , we need their need their average length average length llii

Placed and routed Placed and routed several MCNC several MCNC circuitscircuits

Average length Average length llii

Cross-bar BandwidthCross-bar Bandwidth

Consider a rectangle of size Consider a rectangle of size ll11 by by ll22 Via resistance:Via resistance: Elmore delayElmore delay

where: where: cc11 & & cc22 are extracted per unit are extracted per unit length capacitanceslength capacitances

CBBCBB

212

2

w

Lrvia

)()()()( 2222221111 lclrrlclclr via

121221 hwrr

)1

()1

(1212 sw

CBB

Power-adjusted CBBPower-adjusted CBB

Charging currentCharging current

Assume Assume

Total power consumptionTotal power consumption

PCBBPCBB

t

vlclci

)( 2211

VDD

t

v

1212

22112 )(

sw

lrlriPtotal

))1(( totalPKCBBPCBB

CBB & PCBB with CBB & PCBB with RRdriverdriver

Including driver resistance Including driver resistance RRdriverdriver

Elmore delayElmore delay

CBB with driver includedCBB with driver included

PCBB with driver included PCBB with driver included

)()()()( 2222221111 lclrrlclclrR viadriverdriver

)1

()1

(1212 sw

CBBdriver

driver

))1(( totaldriverdriver PKCBBPCBB

Experimental ResultsExperimental Results

Extracted wire capacitances for 70nm Extracted wire capacitances for 70nm process using SPACE 3D-capacitance process using SPACE 3D-capacitance extractorextractor

Computed CBB and PCBB (for Computed CBB and PCBB (for = 0.4) = 0.4) for several wiring configurationsfor several wiring configurations

METAL1 and METAL2 Parameters

METAL3 and METAL4 Parameters

METAL1 & METAL2 - METAL1 & METAL2 - CBB CBB

CBB for all CBB for all parameter parameter variationvariation

Order of Order of variation:variation: ww1212

ss1212

LL22

LL11

hh 1212

L1 has no effect on CBB therefore, select its lowest value i.e. 200nm

METAL1 & METAL2 - METAL1 & METAL2 - CBBCBB

Varying:Varying: ww1212

ss1212

LL22

ForFor

LL11=200nm=200nm

Optimal ValuesOptimal Values

ww1212 = 140nm = 140nm

ss1212 = 100nm = 100nm

CBB is maximum for w12 = 140nm

CBB is maximum for s12 = 100nm

METAL1 & METAL2 - METAL1 & METAL2 - CBBCBB

Vary Vary hh1212 for for optimal optimal valuesvalues of of ww1212, , ss1212 and and LL11

and a and a fixed fixed valuevalue of of LL22

CBB is maximum for h12 = 300nm

METAL1 & METAL2 - METAL1 & METAL2 - CBBCBB

Vary Vary LL22 for for optimal optimal values of values of ww12 12 , , ss1212,, LL11 and and hh1212

Optimal value Optimal value of of

LL2 2 is 200nmis 200nm

CBB is maximized for smallest value of L2

METAL1 & METAL2 - METAL1 & METAL2 - PCBBPCBB

For For = 0.4 = 0.4

PCBB is maximum

ww1212 140n140nmm

ss1212 140n140nmm

LL11 200n200nmm

LL22 200n200nmm

hh1212 240n240nmm

Optimal SizingOptimal Sizing

For METAL1 and METAL2For METAL1 and METAL2

For METAL3 and METAL4 For METAL3 and METAL4

CBB and PCBB CBB and PCBB ImprovementImprovement

For METAL1 and METAL2 optimal For METAL1 and METAL2 optimal sizing yield sizing yield 12.94% increase in CBB 12.94% increase in CBB 19.29% in PCBB19.29% in PCBB

METAL3 and METAL4METAL3 and METAL4 16.5% increase in CBB16.5% increase in CBB 17.15% increase in PCBB17.15% increase in PCBB

Optimal SizingOptimal Sizing

For METAL1 and METAL2 with driver For METAL1 and METAL2 with driver resistanceresistance

For METAL3 and METAL4 with driver For METAL3 and METAL4 with driver resistanceresistance

CBB and PCBB CBB and PCBB ImprovementImprovement

For METAL1 and METAL2 with driver For METAL1 and METAL2 with driver resistanceresistance

For METAL3 and METAL4 with driver For METAL3 and METAL4 with driver resistanceresistance For 300 ohm drivers, the improvements are 31.7% For 300 ohm drivers, the improvements are 31.7%

and 68.9% (CBBand 68.9% (CBBdriverdriver and PCBB and PCBBdriverdriver respectively) respectively) Improvements for other resistance values are Improvements for other resistance values are

similar, and reported in the paper.similar, and reported in the paper.

ConclusionsConclusions

Optimal wiring configuration depends upon Optimal wiring configuration depends upon several parameters therefore,several parameters therefore, closed form closed form model is not feasiblemodel is not feasible

We proposed 2 metrics for wire sizing i.e. We proposed 2 metrics for wire sizing i.e. CBB and PCBB which account for delay and CBB and PCBB which account for delay and powerpower

Without considering driver resistance, our Without considering driver resistance, our approach yields up to approach yields up to 16% improvement in 16% improvement in CBB and 19% improvement in PCBBCBB and 19% improvement in PCBB

With driver resistance, the percent With driver resistance, the percent improvement is even higherimprovement is even higher

Thank You!Thank You!