A Memory Model for RISC-V...I6: r2 = Ld a WMM allows: r1=0, r2=0 Monolithic memory P1 Reg state...

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A Memory Model for RISC-V Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind RISC-V Workshop, November 29, 2016

Transcript of A Memory Model for RISC-V...I6: r2 = Ld a WMM allows: r1=0, r2=0 Monolithic memory P1 Reg state...

Page 1: A Memory Model for RISC-V...I6: r2 = Ld a WMM allows: r1=0, r2=0 Monolithic memory P1 Reg state Store buffer Inv buffer P2 Reg state Store buffer Inv buffer

AMemoryModelforRISC-V

Sizhuo Zhang,Muralidaran Vijayaraghavan,Arvind

RISC-VWorkshop,November29,2016

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WhynotSC/TSO?

Theybothhavesimplespecifications,bothaxiomaticallyandoperationallyButsimpleimplementationshavelowperformancen Strictorderingrequirementsformemory

instructionsn Toimproveperformance,onemustmonitor

coherenceinvalidationtraffictopotentiallysquashexecutedloads

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WhynotPOWER/ARM?

Theiroperationalmodelsexposetoomuchmicroarchitectural detailsn Branchspeculation,OOOexecution,rollbacketc

areexposedinthememorymodelspecification!Theiraxiomaticmodelsaretoocomplexwithnowell-understoodrelationtomicroarchitecturen Onecannotsaywithconfidenceifaparticular

microarchitectural implementationobeysthemodel

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

(1)

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

(1)

(1)

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

(1)

(1)

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

(1)

(1)

(1)

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

(1)

(a)

(1)

(1)

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

(1)

(a)

(1)

(1)

(1)

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Propertiesforanewmemorymodel

Simplespecificationwithoutmicroarchitectural detailslikeBranchspeculation,OOOexecution,rollback,etcButestablishcorrespondencetomicroarchitectureimplementationsWeakerthanSC/TSOforhighperformant,simpleimplementationsInclusionofsufficientfencestoforceSC-likebehaviorwhennecessary

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OurproposalforRISC-Vmemorymodel:WMM

SimpleoperationalspecificationlikeSC,TSO,PSOProcessor …

InstantaneousMemory

SC:• Storesupdatememoryinstantly• Loadreadsmemoryinstantly

ProcessorInstantaneousInorderExecution

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OurproposalforRISC-Vmemorymodel:WMM

SimpleoperationalspecificationlikeSC,TSO,PSOProcessor …

InstantaneousMemory

TSO:• Storesaredequeued inorder• Whenastoreisdequeued fromstorebuffer,itupdatesmemory

instantly

• Loadreadstheyoungeststorefromstorebuffer,or(ifnotpresent)memoryinstantly

StoreBuffer

Processor

StoreBuffer

InstantaneousInorderExecution

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OurproposalforRISC-Vmemorymodel:WMM

SimpleoperationalspecificationlikeSC,TSO,PSOProcessor …

InstantaneousMemory

PSO:• Storesaredequeued inorderonlyforsameaddress• Whenastoreisdequeued fromstorebuffer,itupdatesmemory

instantly

• Loadreadstheyoungeststorefromstorebuffer,or(ifnotpresent)memoryinstantly

StoreBuffer

Processor

StoreBuffer

InstantaneousInorderExecution

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OurproposalforRISC-Vmemorymodel:WMM

SimpleoperationalspecificationlikeSC,TSO,PSOProcessor …

InstantaneousMemory

WMM:• Storesaredequeued inorderonlyforsameaddress• Whenastoreisdequeued fromstorebuffer,itupdatesmemory

instantly,removesaddressfromowninvalidationbufferandenterseveryotherinvalidationbufferinstantly

• Loadreadstheyoungeststorefromstorebuffer,or(ifnotpresent)oldestentryininvalidationbuffer,or(ifnotpresent)memoryinstantly

• Oldestinvalidationbufferentrycanbethrownoutanytime

StoreBuffer

Processor

StoreBuffer

InvalidationBuffer

InvalidationBuffer

InstantaneousInorderExecution

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FencesinWMM

Acquire/ReconcileFence:ClearsInvalidationbufferRelease/CommitFence:WaitsforStorebuffertobeflushed(non-atomically)

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AxiomaticDefinitionofWMMMemoryorderreorderingaxiom:

Loadreadstheyounger(inmemoryorder)ofn LateststoreinmemoryorderforthataddressORn Lateststoreinprogramorder(inthatthread)forthataddress

Can Reorder?Second

Ld b Stbv’ Acq/Reconcile Rel/Commit

First

Ld a a!=b No No No

Stav Yes a!=b Yes No

Acq/Reconcile No No No No

Rel/Commit Yes No No No

St-StFence:CommitLd-Ld Fence:Reconcile

St-Ld Fence:Commit+ReconcileLd-StFence:Notneeded

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ImplementingWMM

Anexecutedloadwontgetsquashedlateraslongasitdoesn’tovertakeareconcileormemoryinstructiontosameaddressn Nomonitoringofcoherenceinvalidationsn Loadaddressspeculationallowed– squashedonlyif

predictedaddressiswrongAllinstructionsarecommittedinordern Storescannotovertakeloadsn Prevents“out-of-thin-air”generationofvalues

FormallyProven:OOO+ Single-threaded-correctness+ In-order-commit

+ ValuePrediction+ GlobalStoreAtomicity=WMM

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ImplementingWMM

Writeback coherentcachehierarchytypicallysatisfiesGlobalStoreAtomicityIfL1iswrite-through,easytoensureGlobalStoreAtomicityunlessthecoreisSMTn SMTcoreswithL1write-throughcachesimplementa“non-multicopy-atomic”

memory Don’tdoit

“Theoretically, the definition of the aq and rl bits allows for implementations without global store atomicity. When both aq and rl bits are set, however, we require full sequential consistency for the atomic operation which implies global store atomicity in addition to both acquire and release semantics. In practice, hardware systems are usually implemented with global store atomicity, embodied in local processor ordering rules together with single-writer cache coherence protocols.”

FormallyProven:OOO+ Single-threaded-correctness+ In-order-commit

+ ValuePrediction+ GlobalStoreAtomicity=WMM

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MappingC++11toWMMC++11 WMM

Non-atomic Load Load

Load Relaxed Load

LoadConsume Load;Acquire/Reconcile

LoadAcquire Load;Acquire/Reconcile

LoadSC Rel/Commit;Acq/Reconcile;Load;Acq/Reconcile

Non-atomicStore Store

StoreRelaxed Store

StoreRelease Release/Commit;Store

StoreSC Release/Commit;Store

UsingoperationalspecificationofWMMmakesitstraightforwardtoderive/verifythismapping

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Conclusion

WMMisamemorymodelwithsimplespecificationandpotentiallyhighperformantimplementationsn BlendswellwithRISC-Vphilosophyandshould

beusedasthememorymodelforRISC-V

Thankyou! [email protected]@[email protected]

Advertisement:FormallyverifiedRISCV(subsetofRV32I)multicoreimplementationinKami,ahardwareformalverificationplatform

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Backup

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WhynotRMO?

Thread1 Thread2Sta=1 Ld r1=bMEMBAR Branchr1!=1goto exitStb=1 Stc=1

Ld r2=cr3=a+r2- 1Ld r4=[r3]exit:

RMO’sdependencyrequirementsaretoostrict

Initiallyeverything’s0

(1)

(a)

(1)

(1)

(1)

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WhynotReleaseConsistency?

FencesarenotstrongenoughtogiveSequentialConsistency

Thread1 Thread2 Thread3Stval =1 Ld r1=val Ld r2=flag

Stflag =r1 Ld r3=val

Non-cumulativeFences

Initially,everythingis0

(1)

(1)

(1)

(0)

AcquireRelease

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Out-of-thin-airissue

Noprocessorcanproducevaluesoutofthinairn ButincompletesetofaxiomsseeminglyallowsthisInsistingonin-ordercommitsandadvertisingstoresonlyaftercommittootherthreads/processorstakescareofthisissue

Thread1 Thread2Ld r1=x Ld r2=ySty=R1 Stx=42

Initiallyeverythingis0Finallyx=y=r1=r2=42

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“The AMOs were designed to implement the C11 and C++11 memory models efficiently. Although the FENCE R, RW instruction suffices to implement the acquire operation and FENCE RW, W suffices to implement release, both imply additional unnecessary ordering as compared to AMOs with the corresponding aq or rl bit set.”

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LitmusTestsforWMM

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TestSB

P1 P2

I1:Sta 1I2:Commit

I3:r1 =Ld b

I4:Stb1I5:Commit

I6:r2=Ld a

WMMallows:r1=0,r2=0

Monolithicmemory

P1Reg state

Storebuffer

Invbuffer

P2Reg state

Storebuffer

Invbuffer<a,1> <a,0><b,1><b,0>

Reconcile Reconcile

WMMallowsthebehavior- Ld overtakesStandCommit

AddReconciletoforbidthis

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LitmusTestsforWMM

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Monolithicmemory

P1Reg state

Storebuffer

Invbuffer

P2Reg state

Storebuffer

Invbuffer<a,1>

<a,0>

<b,0>

<b,a>

WMMallowsthebehavior- Ld overtakesLd- Nodependencyordering- Canbecausedbyvaluepredictioninhardware

AddReconciletoforbidthis

Out-of-thin-airisimpossiblebecauseofI2E

TestMP+data

P1 P2

I1:Sta1I2:CommitI3:St ba

I4:r1 =Ld b

I5: r2=Ld r1

WMMallows:r1=a,r2=0

Reconcile

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WMM-S

ThesameabstractmachinestructureasWMMModelnon-multi-copy-atomicstoresn Makeastorefromprocessori visibletoprocessorj beforethestoreupdates

monolithicmemoryn Makeacopyofthestorefromthesb ofprocessori, andinsertthecopyintothe

sb ofprocessorjn Eachstorehasauniquetag,copieshavethesametagDequeue astorefromsb tomonolithicmemoryn Allcopiesaredequeued fromsbn AllcopieshavetobetheoldestoneforthestoreaddressintheirrespectivesbCopyingofamustbeconstrainedforper-locationSCn Eachsb ordersstoresforacertainaddressasalistn Combiningallsuchlistsfromallsb togetherformsapartialcoherenceorder

(<"#)ofthestoretagsforthataddressn Aftercopying,partialcoherenceordermustbestillacyclic

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Stbuffer𝑠𝑏

Monolithicmemory𝑚

…

Processor𝑝𝑠[𝑖]Regstate𝑠

Inv buffer𝑖𝑏 …

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Storecopyexample

Currentpartialcoherenceordern 𝑡, <"# 𝑡- <"# 𝑡. and𝑡/ <"# 𝑡-n 𝑡, and𝑡/ areunrelatedIfwecopyCintosb ofP1asC’n Createcycle:𝑡. <"# 𝑡/ <"# 𝑡- <"# 𝑡.n ShouldnotbeallowedIfwecopyAintosb ofP2n Createcycle:𝑡. <"# 𝑡.

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A:𝑡.

P1sbInsertedlater(younger)

↕Insertedearlier(older)

A’:𝑡.B:𝑡-D:𝑡,

P2sbB’:𝑡-

C:𝑡/

P3sb

C’:𝑡/

(Primesarecopies)

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LitmusTestsforWMM-S

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TestWRC

P1 P2 P3

I1:Sta 1 I2:r1=Ld a

I3:Stb r1

I4:r2 =Ld bI5:ReconcileI6:r3=Ld a

WMM-Sallows:r1=1,r2=1,r3=0

<a,1>

P1sb

<a,1>

P2sb P3sb

m <b,1>

• AddCommitinP2toforbidthisbehavior

• Commitgloballyadvertisesobservedstores-- release

• Reconcilepreventsloadsfromreadingstalevalues--acquire

Commit

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LitmusTestsforWMM-S

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TestIRIW

P1 P2 P3 P4

I1:Sta 1 I2:r1=Ld a

I3:ReconcileI4:r2=Ld b

I5:Stb1 I6:r3=Ld b

I7:ReconcileI8:r4=Ld a

WMM-Sallows:r1=1,r2=0,r3=1,r4=1

<a,1>

P1sb

<a,1>

P2sb

<b,1>

P3sb

m

<b,1>

P4sb

Commit Commit

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WMM-SImplementation

WMM-ScanbeimplementedusingOOO+non-atomicmemorysystemn e.g.memorysystemoftheARMFlowingModel(FM)[1]

n WedonotneedstorebufferinOOO,becauseFMhasbuffers

33[1]Flur etal.“ModellingtheARMv8architecture,operationally:concurrencyandISA”,POPL2016

OOOP1ROB

OOOP2ROB

OOOP3ROB

OOOP4ROB

Segment𝑠[1] Segment𝑠[2] Segment𝑠[3] Segment𝑠[4]

Segment𝑠[5] Segment𝑠[6]

MonolithicmemorymFM

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FM+OOO

Eachsegmentisabufferofmemoryrequestsn KeepsFIFOorderingofrequeststothesameaddressn Flowrule:Theoldestrequestforsomeaddressinasegmentcanbemovedto

theparentsegmentormonolithicmemoryn Bypassrule:Astorecanforwarditsdatatoaload,aslongasthereisnoother

requesttothesameaddressinbetweenOOOcommitn store:directlyinsertintosegmentn Commitfence:ifanysegmentcontainsastoreobservedbythecommitsofthe

OOOprocessor,thenwecannotcommitthefence

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Seg.𝑠[1]

Seg.𝑠[5] Seg.𝑠[6]

Monolithicmemorym

P1 ROB

Seg.𝑠[2]

P2 ROB

Seg.𝑠[3]

P3 ROB

Seg.𝑠[4]

P4 ROB

Astoreobservedbycommitsof𝑃𝑖:eithercommittedby𝑃𝑖 orreturnedbyaloadcommittedby𝑃𝑖

SimplifiedversionofFM(nofenceinFM)

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CCM+OOO⊆WMMFM+OOO⊆WMM-S

HowWMM/WMM-SsimulatesCCM/FM+OOOn WhenthemonolithicmemoryinCCM/FMisupdatedbyastore

w WMM/WMM-Sdequeues thatstorefrom𝑠𝑏tomonolithicmemoryn WhenOOOcommitsaninstruction

w WMM/WMM-SexecutesthatinstructionWhenOOOPicommitsaloadLforaddressa withresultvn Considerwhereisv inCCM/FM+OOOwhenLcommits

n v isinmonolithicmemoryofCCMw WMMexecutesLbyreadingmonolithicmemory

n v hasbeenoverwrittenbyanotherstoreinmonolithicmemoryw WMMhaspreviouslyinserted<a,v>intoib ofps[i]w NowWMMcanexecuteLbyreadingib

n visinstorebufferofOOOPiw IfvhasbeenobservedbycommitsofPibeforeLiscommitted,thenWMM/WMM-Scan

executeLbyreadinglocalsbw Otherwise,WMM-Sfirescopy<a,v>intolocalsb andletLreadit

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ImpactofDisallowingLd-StReordering

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Qualitativeanalysisn Storebuffercanalreadyhidethestoremisslatencyn Storesarenotonthecriticalpathforsingle-threadperformancen Inextremecases,thespeculativestorequeuemaybefilledupwith

uncommittedstores

Quantitativeevaluationn Simulate8-coremultiprocessorusingESESCsimulatorn RunSPLASH2xbenchmarksn CompareWMM,Alpha,andaggressiveimplementationsofSCand

TSOn Alpha=WMM+Ld-Streordering

w TrytofindyoungerstorestocommitwhentheinstructionatthecommitslotoftheROBcannotcommit

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SimulationConfiguration

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Results

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NormalizedexecutiontimeanditsbreakdownatthecommitslotofROB

NormalizedexecutiontimeanditsbreakdownattheissueporttoROB

AveragecyclestocommitstoresearlyinAlpha

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Non-AtomicMemory

Modelsfornon-atomicmemoryismorecomplicatedWeareunclearabouttheperformanceadvantageofnon-atomicmemoryn Becauseourunderstandingofthemicroarchitectural sourcesfornon-atomic

memoryislimitedn POWER:sharedwrite-throughL1duetoSMT

w OthersourcesinthehierarchystartingfromL2?n ARM:noclue

w Manylitmustestsfornon-atomicstoresarenotobservableonhardwarew WRC+addrs,WWC+addrs,IRIW+addrs (http://diy.inria.fr/cats/model-

arm/all.html)w WRC+addrs (http://www.cl.cam.ac.uk/~sf502/popl16/observations.pdf)

Onlybyunderstandingthemicroarchitectural reasonsfornon-atomicmemory,areweabletoanalyzethebenefitofit

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COGS & Inv.

COGS & Inv.

Inv Access

Inv Access

COMUNE DI MONTECENERI · di in r3 in ar-r r2 r4 r3 r3 r2 r3 ar-r r4 r2 r3 apep r2 r2 ar-r r3 aepp r2 r3 r2 r2 r4 nt in r2 r2 r3 r2 aepp aepp r2 r2 r2 apep r2 r2 r2 r2 nt r4 r4 np

COMUNE DI MONTECENERI · di in r3 in ar-r r2 r4 r3 r3 r2 r3 ar-r r4 r2 r3 apep r2 r2 ar-r r3 aepp r2 r3 r2 r2 r4 nt in r2 r2 r3 r2 aepp aepp r2 r2 r2 apep r2 r2 r2 r2 nt r4 r4 np

pending inv

pending inv

Oracle Inv

Oracle Inv

proyecto inv

proyecto inv

Inv. Accidentes

Inv. Accidentes

Inv Cientifica

Inv Cientifica

BUFFER SOLUTIONS. CONTENTS What is a buffer solution? Uses of buffer solutions Acidic buffer solutions Alkaline buffer solutions Buffer solutions - ideal.

BUFFER SOLUTIONS. CONTENTS What is a buffer solution? Uses of buffer solutions Acidic buffer solutions Alkaline buffer solutions Buffer solutions - ideal.

50' UNDISTURBEDVEGETATIVE BUFFER · 15 6 17 3 25' state buffer 50' undisturbedvegetative buffer 50' undisturbed vegetative buffer 50' undisturbedvegetative buffer asphalt asphalt

50' UNDISTURBEDVEGETATIVE BUFFER · 15 6 17 3 25' state buffer 50' undisturbedvegetative buffer 50' undisturbed vegetative buffer 50' undisturbedvegetative buffer asphalt asphalt

LEGEND EVENT SPACE · di tc 41.76 gr 41.41 a-inv 39.76 b-inv 39.67. di tc 41.58 gr 41.21 a-inv 39.81 b-inv 39.74. di tc 41.95 gr 41.56 a-inv 39.55 b-inv 40.22. di tc 41.52 gr 41.18

LEGEND EVENT SPACE · di tc 41.76 gr 41.41 a-inv 39.76 b-inv 39.67. di tc 41.58 gr 41.21 a-inv 39.81 b-inv 39.74. di tc 41.95 gr 41.56 a-inv 39.55 b-inv 40.22. di tc 41.52 gr 41.18

KMC654e H9562-20170502083019 · cmh1501 rim = 689.86 inv = 680.42 cmh654 rim = 690.577 inv = 684.187 cmh336 rim = 690.973 inv = 683.363 cmh337 rim = 690.907 inv = 681.627 cmh338 rim

KMC654e H9562-20170502083019 · cmh1501 rim = 689.86 inv = 680.42 cmh654 rim = 690.577 inv = 684.187 cmh336 rim = 690.973 inv = 683.363 cmh337 rim = 690.907 inv = 681.627 cmh338 rim

Connect Ethernet, Fast Ethernet, or Gigabit Ethernet copper ports to 1000 … · 2017-04-19 · LGC120A-R2 LGC125A-R2 LGC129A-R2 LGC121A-R2 LGC126A-R2 LGC130A-R2 LGC122A-R2 LGC127A-R2

Connect Ethernet, Fast Ethernet, or Gigabit Ethernet copper ports to 1000 … · 2017-04-19 · LGC120A-R2 LGC125A-R2 LGC129A-R2 LGC121A-R2 LGC126A-R2 LGC130A-R2 LGC122A-R2 LGC127A-R2

&200,77((21&/$,06 - carroll-county.net7FC08AB3-4BE5-4C4B... · 9778? Stage Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv S226596 S226596 Vendor/ Line Nbr 3565 2960 1091 3565 1464 1660

&200,77((21&/$,06 - carroll-county.net7FC08AB3-4BE5-4C4B... · 9778? Stage Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv S226596 S226596 Vendor/ Line Nbr 3565 2960 1091 3565 1464 1660

guam Tax Assd Roll · Inv# Agana Heights ADKINS ROBERT DEAN SANTOS ... M15 L3338-2-R2 0 94,190 213.93 0 ... BLEND ALLEN E C PO BOX 1255

guam Tax Assd Roll · Inv# Agana Heights ADKINS ROBERT DEAN SANTOS ... M15 L3338-2-R2 0 94,190 213.93 0 ... BLEND ALLEN E C PO BOX 1255

Inv Synchronization

Inv Synchronization

&200,77((21&/$,067FC08AB3-4BE5-4C4B... · 5474/5493 9209155598 & MAINTENANCE Stage Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv WATER WATER Vendor/ Line Nbr

&200,77((21&/$,067FC08AB3-4BE5-4C4B... · 5474/5493 9209155598 & MAINTENANCE Stage Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv Inv WATER WATER Vendor/ Line Nbr

EE457 Branch Prediction r2 - branch prediction branch prediction buffer (bpb) accessed with instruction in i-fetch instrucion memory ... ttttttttttt examples tttttttt n ttttttt

EE457 Branch Prediction r2 - branch prediction branch prediction buffer (bpb) accessed with instruction in i-fetch instrucion memory ... ttttttttttt examples tttttttt n ttttttt

Inst. Inv. Ph. 2 Penalty1.pdf · Title: Inst. Inv. Ph. 2 Author: CamScanner Subject: Inst. Inv. Ph. 2

Inst. Inv. Ph. 2 Penalty1.pdf · Title: Inst. Inv. Ph. 2 Author: CamScanner Subject: Inst. Inv. Ph. 2

Inv Patiala

Inv Patiala