A Low Temperature Ohmic Contact Process for n …...1 A Low Temperature Ohmic Contact Process for...
Transcript of A Low Temperature Ohmic Contact Process for n …...1 A Low Temperature Ohmic Contact Process for...
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A Low Temperature Ohmic Contact Process for n-type Ge Substrates
K. Kakushima, R. Yoshihara, K. Tsutsui, H. Iwai
Tokyo Institute of Technology
IWJT 2013 6 May 2013
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High mobility channel candidates for n- and p-MOSFETs
I. Vurgaftman, et al., J. Appl. Phys., 89, pp. 5815 (2001).Table from S. Takagi, IEDM Short course (2011).
Channel selection
C. H. Lee, et al., IEDM p. 457 (2009).
InGaAs for n-MOSFETGe for p-MOSFET
High electron mobility with Ge channel(after Dit reduction process)
No doubt for p-MOSFET with Ge channelGe channel is also attractive for n-MOSFET
Ge n-MOSFET
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Source/Drain junctions for Ge n-MOSFET
Large diffusion coefficient for P, As, Sb (>500oC)Incomplete activation of dopants
A. Axmann, et al., Appl. Phys., 12, pp. 173 (1977).S. Mirabella, et al., J. Appl. Phys., 113 031101 (2013).
Control of diffusion and activation of dopants are the keyfor source/drain for Ge sub.
Short period/high temperature annealing to exceed 1020 cm-3
C. O. Chui, et al., Appl. Phys. Lett., 83, 3275 (2003).
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R. Li, et al., EDL, 27, 476 (2006).
Ge MOSFET with Schottky junctions
Metal Schottky junctions have advantages for scaled MOSFETsMany reports of metal Schottky junction (PtGe2, NiGe, etc.) for Ge p-MOSFET
Advantages of metal Schottky S/D- atmoically abrupt junction- robust against short-channel effect- low parasitic resistance- low temperature process capability
J. M. Larson, TED, 53, 1048 (2006)
Lphy
Dop
antC
onc.
y position
δ δGate
σ σ
Lphy
Dop
antC
onc.
y position
δ δGate
σ σ Met
al C
onc.
y position
Gate
Lphy = Leff
Met
al C
onc.
y position
Gate
Lphy = Leff
Conventional doping Schottky junction
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Fermi level pinning at metal/Ge
Metal-induced gap states
Extrinsic defects (interface states)
Dangling bonds
Structural disorder at interfaceP. S. Y. Lim, Appl. Phys. Lett.,101, 172103 (2012).
Proposed mechanism of pinning
Metal pinnned near VB of Ge, which is favorable for p-MOSFETHowever, it gives a huge challenge for n-MOSFETA depinning process has to be developed
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Reported de-pinning process for Ge sub.
M. Kobayashi, et al., J. Appl. Phys., 105, 023702 (2009).
Insertion of thin SiN layer Formation of amourphous Ge layer
Sensitive to SiN thicknessTrade-off between parasitic resistance
Sensitive to process conditionsRestriction for thermal treatments
No intentional layer insertion to achieve a low φBn (Ohmic) contactStable process with wide process window (power, annealing, etc.)
M. Iyota, et al., Appl. Phys. Lett., 98, 192108 (2011).M. Mitsuhara, et al., JSAP Autumn meeting (2012).
De-pin process requirements for Schottky S/D
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Contents of this presentation
1. Introduction2. Stacked silicidation sputtering process3. φBn tuning with P atom incorporation4. Extraction of surface potential shift by XPS5. Conclusions
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Stacked silicidation sputtering process
n-Ge(100) sub.
Ni(5.5nm)
(a)
n-Ge(100) sub.
Si(1.9nm)/Ni(0.5nm)
8 set of Si/Ni layers
(b)
n-Ge substrate (4x1016 cm-3)
HF treatment
Diode patterning
Deposition by RF sputtering in Ar
Backside Al contact
Rapid Thermal Annealing (RTA) in N2
(a) Ni (5.5nm)
(b) Ni(0.5nm)+Si(1.9nm) x 8
(Control sample)
Control sample
NiSi2 film on Geusing stacked silicidation
10nm
Corresponds to atomic ratio of 1:2
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rms
Rou
ghne
ss (n
m)
Annealing temperature (oC)
asdepo. 200 300 400 500 600 700
0
2.0
4.0
6.0
StackedNiSi2
NiSi2 is formed over 350 oC, stable sheet resistances can be obtained up to 700 oC
050
100150200250300350400
0 100 200 300 400 500 600 700Annealing temperature (oC)
asdepo.
Ni (5.5nm)
StackedNiSi2
(10nm) agglomeration
wide processwindow
Shee
t res
ista
nce
(Ω/s
q.)
Sheet resistance by 4-point probe method Surface roughness (rms) by AFM
Smooth surface can be obtained up to 600 oC annealing
A thermally stable metal with wide process window (350oC~600oC) can be obtained with stacked silicidation sputtering process
on n-Ge
on n-Ge
Thermal stability of NiSi2 on Ge sub.
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Reaction of NiSi2 and Ge substrate
56kJ/mol2SiNiGeGeNiSi2 −+=+
22 OGeNiSi ++1760kJ/mol2SiONiGe 2 ++=
Reaction do not proceed
Under presence of oxygen atomsNiSi2 can be decomposed by Ge
-Formation of SiO2 is confirmed-Further stability can be expected by adopting oxygen atom/molecule blocking capped layer
Main composition is NiSi2 at 500oC annealing with thin NiGe (<1nm)
∆Hf data from Y.Q.Lu, J. Alloy. Comp., 491, p64 (2010)
851852853854855856857
Binding energy (eV)
Inte
nsity
(a.u
.)
NiGeNiSiNiSi2
500 oC800 oC
Ni 2p3/2hν=7940 eVTOA=80o
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Diode characteristics of NiSi2/n-Ge sub.
NiSi2 showed stable φBn with ideality factor within 1.2 up to 500 oC
asdepo. 400 500 600
Annealing temperature (oC)
Stacked NiSi21.0
2.0
3.0
Idea
lity
fact
or
Stacked NiSi2
Ni(5.5nm)0.50
0.55
0.60
0.45
φ Bn
(eV)
Ni(5.5nm)
NiSi2 by stacked silicidation process is useful to preserve ideal metal/Ge interface
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φBn tuning with P atom incorporation
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φBn tuning by P atom incorporationwith stacked silicidation process
n-Ge(100) sub.
Si(1.9nm)/Ni(0.5nm)
Ni3P(0.68nm)Si(1.9nm)
7 set of Si/Ni layers
Incorporation P atoms at metal/Ge interface
The first Ni layer was replaced with Ni3P layer
Corresponds to P atoms of 4.6x1015 /cm2
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Ge diode characteristics with P incorporation
Anode voltage (V)
Cur
rent
den
sity
(A/c
m2 )
0 0.5 1.0-0.5-1.0
30
2010
0
-10
-20-30
600oC500oC
400oCasdepo.
n-Ge (100)(Nd=4x1016cm-3)
Anode voltage (V)
Cur
rent
den
sity
(A/c
m2 )
0 0.5 1.0-0.5-1.0
102
101
100
10-1
10-2
10-2
600oC500oC
400oC
asdepo.
An Ohmic contact to n-type Ge substrate can be achievedat annealing temperature over 400 oC
Stable Ohmic characteristics can be obtain up to 600 oC
Increase in reverse current after annealingAfter annealing, Ohmic contact can be obtainedFurther increase in current with temperature
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Cross-sectional images of NiSi2:P/Ge
Surface agglomeration with interface reaction and SiO2
A thin bright contrast at interface
A 1-nm-thick layer with a bright contrast with P atoms might be the key to realize Ohmic contact for n-type Ge sub.
Flat surface and interface
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Extraction of surface potential shift by XPS
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Potential profile extraction of Ge sub.
[ ]dzzEEIeEJz
)(sin)( 00sin ψθθλ +−⋅⋅= ∫
∞−
I(E-E0) : a typical spectrum with a peak energy of E0Ψ(z) : potential profile in Si substrateθ: take off angleλ: Inelastic mean free pass (IMFP)
Energy
Spectrum is the convolution of potential
Peak shift
Energy
Ge 2p
VB
CBφBn
2
21)( ⎟
⎟⎠
⎞⎜⎜⎝
⎛⋅−≈ zqNz
sGe
bs ψε
ψψ
Nb: doping concentrationψs: surface potential 3/2
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Surface potential extraction by XPS
Spectrum shifts due to band bending in Ge substratesA shift of 0.3eV is the average binding energy of each photoelectron
Surface bends down with P incorporation
without incorporation
P incorporation
1220 1219 1217
Binding energy (eV)
1216
Inte
nsity
(a.u
.) Ge 2p3/2 spectrahν=7940 eVTOA=80o
500 oC 1min
0.3 eV
GeNiSi2 10nm
hν=7940eV
IMFP(λ)~10nm
TOA=80o
BE
ψs
Z
distance from surface Ge(3λ~36nm)0
ψs,P with P incorporation
NiSi2 only
Ge 2p3/2
(3λ~30nm)
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NiGeGe sub.Ge 2p3/2hν=7940 eVTOA=80o
500 oC 1min
NiGeGe sub.
1220 12151219 1218 1217 1216Binding energy (eV)
1220 12151219 1218 1217 1216Binding energy (eV)
interface
bulk
interface
bulk
Inte
nsity
(au)
Inte
nsity
(au)
deconvolutiondeconvolution
ψs = -0.43 eVψs,P = 0.14 eV
A potential shift of 0.57 eV can be extracted by deconvolution
BE
ψs
Z
distance from surface Ge(3λ~36nm)0
ψs,P with P incorporation
NiSi2 only
Ge 2p3/2
(3λ~30nm)
Deconvolution of Ge 2p3/2 spectra
w/o P with P
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Specific contact resistance with P incorporation
-1.0 -0.5 0.0 0.5 1.0
2.01.51.00.50.0
-0.5-1.0-1.5-2.0
Cur
rent
(mA)
Voltage (V)
60µm
30µm
60µm
30µm
as-sputtered
700oC
600oC
300oC
200 300 400 500 700
10-1
10-2
10-3
Con
tact
resi
stan
ce (Ω
cm2 )
Annealing temperature (oC)600
n-Ge (4x1016cm-3)
Less dependency on annealing temperatureStill, this process has strong advantage for meal Schottky S/D application
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0 1.0 2.0 3.0 4.0 5.01015
1017
1019
1021
1023
Diffusion depth (nm)
P co
ncen
tratio
n (c
m-3
)
NiSi2 Ge sub.
500 oC 1min
Nd = 4.0x1016 cm-3
⎟⎠
⎞⎜⎝
⎛=DtxNtxN s 2
erfc),(
Ns: solid solubility limitD : diffusion constant
D = 2.3x10-17
Ns = 3.0x1019 cm-3
Number of P atoms= 4.6x1015 atoms/cm2
P
x
Discussion: P atom diffusion into Ge?
Contribution of φBn tuning→Low temperature JV measurement in progress
Model from XPS measurementsP atom diffusion <1nm for 300oCCannot explain the contact resistance
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ConclusionsStacked Ni silcidation process for Ge sub.
- initial flatness of Ge substrate can be maintained- position of the interface is defined- stable surface and interface up to 600oC annealing
Effective Schottky barrier height (φBn) reduction - effective φBn reduction to Ohmic with P incorporation- stable properties up to 600oC annealing
Surface potential shift with P incorporation is confirmed- Shift of 0.57eV, near CB of Ge, has been extracted by XPS
Constant specific contact resistance against annealing - Contribution of φBn shift in addition to P atom diffusion
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Si(1.9nm)/Ni(0.5nm)
Ni3P(0.7nm)
B(0.3nm)
Si sub.
Si(1.9nm)/Ni(0.5nm)
Ni3P(0.7nm)
B(0.3nm)
Si sub.
1023
1022
1021
1020
1019
NiSi2 Si sub.
0 10 20Depth (nm)
B co
ncen
tratio
n (c
m-3)
before
B
after 500oC annealing
1022
1021
1020
1019
1018
NiSi2 Si sub.
0 10 20Depth (nm)
P co
ncen
tratio
n (c
m-3)
before
after 500oC annealing
P
B or P incorporation with stacked silicidation process
SIMS B and P profile
Feasibility study: NiSi2 on Si substrate with P and B atoms
Most of the B and P atoms remain at NiSi2/Si sub. Interface(some of them diffuse out toward surface)
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Depinned report with epi-NiGe2 formation
φBn tuning 0.60 → 0.37eV
Laser irradiation epitaxial NiGe2 growthNiGe NiGe2
NiGe2 is not a stable form for bulk nickel germanide
NiGe2 might be formed under high stress or non-equilibrium thermal treatmentRole of P atoms and thin bright layer are the keys for our Ohmic contact
P. S. Y. Lim, et al., Appl. Phys. Lett., 101, 172103 (2012).