A Low-Power Multi-band ECoG/EEG Interface ICFan Zhang∗, Apurva Mishra∗, Andrew G. Richardson†, Stavros Zanos†, and Brian P. Otis∗

∗Department of Electrical Engineering, University of Washington, Seattle, WA 98195-2500†Department of Physiology and Biophysics, University of Washington, Seattle, WA 98195-2500

Abstract—We present a 6.4 µW electrocorticography(ECoG)/electroencephalography (EEG) processing integratedcircuit (EPIC) with 0.4 µVrms noise floor intended foremerging brain-computer interface (BCI) applications. Thischip conditions the signal and simultaneously extracts energyin four fully-programmable frequency bands. Functionality isdemonstrated by tuning the four bands to important frequencybands used by ECoG/EEG applications: α (8-12Hz), β (18-26Hz), low-γ (30-50Hz) and γ (70-100Hz). Measured resultsfrom in-vivo ECoG recording from the primary motor cortex ofan awake monkey are presented.

I. INTRODUCTION

Electrocorticography (ECoG) is a method of recordingelectrical brain activity using planar electrodes on the surfaceof the brain cortex. ECoG electrodes may be more suitable forlong-term recordings than intracortical electrodes, as ECoGrecording quality may be less affected by electrode movementand the tissue response [1]. ECoG implants, used extensivelyin the diagnosis of epilepsy [2], have recently demonstratedpromising results towards potential use in brain-computerinterfaces (BCIs): systems to help people with movementdisorders communicate or operate motor prosthetic devices.Certain frequency ranges of ECoG signals from motor corticalareas are found to be associated with movement or movementintentions, and have been used with BCI systems that allowsubjects to control a cursor on a computer screen [1].

Since ECoG spectral changes in specific frequency rangesare believed to be markers of cortical neuronal activity, arecording system that extracts sub-banded energy content inreal time would be useful for ECoG-based BCI applications. Ina wireless system, this would reduce the amount of data thatneeds to be transmitted out of the recording chip, resultingin reduced power dissipation. This is particularly important ifmany channels (e.g., 16) are processed on each chip. In thispaper, we present an ECoG/EEG processing integrated circuit(EPIC) with 6.4 µW core power dissipation primarily designedfor, but not limited to, ECoG-based BCI applications. Thischip conditions the signal and simultaneously extracts energyfrom four independently tunable bands. The outputs will bedigitized and transmitted to a body-worn device or a remotestation for further processing. Classifiers can then be appliedto the transmitted spectral information to decode movementintentions. This work focuses on the ultra-low power real-timeenergy detection of four frequency bands.

II. SYSTEM AND CIRCUIT DESIGN

EPIC functions as a computational interface between brainelectrodes and A/D converter in a neural-recording system.

Fig. 1. System block diagram of the ECoG/EEG processing IC (EPIC) tobe used in BCI applications.

Fig. 1 shows the system block diagram, comprising four mainblocks: a low-noise analog front-end (AFE) that amplifies theinput waveforms, four configurable band energy extractors,clock generation, and control logic. All four band energyextractors are power- and clock-gated so that any or all ofthe bands can be enabled at a time. Fully-differential designis used throughout EPIC to ensure sufficient output swing andimprove the CMRR/PSRR for low supply voltages (1.2V).

A. Analog Front-End (AFE)

ECoG/EEG-recording applications demand a low noise floor(<5 µVrms input-referred) and a relatively low bandwidth(<500Hz). We employ a chopper-stabilized topology to sup-press offsets and 1/f noise that dominates in low-frequencydesigns. A fully-differential chopper-stabilized closed-loopamplifier [3] is used to provide 40 dB of gain. A programmableGm-C filter is used to reduce switching ripple to below thenoise floor. The outputs are then fed into a variable-gainamplifier (VGA) with 6 programmable gain settings from 0to 34 dB and 7 variable high-pass corners, including a sub-Hzcorner formed by pseudoresistors.

B. Band Energy Extractor

Simultaneously calculating signal energy in multiple bandsis necessary to decode neuronal activities [1][4]. To accomo-date subject variation and various classification algorithms, thefrequency band selection, integration gain, integration durationshould be fully programmable. Previous implementations ofenergy estimators have been reported in [5][6]. In [5], hetero-dyning dual-nested chopping architecture enables selectabilityof the center frequency (fo) and bandwidth (BW), while

eliminating offsets and low-frequency noise. However, the het-erodyne chopping architecture requires two relatively power-hungry front-end low-noise amplifiers to extract spectral powerfrom one frequency band. In addition, the fo trim step size(5Hz) is too coarse to realize stagger tuning [6] especiallyin α and β bands. In [6], Gm-C filters are used to realizea stagger-tuned fourth-order bandpass filter, followed by asquaring circuit and a leaky integrator. However, the fo and Qof the band-pass filter (BPF) can not be independently tuned.In addition, the precise location of fo requires trimming dueto process variation in the bias current. Here we present thedesign of a 2.6µW band energy extractor that simultaneouslyoutputs the real-time energy in four independently tunablefrequency bands. Switched-capacitor (SC) techniques are usedhere to realize tunable band-pass filter and integrator. PreciseSC frequency responses are obtained without external trim-ming because frequency response only depends on capacitorratios and clock frequency. The band energy extractor consistsof a tunable 4th-order SC BPF, a continuous-time Gilbert-cellmultiplier, and a tunable SC integrator (Fig. 1).

Two stagger-tuned 2nd-order SC biquad sections are usedto realize a programmable 4th-order BPF. Fig. 2 shows thesimplified schematic of one 2nd-order SC biquad section. foand Q are determined by:

fo =C3

C2fc

1

2π(1)

Q =C2

C1(2)

φ1,2 represent two non-overlapping phases. Dual-switchconfigurations with minimum-sized switches are used to re-duce stray capacitance errors and charge injection [8]. Theswitches connecting to the virtual ground nodes near the OTAinputs are turned off first during φ1a,2a, so that the chargeinjected is the same from one clock cycle to the next and canbe considered as a DC offset.

Fig. 2. Schematic of the 2nd-order SC biquad.

To achieve a wide tuning range and fine tuning stepsfor fo, coarse tuning adjusts the center frequency fo by

varying the divided clock frequency fc in octave steps. Finetuning varies the fo within each coarse frequency step bycontrolling the capacitor banks C3. Fine tuning provides 16center frequencies spread logarithmically over each octave offrequency. This technique provides both a wide tuning rangeand fine frequency steps, which is consistent with the com-mon frequency bands used in ECoG/EEG applications, wheresmaller frequency steps are desired in the low frequencies toresolve consecutive bands within a few Hz of each other.

By adjusting the C1 capacitor banks, the Q is tunable from0.5 to 8 over 16 linear steps. To save area, we use linearcombinations of 7 capacitors to realize 16 Q values (Eqn. 2).In C1 capacitor banks, unused capacitors are connected to theoutput on one end, and virtual ground on the other to reduceswitching glitches in the output [7].

The biquad OTAs are realized with fully-differential tele-scopic two-stage op-amps. The OTA bandwidth needs tobe at least 5 times fc to reduce the effects of finite OTAbandwidth on SC operation [9]. When fc is varied to tunethe biquads to different frequencies, the bias currents in theOTAs are digitally adjusted accordingly to save power. SCcommon-mode feedback (CMFB) is used as a convenient andpower-efficient approach to ensure a stable and well-controlledcommon-mode operation.

Fig. 3 shows the multiplier circuit that squares the signalsfrom the BPF. The BPF outputs are AC-coupled into themultiplier to reject DC offsets. The multiplier consists of asubthreshold CMOS Gilbert multiplier core that squares theinput voltage, a transimpedance stage, and an output stagethat lowers the output impedance. By sensing the CM voltageat the output and feeding the CMFB control voltage to thetransimpedance stage, only one CMFB loop is required. Threebits of current tuning at the outputs of the transimpedancestage are used to trim the differential DC offsets. This blockalso functions as an anti-aliasing filter for the SC BPF.

Fig. 3. Schematic of the multiplier and the SC integrator.

We used a SC technique to realize a lossless integrator withprecise and adjustable integration window and gain. An area-efficient approach [10] is employed to realize large integrationtime constants (Fig. 3). This operation effectively attenuatesthe input voltage by a factor C3/C2, then integrating it ontoC2 through C1. The unity gain frequency of the integrator and

the integration time constant are approximately given by:

fu =1

2π

C1

C1 + C2

C3

C2fc (3)

τ =1

2πfu(4)

The integration output is reset periodically by a variablereset clock, divided from its SC clock. Because the gain of theintegration can be approximated as the ratio of the reset timewindow and the time constant (Trst/τ ), C2 can be selected tovary τ , and thus the gain of the integration.

C. Clock Generation

As shown in Fig. 1, four sets of independently pro-grammable SC BPF and integrator clocks are derived froma 160kHz on-chip crystal oscillator. A 20kHz chopper clockis chosen to maintain compatility of the chopper-stabilizedamplifier and all the SC blocks. Because discrete-time SC op-erations are sensitive to the sampling instant, the SC integratorclocks are shifted by 90 degrees to avoid sampling transientsfrom the SC BPF. Programmable SC BPF clocks are derivedfrom in-phase (I) of the 20kHz clock, and programmable SCintegrator and reset clocks are derived from the quadrature-phase (Q).

D. Control Logic

The control logic supplies the synchronization and resetcontrols for multiplexing the four integrators in a round-robinfashion. The synchronization pulses are immediately followedby the reset pulses.

III. EXPERIMENTAL RESULTS

EPIC was fabricated in a 0.13 µm CMOS process. System-level performance is summarized in Table I. The total currentdraw is roughly 9 µA from a 1.2V supply: 2.7µA from thechopper amplifier/VGA, 2.6 µA from the four energy extrac-tors combined, 2.7µA for bias generation, and approximately 1µA for the auxilary circuitry such as crystal oscillator, digitalclock generation and logic. The die photo is shown in Fig.4(a). The total active area is 1400 µm by 2000 µm, and eachenergy extractor occupies 0.46 mm2.

A. Characterization of the BPF

Fig. 5(a) shows the coarse fo tuning from 3.12 to 200Hz,and Fig. 5(b) shows the fine fo tuning from 200 to 400Hz, bothwith logarithmically incremental steps. 16 Q tuning frequencyresponses from Q = 0.5 to 8 are illustrated in Fig. 5(c) withfo set to 200Hz.

B. Multi-band Spectral Analysis

The fo and Q of the 2nd-order biquad sections are tuned torealize an overall 4th-order Butterworth BPF responses. BPFresponses in four common frequency bands used in ECoGresearch (α or 8-12Hz, β or 18-26Hz, low-γ or 30-50Hz, andγ or 70-100Hz) are synthesized by configuring the two biquads(Fig. 6(top)). Close resemblance between the measured (solid

Fig. 5. Measured frequency responses of one biquad: a) coarse fo tuningwhen fc is varied; b) fine fo tuning when C3 is changed; c) Q tuning whenC1 is changed.

Fig. 6. Top: measured frequency response (solid) compared to theoretical(dotted) of BPF tuned to α, β, low-γ and γ bands; bottom: measured input-referred noise plots of LNA, VGA and BPF tuned to these four bands.

line) and the theoretical (dotted line) BPF responses wereobserved.

Fig. 6(bottom) illustrates the input-referred noise spectrumat the output of the VGA and BPF when tuned to the fourbands described above. The AFE is set to the maximum gainin order to characterize the noise performance when signal isweakest. The AFE with a 85nV/

√Hz noise floor limits the

resolution. Flicker noise and lower bias currents used in the αand β bands results in slightly higher noise. The integratedinput-referred noise within the four passbands at the BPFoutput are 0.3, 0.29, 0.31, and 0.35µV respectively. The input-referred noise over the same bands at the output of the LNAand VGA alone are 0.18, 0.21, 0.31, and 0.34µV respectively.

A 6-second pre-recorded human ECoG waveform [11] wasprocessed by the chip. Fig. 4(c) compares the measured (solid)with the modeled (dashed) energy-extractor responses fromfour simultaneously recorded freqency bands. Close matchingwas observed.

Fig. 4. Left: die photo; middle: performance comparison table with [5]; right: theoretical (dashed) and measured (solid) energy profile in a) signal, b) α, c)β, d) Low γ, e) γ band for a 6-second ECoG waveform [11].

IV. IN-VIVO EXPERIMENT RESULTS

An in-vivo ECoG recording was performed from the pri-mary motor cortex of a pigtailed macaque monkey (Macacanemestrina), through a 32-electrode subdural array (PMTCorp.). The electrodes were platinum, had an exposed diameterof 0.075 mm and impedances of 50-100 kΩs measured at 1kHz. EPIC was connected directly to the ECoG electrodesthrough a 0.16 Hz high pass DC blocking RC filter.

To assess the fidelity of the signals recorded using EPIC, wecompared the output of EPIC to the simultaneously-recordeddigitized output of a 24-bit ADC (gUSBamp, Guger Tech.)sampling at 2.4 ksps/s. Fig. 7 shows two 1-second recordingsegments: the first shows activity in the β/low-γ band; thesecond shows ECoG activity with no increased frequency-specific components (baseline). No noticeable difference wasobserved between the EPIC (solid) and the gUSBamp (dotted)recordings. The PSD (power spectral density) illustrates theincreased power in the 15-45Hz range in the first segmentcompared to the second.

Fig. 7. Recording of in-vivo ECoG data from an awake monkey with EPICand a commercial ADC (gUSBamp). PSD and time-domain representationsof two segments: I. β/low-γ activity; II. baseline activity.

V. CONCLUSION

We present a four-band EPIC with 6.4 µW core power dissi-pation and 0.4 µVrms input-referred noise floor integrated overECoG/EEG-relevant frequency bands. This chip conditionsthe signal and simultaneously extracts energy from four pro-grammable bands. The broad tuning range and logarithmicallyincremental fine tuning steps of the band energy extractors aretailored for ECoG signal characteristics. This work featuresprogrammable multi-band spectral analysis with comparablepower consumption to the state-of-the-art.

VI. ACKNOWLEDGEMENT

The authors gratefully acknowledge Reinhold Scherer andFelix Darvas for their pre-recorded ECoG data set.

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