A Low-Leakage 2.5GHZ Skewed CMOS 32-Bit Adder For Nanometer CMOS Technologies Advanced VLSI Course...

A Low-Leakage 2.5GHZ Skewed CMOS

32-Bit AdderFor

Nanometer CMOS Technologies

Advanced VLSI Course Seminar December 28, 2006

Peresented by: Rabe’e Majidi Advisor: Dr Mehdi FakhraeeAdopted: ISSCC 2005/Session20/Processor Building Blocks/20.4

2

Outline

Introduction

Leakage-optimized skewed-CMOS logic for

circuit design-driven leakage reduction

Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture

- Latches and flip-flops for Skewed CMOS logic

Measurement results of four adder cores using different

90nm CMOS device options, sleep transistor technique,

and body biasing

Conclusion

Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

3

Outline

Introduction







and body biasing

Conclusion


4

Leakage power control, why?

With technology scaling → leakage power of idle units becomes a large fraction of the total chip power [4].

Sub-threshold

leakage power is soon

expected to dominate the

total power consumed by

a CMOS circuit [2].

Fig.1. Power trends of high performance microprocessors [2].

5

Charge Leakage

CL

Clk

Clk

Out

A

Mp

Me

Leakage sources

CLK

VOut

Precharge

Evaluate

Dominant component is sub-threshold current

Fig.2.Charge Leakage source, [3].

6

Leakage power control methods

The custom methods of Leakage power control [4]:

Dual threshold voltage Dynamic sleep transistor Body biasing techniques Clock gating

7

Using Dual threshold voltage

Fig.3. Standard domino logic circuits. (a) Standard low-Vt domino logic circuit. (b) Standard dual-Vt domino logic circuit. High-Vt transistors are symbolically represented by a thick line in the channel region [2].

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Using Dual threshold voltage

In a dual- domino circuit, all of the transistors that can be activated during the evaluation phase have a low-Vt .

Alternatively, the precharge phase transitions are not critical for the

performance of a domino logic circuit. Therefore, those transistors

that are active during the precharge phase have a high-Vt.

If all of the high-Vt transistors are cutoff in a dual- domino logic circuit, the leakage current is significantly reduced as compared to a low-Vt

circuit.

9

Dynamic Sleep transistors

Fig.4.Sleep switch dual-Vt domino logic circuit technique. High-Vt transistors are symbolically represented by a thick line in the channel region [2].

10

Body biasing techniques

Fig.5.Transition based forward body biasing with low skew forward body bias [5].

11

Clock gating

Adopted : ISSCC 2003/Session6/Low power digital techniques/6.1/slides

12

Active Leakage Control

Adopted : ISSCC 2003/Session6/Low power digital techniques/6.1/slides

13

Outline

Introduction







and body biasing

Conclusion


14Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

18

Outline

Introduction







and body biasing

Conclusion


23

Outline

Introduction







and body biasing

Conclusion


27

Outline

Introduction







and body biasing

Conclusion


31

Outline

Introduction







and body biasing

Conclusion


33

References

[1] Klaus von Arnim, Peter Seegebrecht, Roland Thewes, Christian Pacha, Infineon Technologies, Munich, Germany,Christian Albrecht University, Kiel, Germany,” A Low-Leakage 2.5GHz Skewed CMOS 32b Adder for Nanometer CMOS Technologies” , ISSCC 2005/Session20/Processor Building Blocks/20.4,pp.380-381,Feb.,2005

[2] Volkan Kursun, Student Member, IEEE, and Eby G. Friedman, Fellow, IEEE, “ Sleep Switch Dual Threshold Voltage Domino Logic With Reduced Standby Leakage current” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 5, MAY 2004

[3] Jan.M.Rabaey, Anantha Chandraksan, Borivoje Nikolic, “Digital Integrated Circuits A Design Perspective”, Second Edition, 2005

34

References

[4] James Tschanz, Siva Narendra, Yibin Ye, Bradley Bloechel, Shekhar Borkar, Vivek De,

Intel, Hillsboro, OR, “Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors”, ISSCC 2003 / SESSION 6 / LOW-POWER DIGITAL TECHNIQUES / PAPER 6.1, pp. 102-103, Feb.,2003

[5] S. Jayapal and Y. Manoli, Chair of Microelectronics, Department of Microsystems Engineering (IMTEK), University of Freiburg, Georges-Koehler-Allee 102, 79110 Freiburg, Germany, “Monotonic transition based forward body bias for dual threshold voltage low power embedded processors”, Adv. Radio Sci., 4, 269–273, 2006, www.adv-radio-sci.net/4/269/006/

© Author(s) 2006. This work is licensed under a Creative Commons License.

A Low-Leakage 2.5GHZ Skewed CMOS 32-Bit Adder For Nanometer CMOS Technologies Advanced VLSI Course...

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