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A HIGH dI/dt CMOS DIFFERENTIAL OPTICAL TRANSMITTER FOR A LASER DIODE APPROVED: ____________________________________ Martin A. Brooke, Chairman ____________________________________ Joy Laskar ____________________________________ Russell Callen ____________________________________ Thomas Habetler ____________________________________ ?????? Date approved by chairman:_____________
Transcript of A HIGH dI/dt CMOS DIFFERENTIAL OPTICAL TRANSMITTER FOR …mbrooke/Thesis/sungyoung.pdf · This...
A HIGH dI/dt CMOS DIFFERENTIAL OPTICAL
TRANSMITTER FOR A LASER DIODE
APPROVED:
____________________________________
Martin A. Brooke, Chairman
____________________________________
Joy Laskar
____________________________________
Russell Callen
____________________________________
Thomas Habetler
____________________________________
??????
Date approved by chairman:_____________
ii
TABLE OF CONTENTS
ACKNOWLEDGMENTS ......................................................................... iii
LIST OF TABLES .................................................................................... vii
LIST OF FIGURES .................................................................................viii
SUMMARY ..................................................................................... xi
Chapter I INTRODUCTION .............................................................. 1
Chapter II BACKGROUND ................................................................ 7
2.1 Optical Interconnect Systems and Optical Media................... 7
2.2 Optical Sources ..................................................................... 10
2.3 Optical Transmitters.............................................................. 14
2.4 Eye Diagram ......................................................................... 19
Chapter III Through-Silicon Optical Interconnect Systems .................... 23
3.1 Introduction and Applications............................................... 23
3.2 Optical Devices..................................................................... 25
3.3 Single-Ended Transmitter Design......................................... 28
3.4 Single-Ended Receiver Design ............................................. 31
3.5 Two-Layer Systems .............................................................. 34
3.6 Three-Layer Systems ............................................................ 38
Chapter IV DIFFERENTIAL LASER DRIVER..................................... 41
4.1 Introduction........................................................................... 41
4.2 Differential Transmitter Design............................................ 44
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4.3 Simulations ........................................................................... 48
4.4 Layout .................................................................................. 52
4.5 Scalability ............................................................................. 53
Chapter V PACKAGING PARASITIC CONSIDERATION................ 55
5.1 Introduction........................................................................... 55
5.2 Background ........................................................................... 57
5.3 Modeling of the Parasitics .................................................... 59
5.4 Differential Topology ........................................................... 65
5.5 Decoupling Capacitors.......................................................... 67
5.6 Parasitic Effect Simulation ................................................... 69
5.7 Chip Layout .......................................................................... 74
5.8 Measurements ....................................................................... 76
Chapter VI A DIFFERENTIAL LASER DRIVER FOR LVDS
STANDARD......................................................................... 85
6.1 Introduction and Application ................................................ 85
6.2 Differential Transmitter Design for LVDS Standard............ 87
6.3 Simulation and Layout.......................................................... 91
Chapter VII CONCLUSIONS AND PROPOSED FUTURE
RESEARCH........................................................................... 96
6.1 Contribution ........................................................................... 96
6.2 Future Research ..................................................................... 99
6.3 Conclusions.......................................................................... 101
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Appendix A BRIEF LVDS SPECIFICATION ................................... 103
Appendix B EDGE EMITTING LASER FABRICATED IN
GEORGIA TECH ........................................................... 105
Appendix C HSPICE INPUT CONTROL FILES AND BSIM
MODEL PARAMETERS USED IN SIMULATION..... 111
REFERENCES .................................................................................. 143
VITA .................................................................................. 153
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LIST OF TABLES
Tables Page
1.1 List of recently published optical transmitters..................................... 3
4.1 Design specification of the differential laser driver........................... 43
5.1 The parameter values for the model of bonding wires ...................... 60
5.2 The length and width of metal strips in PCB..................................... 62
5.3 The value of parasitic model.............................................................. 64
6.1 Design specification of the differential laser driver for LVDS.......... 86
7.1 The performance comparison of the transmitter in this research
with recently published transmitters .................................................. 97
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LIST OF FIGURES
Figures Page
2.1 A block diagram of a typical optical communication system.............. 8
2.2 The light output versus current characteristic of Laser and LED ...... 12
2.3 An example of the LED driver circuit I ............................................. 15
2.4 An example of the LED driver circuit II............................................ 15
2.5 An example of the laser driver I ........................................................ 18
2.6 An example of the laser driver II ....................................................... 18
2.7 Characteristics of an eye diagram...................................................... 20
2.8 SONET eye diagram mask................................................................. 22
3.1 Diagram of vertical optical interconnect system ............................... 24
3.2 Illustration of the optical device integration on Si circuit substrate .. 26
3.3 Circuit schematic of single-ended transmitter ................................... 28
3.4 The microphotograph of the transmitter with integrated LED .......... 30
3.5 The measured eye diagram of the integrated transmitter
at 155 Mbps .................................................................................... 30
3.6 Overall circuit schematic of the receiver ........................................... 31
3.7 The microphotograph of the receiver with integrated
I-MSM detector.................................................................................. 32
3.8 The measured eye diagram of the integrated receiver at 155 Mbps .. 33
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3.9 Test setup block diagram for through-wafer system.......................... 35
3.10 The microphotograph of the OEIC for two-layer system .................. 36
3.11 The microphotograph of the two-layer system .................................. 36
3.12 The measured eye diagram of two-layer system at 10 Mbps............. 37
3.13 The measured eye diagram of two-layer system at 40 Mbps............. 37
3.14 Layout of the OEIC for three-layer system........................................ 39
3.15 Microphotograph of three-layer system............................................. 40
3.16 The measured eye diagram of three-layer system at 1 Mbps............. 40
4.1 Design procedure of differential transmitter...................................... 42
4.2 A differential laser driver................................................................... 46
4.3 The optimization in terms of the transistor size................................. 47
4.4 Equivalent Model of a laser diode ..................................................... 48
4.5 Transient response of 1 Gbps differential laser driver....................... 49
4.6 Temperature simulation at 27 and 200 degree................................... 50
4.7 Transient response of differential laser driver at 2 Gbps................... 51
4.8 MAGIC layout of the driver .............................................................. 52
4.9 MAGIC layout of the driver using 0.18 µm technology.................... 54
4.10 Transient response of differential driver at 10 Gbps ......................... 54
5.1 The example of the delta-I noise in a circuit...................................... 58
5.2 The PCB for the driver testing ........................................................... 61
5.3 The diagram of metal strip in PCB .................................................... 62
5.4 The final equivalent model of packaging........................................... 63
5.5 Bias current comparison between single-ended and differential
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drivers ................................................................................. 66
5.6 The model of the capacitor ................................................................ 68
5.7 Parasitic impedance effect simulation ............................................... 70
5.8 Output signal with the ideal decoupling capacitor............................. 71
5.9 Output signal with the real model of 10 nF decoupling capacitor ..... 72
5.10 Cadence layout of the chip submitted to fabrication ......................... 75
5.11 The block diagram of the test structure.............................................. 77
5.12 Microphotograph of the chip ............................................................. 78
5.13 Test board with a bonded chip ........................................................... 79
5.14 622 Mbps pulse waveform................................................................. 82
5.15 622 Mbps eye diagram....................................................................... 82
5.16 900 Mbps pulse waveform................................................................. 83
5.17 900 Mbps eye diagram....................................................................... 83
5.18 1 Gbps pulse waveform ..................................................................... 84
5.19 1 Gbps eye diagram ........................................................................... 84
6.1 The differential amplifier for the pre-driver stage ............................. 89
6.2 The overall schematic of the driver for LVDS .................................. 90
6.3 Transient response of LVDS compatible differential laser driver
at 1 Gbps ................................................................................... 92
6.4 The layout of the overall driver for LVDS ........................................ 93
6.5 The final layout of the whole chip submitted to fabrication.............. 94
6.6 Microphotograph of the chip for LVDS compatible driver ............... 95
ix
SUMMARY
As high data rate and large throughput are necessary in telecommunication
systems, optical communication systems have become attractive solutions to cope with
bottleneck of the electrical communications. In optical communication systems, an
optical transmitter is one of the key components, where it performs as the interface
between the electronics and the emitters. It is very challenging to design optical
transmitters since its requirements of large output current and high speed are
contradictory, necessitating a large driving signal and large output transistors.
To date, the majority of optical transmitters have been designed using GaAs HBT
or GaAs MESFET due to wider bandwidth and good quality of passive components.
However, the standard digital CMOS technology provides advantages such as low power,
low cost of fabrication due to high yield, and a higher degree of integration. Thus, Si
CMOS technology, which is well known for low cost and high density is preferred for
design of optoelectronic circuitry.
This thesis describes the development of a high dI/dt differential transmitter
meeting greater than 1 Gbps data rate for free-space optical communication. Since the
performance of the system is limited by unwanted packaging parasitics as the data rate is
increased, the equivalent circuit model of parasitics is developed and incorporated in the
design process. To overcome the effect of parasitics, the solution using a decoupling
capacitor is suggested and verified in the simulation and measurement. To test optical
transmitters, chip-on-board (COB) technology is employed and printed circuit board
(PCB) is designed and manufactured for it.
In addition, the optical transmitter compatible with low-voltage differential signal
(LVDS) that is one of the IEEE standards is introduced. The simulation results show that
the transmitter can meet the 1 Gbps data rate.
1
CHAPTER I
INTRODUCTION
As high data rate and large throughput are necessary in telecommunication
systems, optical communication systems have become attractive solutions to cope with
bottleneck of the electrical communications [1-6]. Compared to the conventional
electrical counterparts, optical communication can provide larger bandwidth, smaller
channel crosstalk, shorter interconnection delays, and lower levels of power
consumption. Thus, it is commonly used in digital transmission system such as long and
short haul tele-communication and data communication, and also used in many
applications such as optical storage system, printers, and cable TV [7].
The typical optical communication system consists of a transmitter, optical
source, transmission media, a detector, and a receiver [8]. In such a system, an optical
transmitter is one of the key components, where it performs as the interface between the
electronics and the emitters. It is very challenging to design optical drivers since its
requirements of large output current and high speed are contradictory, necessitating a
large driving signal and large output transistors. Therefore, suitable circuit structures,
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suitable decoupling techniques, and a series of optimization steps are necessary for
optical transmitters.
To date, to attain the high-speed data rates, many researchers have designed and
fabricated optical transmitter using various technologies different applications such as
GaAs MESFETs, AlGaAs/GaAs HEMTs, AlGaAs/GaAs HBTs, Si Bipolar transistors, or
SiGe Bipolar transistors [9-18] as shown in Table 1.1. However, those technologies are
not compatible with the non-optoelectronic digital circuits that are widely used in
telecommunications.
The enormous development of research in the field of optical transmitter in
different technologies is not only because bipolar or GaAs transistors usually provide
wider bandwidth, but also because the process technology associated with these
transistors can provide relatively good quality of passive components such as resistors
and capacitors. However, standard digital CMOS technology provides advantages such as
low power, low cost of fabrication due to high yield, and a higher degree of integration
which gives more function blocks in a given size [19].
In the past years, standard digital CMOS technology has been steadily improved
[20,21], and therefore, is intruding the area of other technologies. In addition, new
technology such as Epitaxial-Lift-Off (ELO) [22-26] is now available to integrate a
hybrid-material device into a silicon material substrate. This technology enables to
achieve low cost and high-speed optical communication systems.
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Table 1.1. List of recently published optical transmitters
Ref. Process
Channel Length
or
fT
Optical Source
Speed [Gbit/s]
Max. Output Current or
Output voltage
Eye Diagram BER Remark
[3] Si Bipolar 0.6 um Off-chip Laser 5 45 mA Yes No -Electrical test
[4] GaAs MESFET 0.5 um LiNbO
electro-optic Moculator
5 36 mA Yes No -Measured in
package
-Electrical test
[5] AlGaAs/GaAs HBT
105 GHz Modulator 20 4 Vpp Yes No
-On-wafer measure
-Electrical test
[6] AlGaAs/GaAs HEMT 0.3 um On-chip
Laser 20 90 mA Yes No - Measured in
package
-Electrical test
[7] AlGaAs/GaAs HEMT 0.2 um Modulator 30 2.2 Vpp Yes No
- Measured in package
-Electrical test
[9] CMOS 0.5 um On-chip VCSEL 2.5 1.6 mA Yes Yes -Optical test
[10] CMOS 1.2 um On-chip Laser 1 1.2 mA Yes Yes -Optical test
[11] CMOS 1.0 um On-chip VCSEL 0.622 40 mA Yes No -Optical test
[31] SiGe Bipolar 0.3 um Modulator 23 2 Vpp Yes No - Measured in
package
-Electrical test
[32] SiGe Bipolar 0.2 um Modulator 20 0.8 Vpp Yes No - On-wafer
measure
-Electrical test
[33] CMOS 0.8 um Laser 2.5 40 mA No No - On-wafer
measure
-Electrical test
[34] CMOS 0.35 um VCSEL 1 NA No No -Simulation results
4
Consequently, Si CMOS technology, which is well known for low cost and high
density is preferred for design of optoelectronic circuitry. Several CMOS driver circuits
have been previously reported for high-speed operation but they have provided small
output current to a laser to achieve high-speed [27-34].
As the data rate is increased, the performance of the system is limited by
packaging parasitics [35,36]. The output of optical transmitter is degraded when
packaging parasitics are combined with abrupt current ripple in bias lines. However not
enough research has been done on packaging parasitics with optical transmitter design.
Thus, thorough research is necessary to address the related issues such as the
simultaneous switching nose. Also, the extraction of packaging parasitics is required. The
primary objective of this research is to develop an differential optical transmitter suitable
for high-speed and high-power using standard digital CMOS technology. The CMOS
optical transmitter will be hybrid integrated with an edge emitting laser using ELO
technology. It is low cost at a given die size, easy to manufacture, and meets high-speed
requirement on optical communication.
In this research, two types of optical transmitters are introduced to achieve the
objective. First one is a scaleable, high dI/dt differential transmitter to meet greater than 1
Gbps data rate. Second one is the optical transmitter compatible with low-voltage
differential signal (LVDS) that is one of the IEEE standards to meet 1 Gbps data rate. To
test optical transmitters, chip-on-board (COB) technology is employed and printed circuit
board (PCB) is designed and manufactured for it. With this technology, 1Gbps
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performance of the first differential transmitter was achieved with 10-11 bit-error-rate
(BER) electrically due to the poor laser development.
This dissertation consists of 7 chapter. In chapter 2, background to design an
optical transmitter is reviewed. The brief description of optical communication systems
are reviewed and the each components related to optical transmitters are described. Basic
technologies of design optical transmitters for LED’s and lasers are presented and the
advantages and disadvantages of each design methods are addressed. A LED and a laser
are briefly compared. As criteria of evaluating the performance of optical transmitters,
eye diagram is discussed.
Chapter 3 starts with discussion of through silicon optical interconnect system
which is an example of free space optical communication. The MSM photodetector and
InP LED, which is integrated onto the circuit substrate using ELO technology are
described followed by the optical receiver and transmitter circuitry. Also, the test strategy
and methods used for verifying the performance of the system is described. Finally, 2 and
3 layer through silicon systems are implemented and the details of operation including
layout, integration of detector, and measurement results are presented.
Chapter 4 addresses the development and application of a scaleable differential
laser transmitter. The design, simulation, and layout of the differential transmitter are
presented in detail. The scaleability of the transmitter is discussed based on the
simulation using a different minimum gate-length.
6
Chapter 5 states the effect of packaging parasitics in optical transmitter design. In
first section, it starts with the description of the simultaneous switching noise caused by
packaging parasitics. The equivalent circuit model of parasitics is developed by spice
model generator of Advanced Design System (ADS) tool and the values of parasitics are
extracted. To overcome the effect of parasitics, two solutions are suggested. Using
differential topology in transmitter design, the current ripple in the bias line can be
minimized and using decoupling capacitors, the voltage bias is stabilized in the presence
of parasitics. The simulation results, a chip layout, and measurement results of
differential transmitter is presented with 1 Gbps speed operation.
Chapter 6 describes the development of LVDS compatible transmitter which
consists of pre-driver stage and laser driver stage. For high-speed and high-gain, a
differential amplifier with an additional current source are described in pre-driver stage.
The simulation results and layout are presented. However, the measurement results are
not available at the time of this writing due to the bonding problem.
The final chapter of this dissertation is devoted to summarizing the results and
contributions of this research. Also, the possible future work after this research of optical
transmitter is addressed.
7
CHAPTER II
BACKGROUND
In this chapter, three main part of the optical interconnect system are reviewed.
The first one reviewed is optical media which propagates light signal to the optical
detector. Next, two primary optical sources which generate light signal related to the
driving current are review. The next one reviewed is optical transmitter circuitry to drive
optical sources. In addition, the criteria such as eye diagram to evaluate the performance
of the system are reviewed.
2.1 Optical interconnect systems and optical media
An Optical communication system is similar in basic concept to any type of
communication system. The function of a general communication system is to transmit
the signal from the information source through the transmission medium to the
destination. A block diagram of a typical optical interconnect system is shown in Figure
2.1. It consists of a transmitter, optical source, optical media, optical detector, and a
8
receiver. At the transmitter, the information source provides electrical signal to a
transmitter circuitry and it drives an optical source such as a laser and a LED to give
modulation of the lightwave carrier. The optical source converts electrical signal to
optical signal and the light output is propagated through the optical media such as optical
fiber and free space. The light signal from the optical media is collected on an optical
detector such as avalanche photodiodes and p-i-n photodiodes and converted to the
electrical signal. Finally, the electrical signal is amplified and recovered by the optical
receiver.
Figure 2.1. A block diagrm of a typical optical communication system
For optical interconnects, optical transmission media is categorized into free
space, optical fibers, and integrated optical waveguides [1]. The difficulties associated
with the fiber-optic approach stem from the alignment requirements for the fibers and
detectors. Also, the fibers cannot be allowed to bend too much since bends cause
radiation losses. In waveguide approach, the difficulties lie on the requirement to
RecoveredInformation
InformationSource
OpticalTransmitter
OpticalReceiver
OpticalSource
OpticalMedia
OpticalDetector
9
efficiently couple into and out of the guides. Careful alignment of the sources with the
integrated waveguides is required.
The other major category of optical interconnects is free-space techniques which
light is propagated in the free space. Free-space interconnects can be distinguished
between two types of techniques, unfocused [37] and focused [38-40]. Unfocused
interconnections are established simply by propagating the optical signals to the entire
electronic chip. However, the system is very inefficient since only a small fraction of the
optical energy might be absorbed on the photosensitive areas of the detectors and the rest
is wasted. Therefore, inefficient use of optical energy may result in requirements for the
extra amplification of the detected signals on the chip. In focused interconnections, the
optical source is actually imaged by an optical element onto a multitude of detection sites
simultaneously. The efficiency of such a scheme can obviously exceed that of the
unfocused case, provided that the optical elements have suitable efficiency. However, the
disadvantage of the focused interconnect technique is the very high degree of alignment
precision that should be achieved and maintained to ensure that the focused spots are the
appropriate places on the chip.
10
2.2 Optical Sources
Optical transmitters in optical interconnection consist of two main parts, a driver
circuit and an emitter [41]. The driver circuit converts electrical signals into an emitter
drive current and the emitter converts this current into light. The two primary light
sources used in telecommunications are semiconductor lasers and light emitting diodes
(LED) [42,43]. These optical sources have several requirements for optical emitter. First,
they should be linear with the electrical input signal to minimize the distortion and noise.
Second, they should emit light at wavelengths which has low losses and low dispersion.
Last, they should have capability to maintain a stable optical output in the condition of
temperature variation.
In a forward biased p-n junction, the normally empty conduction band of the
semiconductor is populated by electrons injected into it by the forward current through
the junction, and light is generated when these electrons recombine with holes in the
valence band to emit a photon. The energy of the emitted photons is roughly equal to the
bandgap energy of the semiconductor material which gives a much wider spectral
linewidth. Therefore, the drawbacks of the LED are low output power, higher divergence
degree, and wide optical spectral bandwidth which are not suitable for high-speed
communication. However, the LED has been widely used in low-speed communication
as an alternatives to the laser since the LED has a number of distinct advantages which
are simpler fabrication, less expensive, high reliability, less temperature dependence,
simpler driver circuitry, and higher linearity. The LED has been developed for edge or
11
surface emission. The edge-emitting LED shows more output power and a somewhat
narrower spectral width since it has a structure more like a laser but it requires the
complexity both in fabrication and in driver circuitry. In contrast to the edge-emitting
LED, the surface-emitting LED shows long device lifetime, low cost, and insensitivity to
ambient temperature.
The term laser is an acronym for light amplification by stimulated emission of
radiation. The light is stimulated utilizing the addition of an optical cavity and mirror
facets to provide feedback of photons. The emission process of the laser can occur in two
ways, which are spontaneous emission and stimulated emission. First, spontaneous
emission is occurred with the same mechanism in which the atom returns to the lower
energy state in a random manner. Second, stimulated emission is occurred when a photon
having an energy equal to the energy difference between the tow states interacts with the
atom in the upper energy state causing it to return to the lower state with the creation of a
second photon. Therefore, LEDs and Lasers have different characteristics as shown in Fig
2.2. In Figure 2.2, it may be observed that the laser emits little light output in the region
below the threshold current but above threshold current, the light output increases
eminently and linearly for small increases in current though the device acting as an
amplifier of light. This linear region can be used for data transmission.
12
Figure 2.2. The light output versus current characteristic of Laser and LED
There are two broad kinds of lasers, edge emitting lasers and vertical cavity
surface emitting lasers (VCSELs). VSCEL has been interested because it has low
threshold current and a symmetric output for efficient optical coupling to the fiber.
However, it has shortcomings including small lifetime, high cost and short wavelength
because of the lack of mirrors for 1.3 to 1.55 µm. 1.3 to 1.55 µm wavelengths has been of
interest for fiber optic communication since the optical fiber has zero dispersion near the
1.3 µm wavelength and has lower loss near 1.55 µm wavelength although 0.85 µm range
is still useful since the wavelength is compatible with on-chip Si detectors.
Several kinds of structure have been developed such as Gain-guided lasers, Index-
guided lasers, and Quantum-well lasers for edge emitting lasers. The simplest and least
expensive laser is the double heterostructure Fabry-Perot (DH FP) laser. However, the
Current
LightOutput(Power)
Threshold current
Laser
LED
13
modulation bandwidth is limited by relaxation oscillations which is the oscillation
between the carrier and photon population when the current is suddenly increased. In
addition, it shows frequency chirp which is the critical for long haul communication due
to fiber dispersion. For long haul communication, distributed feedback (DFB) lasers has
been developed with single frequency operation. The structure is the distributed Bragg
diffraction grating which provides frequency selective feedback in the optical cavity.
For the high-speed communication faster than 10 Gbps, lasers cannot be used
with direct modulation due to chirp but they can be used with external modulator such as
electro-absorptive modulator and mach-zehnder modulator. As a result, the optical source
should be selected carefully in terms of the application area.
14
2.3 Optical transmitters
There are two categories in optical transmitter circuitry with respect to the optical
sources, LED and laser. Although the application of the LED is restricted compare with
the laser, it can be an effective alternative to the laser for low-capacity and short-distance
link such as local area network.
For the on-off keying modulation in digital transmission, the LED are operated with
switching on and off of a current in the range of a few tens to a few hundreds mA. This
current switching is performed in response to input logic voltage levels at the driving
circuit. A common method of performing this current switching operation of the LED is
shown in Figure 2.3. The common emitter configuration is adapted with a bipolar
transistor providing current gain. In this circuit, the output current flowing through the
LED is set by the value of R2. However, the switching speed is limited by the diffusion
capacitance which means that the bandwidth and current gain have the tradeoff relation.
To increase the switching speed, low impedance driver is developed as shown in Figure
2.4. In this configuration, the emitter follower stage is placed with the common emitter
stage to drive the LED. As well as these LED transmitters, many kinds of transmitter
circuitry have been developed in terms of the requirement such as emitter-coupled logic
(ECL) or transistor-transistor logic (TTL) compatibility [44-47]. In digital transmission,
the interface between the transmitter and a common logic family is a frequent
15
requirement. In addition, LED has been considered for analog transmission because of
the linear output response of the optical power as seen in Figure 2.2.
Figure 2.3. An example of the LED driver circuit I
Figure 2.4. An example of the LED driver circuit II
L E D
V in
V C C
V E E
R 1
R 2
LED
Vin
VCC
VEE
R1
R2
16
The laser transmitter circuitry is somewhat different from the LED drivers since
as shown in the light-versus-current characteristics of the laser in Figure 2.2, the light
output is very small until the DC current reaches the threshold current [48]. After the
threshold current, the optical power is approximately linear with current. The problem
associated with typical lasers is that the characteristic curve is not linear at high current
and tends to shift to the right as both the temperature and device ages are increased. This
results in unwanted changes in output power, extinction ratio, and turn-on delay in digital
transmission. Thus, the laser should be biased near the threshold current when it is in off
state to reduce the turn-on delay and to minimize any relaxation oscillations, and also to
easily compensate for variations in threshold due to temperature and device ageing. For
biasing the laser, a bias control circuit is necessary in designing laser driver circuits.
A simple laser driver circuit used to connect the output of a current driver circuit
directly to the laser diode is shown in Figure 2.5 [49]. The threshold current for a laser is
provided by Vbias and modulation current is provided by source resistor, Rmod,
respectively. This type of single-ended laser driver is typically used with low operating
speed due to the unwanted parasitic inductance from the package’s bonding wires. When
this parasitic inductance is combined with the capacitance of the laser driver circuits and
lasers, it degrades output of the laser’s rise time and causes power supply current ripple.
Another example of the laser driver circuit is shown in Figure 2.6 when the driver
circuit and the laser are placed in different package. In this topology, a matching circuitry
between the driver and the laser is necessitated to overcome the large impedance mis-
17
match. In this circuit, Ibias controls the DC threshold current and Imod provides the
modulation current for the laser.
With these laser drivers, many types of drivers has been developed with various
technology in terms of the different application areas [50-55]. As mentioned above, it
becomes critical to consider the interactions among circuitry, interconnections and
packaging at high-speed operation. As a result, the suitable topology should be selected
in the design of the drivers and also, interconnections and packaging should be
considered.
18
Figure 2.5. An example of the laser driver I
Figure 2.6. An example of the laser driver II
VCC
VEE
Vin-
IbiasImod
Laser
Laser
VSSVbias
InputSignal Rmod
19
2.4 Eye Diagram
To evaluate the system performance, the eye diagram is a simple method for
digital transmission systems [56]. The performance of the systems depends on the
amount of intersymbol interference (ISI) and noise [57]. ISI can be occurred when the
signal passes through the dispersive system. In optical interconnect system, dispersion is
associated with the fiber, coupler, the transmitter circuitry, and the receiver circuitry. ISI
is that the pulses corresponding to any one-bit smear into adjacent bits and overlaps. So,
if ISI is large enough, this might trigger a false detection in the adjacent time slot. As a
result, an increasing number of errors may be encountered as the ISI becomes more
pronounced.
When observing data transmitted by optical driver on the oscilloscope, there is a
visual method that is often used to qualitatively measure the properties of a recovered
data waveform. If the pulse stream is applied to the vertical input and the sampling clock
is applied to the external trigger, a waveform looking like a human eye is obtained. This
is called an eye-diagram due to its similarity of shape to a human eye.
An eye diagram is easily generated using an oscilloscope that is triggered by the
symbol-timing clock and keeping the curve trace for certain duration of time. The eye
diagram is a composite of multiple pulses captured with a series of triggers based on
data-clock pulse fed separately into the scope. The scope overlays the multiple pulses to
form the eye diagram.
20
Usually, long pseudo-random data patterns are often used when generating eye-
diagrams to guarantee that the eye-diagram is representative of virtually all possible
symbol transitions. By measuring the width of the eye opening both in the vertical and in
horizontal directions, the information about the system’s ISI, noise, and jitter is obtained
as shown in Figure 2.7. The jitter, which is due to variations in the pulse duration or the
accuracy of the symbol clock, will cause the eye closing in the horizontal direction. Noise
and ISI are indicated by the vertical width of eye diagram. The ideal decision sampling
point occurs at the time of maximum vertical opening. This point corresponds to the time
when the signal-to-noise ration is at its maximum. Also, the size and shape of the eye
diagram changes depending on the data rate.
Figure 2.7. Characteristics of an eye diagram
Optimumsampling time
Sensitivity totiming error
Distortion ofzero crossings
Noise marginPeak distortion
21
After the signal is displayed in the form of eye diagram in oscilloscope, the signal
should meet the certain criteria to ensure the proper performance of the system.
Therefore, eye pattern mask is defined and employed measuring the eye diagram. As an
example of eye mask, the SONET specifications provide a mask inside and around the
eye diagram with required parameter values that can sustain the system link BER as
shown in the Figure 2.7 according to the Bellcore’s technical report [58].
22
Rates X1 X2 Y1
OC-1 and OC-3 0.15 0.35 0.20
OC-9 through OC-24 0.25 0.40 0.20
Figure 2.8. SONET eye diagram mask [58]
Logic "1" level
1 + Y1
1
1 - Y1
0.5
Y1
0
- Y1
0 X1 X2 1 - X2 1 - X1 1
Logic "0" level
Time [UI]
Nor
mal
ized
Am
plitu
de
23
CHAPTER III
THROUGH-SILICON OPTICAL INTERCONNECT
SYSTEMS
3.1 Introduction and Applications
Advances in integrated circuit have remarkably increased device densities and
speeds. However a large portion of the available area and bandwidth is consumed by
interconnects. As line lengths get longer, propagation delays, crosstalk between lines, and
dominance of line capacitance will restrict the utility of conventional electrical
interconnections [2]. Therefore, new chip architectures are required to cope with
associated interconnect problems. One possible solution is multichip modules (MCM’s).
However, as the density of chips on an MCM substrate increases and the interconnections
between chips increase, problems with unwanted coupled noise and simultaneous
switching noise limit the scalability of these architectures [59]. Another approach is to
use vertical optical interconnections [60-66]. They provide high speed, high bandwidth,
24
low loss, small crosstalk, short interconnect delay, and massively parallel
interconnection.
In this chapter, through-wafer vertical optical interconnect system between
stacked silicon circuitry shown in Figure 3.1 is introduced. It is utilized by using
optoelectronic devices operating at wavelengths which silicon substrate is transparent. To
achieve the system, a receiver, a transmitter, and optical devices such as a LED and a
detector are contained. The OEIC (Opto-Electronic Integrated Circuit) was fabricated in
0.8 µm CMOS process through MOSIS foundry. Then optical devices were integrated
onto silicon circuit substrate using thin film hybrid integration technology. This
integration provides the reduction of the packaging parasitics between the optical devices
and the silicon circuits compared with hybrid packaging using wire bonding.
Figure 3.1. Diagram of vertical optical interconnect
Silicon Circuitry
Silicon
Emitter Driver
InGaAsP
Emitter
InP/InGaAsP Detector
Detector
InP/InGaAsP
Emitter
InGaAsP
Silicon Circuitry
Silicon Circuitry
Detector Amplifier
Emitter Driver Detector
25
3.2 Optical Devices
Optoelectronics have been explored as a solution to bypass bottlenecks in
electrical interconnections. The extent of the problem has justified the integration of
optical devices onto a fabricated circuit substrates. Monolithic integration of optical
devices and high-speed circuitry has been demonstrated. However, the costs of these
systems are expensive due to the expensive substrates, growth technologies, and poor
yield [67,68].
An alternative method for combing optical devices with electrical circuits is a
hybrid approach. Hybrid integration enables individual optimization of the optical
devices and of the electrical circuits. In this method, optical devices are grown and
fabricated on their own growth substrate and then attached onto silicon circuitry by either
flip-chip technology or thin film integration. Flip-chip technology attaches optical
devices onto a silicon substrate using bump bonds. However, bump bonding consumes a
large amount of expensive optical materials.
Thin film integration, bonding to the host substrate is performed using standard
microelectronic processing techniques since the devices are on the order of 0.01 to 5
microns thick [23][25]. Furthermore, only a small quantity of optical materials is required
to integrate a large number of host substrates minimizing the use of expensive optical
materials. Another advantage of thin film devices is integration into three-dimensional
systems [63], which are useful for parallel applications such as image processing.
26
In this research, InP based light-emitting diodes (LED’s) [69] and metal-
semiconductor-metal (MSM) photodetectors [70,71] are fabricated and integrated onto
silicon circuit substrate as illustrated in Figure 3.2. The operating wavelength of these
optical devices is in the range of 1.3-1.6 µm where silicon is transparent. The thin-film
optical devices are fabricated by epitaxial lift off (ELO) technology [23]. As shown in
Figure 3.2, the thin film materials and devices are processed separately and bonded
without degrading the quality of the devices by parasitics due to packaging.
Figure 3.2 Illustration of the optical device integration on Si circuit substrate.
Final Integration
27
For vertical interconnects, LED’s are used since they have demonstrated high
reliability, and are low cost, simple to fabricate. Also, LED’s can be operated at the
desired modulation speed up to 155 Mbps with good quantum efficiency. Although the
divergence angle of LED’s is large, it also results in a high degree of alignment tolerance
for the vertical interconnects. In the case of detectors, inverted MSM (I-MSM) detectors
are selected since they have low capacitance per unit area and high responsivity that are
important factors in design of high speed and low power receiver units. MSM detectors
have low capacitance but low responsivity because of the shadowing effect of the
electrodes. Therefore, I-MSM detectors are developed to overcome the low responsivity
of MSM’s defining electrodes on the bottom of the detector to eliminate the shadowing
effect.
To construct through-wafer system, 100 µm LED’s and 50 µm I-MSM
photodetectors are integrated onto transmitters and receivers respectively and then each
chip containing silicon circuits and integrated optical devices is stacked together.
28
3.3 Single-Ended Transmitter Design
The single-ended CMOS transmitter is designed to meet the SONET OC-3 speed
specification of 155 Mbps. The transmitter circuit was optimized to drive up to 80 mA of
output modulation current to the emitter. It consists of two tapered buffers, a current
switch, and a current mirror as shown in figure 3.3. The transmitter is fabricated through
the MOSIS foundry in a 0.8 µm Si CMOS process.
Figure 3.3 Circuit schematic of single-ended transmitter.
M1
M2
M3
M7
M5
M6
M9 M10 M11 M12
M4
M8
D1
I2
I1
V1
VDD
VSS
29
The two-stage tapered buffer input is designed to minimize power consumption at
desired speeds and begins with a minimum geometry inverter used to drive a current
switch. The ratio of two inverter sizes has the tradeoffs between speed, power, and chip
size. For the maximum speed, the ratio of 2.7 is rational but it reveals high power
consumption. If the ratio is above 2.7, speed is slightly decreased but also power
dissipation is decreased. Thus, the optimal value of the ratio considering the tradeoff
between speed and power is set to 5 for 155 Mbps. The current switch was used before
the power transistor stage to avoid large voltage spikes and signal distortion in the output.
In output stage, a current mirror for dc bias of the emitter is included for increased speed.
To test the optical performance of the transmitter unit, the transmitter circuits with
integrated LEDs were wire-bonded onto a quad flat pack. 27-1 psudo random bit
sequence (PRBS) were generated by Tektronix 1400TX and the emitted light was
detected by a New Focus 1811 receiver. A microphotograph of the transmitter with
integrated LED is shown in Figure 3.4. In Figure 3.5, the eye diagram of testing the
integrated chip is shown at 155 Mbps. Bit error rate (BER) was measured by Tektronix
1400RX and 10-13 was achieved at 100 Mbps.
30
Figure 3.4 The microphotograph of the transmitter with integrated LED.
Figure 3.5. The measured eye diagram of the integrated transmitter at 155 Mbps.
Transmitter Integrated LED
31
3.4 Single-Ended Receiver Design
The single-ended transimpedance receiver was designed and fabricated through
the MOSIS foundry in a 0.8 µm Si CMOS process [72]. To obtain the target bandwidth,
which is greater than 155 Mbps, the receiver used a multistage low-gain-per-stage open
loop configuration. The receiver consists of five identical cascaded stage with a current
gain of 3, an offset circuit, and bias circuitry as shown in Figure 3.6.
.
Figure 3.6. Overall circuit schematic of the receiver.
N2
N3
N1
N7a
N7 N4
N4a
Nb
P5 P8 P6
P6aP8aP5aPi2a
Pi2Pi1
Pi1a
Pba
Pb
Nia2
Nia1
Ni1
Ni2
2.4
2.4
2.4
2.4
2.4 2.4
2.4
2.4
2.4
7.2
7.2
7.2
7.22.4
2.4
2.4
2.4120
120
2.4
120
120
2.4
2.4
voutiin
Isink
Ioffset
Isource
VDD1
ig2
ig1
si1si2
VDD2
VSS1 VSS2
Stage 1Offset
BiasP
BiasN
RL
AI = 3 AI = 3 AI = 3 AI = 3 AI = 3
32
Since this receiver is a current –mode amplifier, the current gain of each stage, AI,
is set by the gate width ratio of two transistor in a current mirror. Also, overall
transimpedance gain of the receiver is given by
LLI RRAR *243*5** == (3-1)
Figure 3.7 shows the microphotograph of the receiver integrated with I-MSM
photodetector. To bond the thin-film detector to the input side of the circuit, two small
pads are required. The pad size should be small enough to minimize the pad capacitance
since this capacitance increases the total input capacitance of the circuit limiting high
bandwidth.
Figure 3.7. The microphotograph of the receiver with integrated I-MSM detector.
33
The receiver with integrated I-MSM detector was tested and an eye
diagram was measured using 27-1 PRBS input data which is generated by Tektronix
1400TX. The input signal is fed into a modulator to generate a light emitting with a laser
source. Then the lightwave is illuminated onto the I-MSM detector of the receiver. The
detected light signal is converted into an electrical signal and amplified in the receiver.
The output of the receiver is measured in an oscilloscope with an output load of 50 Ω.
Figure 3.8 shows the measured eye diagram at 155 Mbps. In eye diagram, top trace is the
clock signal and the bottom trance is the eye diagram of the amplifier output. Bit error
rate (BER) was measured by Tektronix 1400RX and 10-10 was achieved.
Figure 3.8. The measured eye diagram of the integrated receiver at 155 Mbps.
34
3.5 Two-Layer Systems
To demonstrate vertical optical interconnects, two-layer system is realized [64].
Each integrated circuit layer in the two-layer stack consisted of an optical transmitter and
an optical receiver. Each of the chips were integrated with a thin film LED and an I-
MSM photodetector. Figure 3.11 shows the microphotograph of each layer before
integrating of optical devices and stacking of two chips. This chip stacked with two
layers where the top chip is rotated 180o relative to the bottom chip as illustrated in
Figure 3.11. After all three layers were assembled, the system was wire-bonded into a
LDCC 44-pin flat package for testing.
To test the two-chip stack, the test set up is shown in Figure 3.9. 27-1 PRBS
digital signal from Tektronix 1400TX was fed into the bottom transmitter. Then the
transmitter supplies current to drive an emitter and the electrical input signal is converted
into the light output signal from the emitter. The voltages and currents in each circuits of
the system were controlled using Keithley 238 source measurement units. An
oscilloscope measured the output signal from the top receiver circuit. The two-layer
system performed well at 10 Mbps with 3.5 V power supply voltage for both the
transmitter and the receiver as shown in Figure 3.12. However, a ringing due to ground
bounce was noticeable in output eye diagram. It causes significant noise, as the bit rates
are higher as shown in Figure 3.13. This noise is primarily due to decoupling problems in
the test fixture. Therefore, the system worked up to 40 Mbps even though each
components of the system has been tested up to 155 Mbps.
35
Figure 3.9. Test setup block diagram for through-wafer system
Clo
ck
for T
ran
sie
nt o
utp
ut c
urv
e a
nd
BE
R s
yn
ch
ron
iza
tion
Mic
row
av
e L
og
ic
gig
a B
ER
T-1
40
0 T
X LE
D D
rive
r
Mic
row
av
e L
og
ic
gig
a B
ER
T-1
40
0 R
X
Te
ktro
nix
11
40
3A
Os
cillo
sc
op
e
Re
ce
ive
r
LE
DD
ete
cto
r
36
Figure 3.10. The microphotograph of the OEIC for two-layer system.
Figure 3.11. The microphotograph of the two-layer system
37
Figure 3.12. The measured eye diagram of two-layer system at 10 Mbps.
Figure 3.13. The measured eye diagram of two-layer system at 40 Mbps.
38
3.6. Three-layer systems
To demonstrate the applicability of through-wafer optical interconnects, a three-
layer system is also introduced [65]. The same components, which were used in two-
layer system are used in this system. The three-layer system was assembled by aligning
the individual layers using an infrared backplane mask aligner. After all three layers were
assembled, the system was wire-bonded into a 144-pin grid array (PGA).
Figure 3.14 shows the layout for three-layer system. In this layout, isolation
method was used to minimize the noise coupled from the digital section to the sensitive
analog input stage of the receiver since this system contains several digital blocks such as
a transmitter, a clock generator, and a comparator. Isolation method is to attempt to keep
the sensitive analog circuitry separated from the noisy digital circuitry, or to block the
transmission of the noise from the digital circuitry to the analog circuits using n-well or
p-well appropriately. In Figure 3.14, n-well and p-well contact are shown between the
receiver part on the left side and the digital blocks on the right side.
Figure 3.15 shows a microphotograph of the packaged 3-D systems, which is
measured to show the performance of the whole system.
The primary goal of this system is to demonstrate optical through-wafer
interconnect from the bottom layer to the top layer. First, the data from the bottom
transmitter goes to the receiver of the middle layer, then the middle layer routes the
39
receiver data through the comparator to the transmitter input. Last, the data is transmitted
from the middle layer to the top layer.
To test three-layer systems, the same test setup as in Figure 3.9 was used. 27-1
PRBS data was generated by pattern generator and the eye diagram is measured by
oscilloscope. BER was also measured by Tektronix 1400RX. The test results at 1 Mbps
was shown in Figure 3.16 with 1.3x10-9 BER. As well as two-layer systems, the speed of
the system is limited due to decoupling problem of the test fixture and signal coupling
within the high-pin PGA package. High-speed demonstrations would be enabled by
utilizing improved decoupling method, by using different package and by employing
differential topology in the design of CMOS transceiver circuits.
Figure 3.14. Layout of the OEIC for three-layer system
40
Figure 3.15 Microphotograph of three-layer system
Figure 3.16 The measured eye diagram of three-layer system at 1 Mbps.
41
CHAPTER IV
DIFFERENTIAL LASER DRIVER
4.1 Introduction
In chapter 3, the free space optical communication was implemented. However, as
the speed is increased, the receiver requires high incident optical power for high signal-
to-ratio (SNR) and high sensitivity. Therefore, the laser should be chosen for optical
source since it has low divergence degree and high power efficiency. A differential
CMOS transmitter circuit to drive a laser is introduced in this chapter. The driver was
fabricated in a 0.35 µm technology process through national semiconductor. A laser
driver circuit that is capable of operating above Gbps and providing large output current
for high optical power is designed for high-speed optical interconnect.
For the development of high-speed driver, the differential topology is employed to
stabilize current ripple in the power supply lines [73], which would otherwise corrupt the
laser output. Differential design minimizes simultaneous switching noise by using
parallel but inverted signal paths with subsequent subtraction of the two signals. In
42
addition to conventional differential pairs, current mirrors are used to provide adjustable
threshold current and modulation current for the laser.
In this research, the goal is to design the driver with greater than 1 Gbps speed
operation providing high modulation output current (up to 180 mA) to the laser. The
driver has been laid out using MAGIC layout tool. Then the parameters of the circuit
layout has been extracted and simulated. When the simulation result did not meet design
specification, the design procedure has been repeated as shown in Figure 4.1.
Figure 4.1 Design procedure of differential transmitter
D e s ig n
L a y o u t
E x tra c t io n
S im u la t io n
S p e c if i-c a t io n
F in a lL a y o u t
Y e s
N o
43
Final layout has been converted into cadence layout with existing electric static
protection pads, which is provided by National Semiconductor. After the chip was
fabricated, it has been tested to meet the design goal, which was predetermined.
The predetermined design specification of the transmitter is shown in the table
below. The specification was predetermined by the optical device group in Georgia
Institute of Technology.
Table 4-1. Design specification of the differential laser driver
Specification Predetermined Goal of Design
Speed Greater than 1Gbps
Output Current DC range: 0 – 30 mA
AC range: 0 – 180 mA
Current Density Less than 30uA/1um square meter
44
4.2 Differential Transmitter Design
The silicon CMOS high dI/dt differential laser driver circuit described herein was
designed to meet the predetermined specification. For giga bit interconnect, some laser
drivers using CMOS has been recently reported [27-35]. However, these laser drivers
provide small output modulation current as shown in Table 2.1. The driver in this
research consists of current mirrors and a current switch, as illustrated in Figure 4.2. In
this driver circuit, the output delivered to the laser diode is composed of Ith for dc biasing
the laser near the threshold current, and Imod for the modulation current above threshold.
In an integrated implementation, the diode would be removed and a laser would be
integrated instead of the diode. Also, Z1 would be replaced either a laser or a resistor. As
shown in Figure 4.2, the switching circuit is realized by differential NMOS transistors in
common source configuration. The current sources for dc biasing and modulation current
are realized by current mirrors, where a reference current should be supplied through the
external source measurement unit.
The transistor size is optimized for up to 180 mA peak-to-peak modulation
current and up to 30 mA laser-biasing current. The primary effects of determining the
operating speed are switching delay of input transistors and the RC time constant of wire
interconnect on a chip. As transistor size increases, higher output currents are achievable
but the speed is decreased since the gate capacitance of the input transistor increases the
total input capacitance, which is given by
45
noxtotal WLCC )(= , (4-1)
oxox
ox xC ε= ,
where the oxide permittivity εox is 3.9εo F/cm when silicon dioxide is used as the gate
insulator, xox is oxide thickness, and W and L are the width and the length of the input
transistor. In this expression, εo is the permittivity of free space and εo≈8.854×10-14 F/cm.
If total capacitance is increased, it causes large switching delay of the circuit.
Thus, the optimization of the transistor size is necessary for the design of the
driver circuit to provide large modulation current maintaining high-speed operation. Also
careful layouts to reduce parasitic capacitance of transistors are required. The simulated
results of the speed versus output current and speed versus input magnitude are illustrated
in Figure 4.3. The speed is proportional to input magnitude but inversely proportional to
output current. In Figure 4.3 (b), it is shown that the speed is saturated above 2 V peak-
to-peak input magnitudes since drift velocity of electron is saturated. As a result, the
optimal size of transistor has been selected to perform 1 Gbps operation driving proper
modulation current and laser-biasing current.
46
Figure 4.2. A differential laser driver.
D2
M1 M2
M5M6
M7M3M4
ImodIth
V2V1
VDD
VSS
Z1
47
(a) Speed versus output current
(b) Speed versus input magnitude
Figure 4.3. The optimization in terms of the transistor size
0
5
10
15
20
25
0 200 400 600 800
Output current (mA)
Spee
d (G
bit/s
)
0
2
4
6
8
10
12
14
0 0.5 1 1.5 2 2.5 3
Input magnitude (V)
Spee
d (G
bit/s
)
48
4.3 Simulation
The HSPICE simulation on the overall transmitter has been performed using 0.4
µm, BSIM level 4 model parameters (See Appendix II) provided by national
semiconductor. The simulation has been done with extracted SPICE files from magic
layout. Figure 4.5 shows the transient response of the driver at 1 Gbps speed with 180
mA output current. In the simulation result, the top trace represents the psudo random bit
input signal and the middle trace is the transient output. The bottom trace is the eye
diagram to prove that there is not any missing bit. As shown in the simulation results, the
driver works properly at the predetermined design specification.
For the SPICE simulation of the laser and the driver circuit, the electrical
equivalent circuit model of the laser is developed and presented as shown in Figure 4.4
[74,75]. For practical usage, it should be as simple as possible to minimize calculation
time.
Figure 4.4. Equivalent Model of a laser diode
Lb Rs
Rj CjCp
49
In this model, chip and package parasitics are included, but for simplicity they are
not incorporated in simulations. In Fig. 4.4, the components of the equivalent circuit
model are inductance Lb due to the wire bond, capacitance Cp of the laser chip, resistance
Rs from the metal contacts, capacitance Cj from the p-n junction, and resistance Rj from
the p-n junction. Using this equivalent model, optical output of the laser is treated as an
electrical output, which can be displayed by SPICE.
4.5 Measurement and Test Results
Figure 4.5. Transient response of 1 Gbps differential laser driver
50
Figure 4.6. Temperature simulation at 27 and 200 degree
Next, temperature is considered since integrated circuits slow as temperature
increases due to the mobility variation. Thus, this simulation is to verify that the driver
works properly at higher temperature. Figure 4.6 shows the transient response of the
driver with temperature variation at 27 degree and 200 degree. The top trace is the
transient output at 27 degree and the second trace is the eye diagram of the top trace. The
third trace represents the transient output at 200 degree and the bottom one is the eye
diagram of the third trace. As shown in Figure 4.5, output is a little slower at 200 degree
than room temperature 27 degree but still shows a wide-open eye diagram.
51
Figure4.7. Transient response of differential laser driver at 2 Gbps.
Figure 4.7 shows the transient response of the drive operating at 2 Gbps. The top
trace is the input signal and the middle trace is the transient output. The bottom trance
represents the eye diagram of the output current. Even though the laser driver was
designed and optimized for 1 Gbps operation with 180 mA modulation current, it worked
well at 2 Gbps as shown in Figure 4.7. Compared with the 1 Gbps simulation result, the
rising and falling time is a little slow but still works with a wide-open eye diagram.
52
4.4 Layout
The driver was laid out carefully for fabrication using magic layout tool as shown
in Figure 4.8. While the driver was laying out, every effort was made to minimize the
parasitic capacitance of input transistors since it was found out that the capacitance was
very critical for the system performance. In the layout, multiple finger structure with one
wide transistor is used to minimize the depletion capacitance such as metal to poly and
metal to metal.
Figure 4.8. MAGIC layout of the driver
53
4.5 Scalability
Since the driver has been designed using 0.35 µm standard CMOS process
without any passive components, the design is scalable, which means there is a room for
speed up in advanced technology. In the CMOS, the speed is related to gm/C. So, The
speed can be improved by a scale factor because the capacitance (C) of the device is
reduced while the transconductance (gm) of the device is almost same. The performance
scalability of the integrated circuits is important to reduce chip area and to improve the
circuit performance [76-80].
The driver in Figure 4.2 is scaled down from 0.35 µm to 0.18 µm with a scale
factor of 1.944 and the bandwidth of the driver increases from 2 Gbps to 10 Gbps as
shown in Figure 4.10. In this simulation, there are two factors increasing the speed. One
is from scaling down the minimum gate length and another is from decreasing the
modulation current from 180 mA to 25 mA. Since the total transistor size is depending on
the current density of the gate in CMOS, reduced current result in the smaller total
transistor size, which allows the smaller parasitic capacitance. Figure 4.9 shows the
layout of the driver that is scaled down using 0.18 µm technology.
In Figure 4.10, the top trace is the input signal and the middle trace is the transient
output. The bottom trance represents the eye diagram of the output current.
54
Figure 4.9. MAGIC layout of the driver using 0.18 µm technology.
Figure4.10. Transient response of differential driver at 10 Gbps.
55
CHAPTER V
PACKAGING PARASITIC CONSIDERATION
5.1 Introduction
The signal degradation due to the presence of the parasitics associated with
packages and bonding wires has been a crucial factor as the higher data rate and higher
density is required in telecommunication [81]. These parasitics causes switching noise
known as delta-I noise when the current is switched in power distribution systems [82-
84]. This noise degrades edge rate of digital signal, reduces noise margins, and finally
causes false switching of digital logics that is the error of the system. Therefore,
packaging parasitics should be included in the design of the drivers.
To date, silicon CMOS drivers for bit rates up to several gigabits per second for
low cost, low power consumption implementations have been reported. Also, delta-I
noise has been analyzed and investigated by many researchers [85-87]. However, the
parasites of the package and bonding wires have not been considered in the design of
56
these laser drivers due to the lack of efficient methods and models, although they are
bonded into a package.
In this research, an equivalent circuit model of parasitics containing bonding
wires and packages are developed. The equivalent model is included in HSPICE
simulation of the driver and shows the effect of the parasitics.
In order to solve the parasitic problem, the differential topology can be selected
instead of single-ended topology by stabilizing the bias current since it has symmetric but
inverse current flowing path to the power supply lines [88]. However, the effect of the
parasitics cannot be eliminated fully due to a device mismatch in the differential pairs and
a different delays in the current path, although it has better bias current stabilization
compared with single-ended version. Thus, use of an decoupling capacitor is also
suggested to eliminate the effect of packaging parasitics [89-93]. In the simulation of the
driver, actual equivalent model of capacitors is included to predict the precise effect of
decoupling capacitor when the driver is tested and compared with the ideal capacitor.
Finally, the differential driver described in chapter 4 has been tested with the
decoupling capacitor and shows the good accordance with the simulation results.
57
5.2 Background
In a single chip package and printed circuit board (PCB) system, voltage
fluctuation named simultaneous switching noise or delta-I noise has exceeding increased
and affected the performance of integrated circuits as the circuit transition time is
increased. The delta-I noise is caused by the parasitic inductance of the power supply
lines in the package and abrupt current change in the switching circuits.
To describe the mechanism of delta-I noise, a simple inverter with parasitic
inductance is shown in Figure 5.1. When the input signal of the inverter (Vin) switches
state from low-to-high or high-to-low, it causes an abrupt current change to the power
supply distribution system through the interconnections. This results in a voltage drop in
the power supply (Vp) in the presence of the parasitic inductance (L_parasitics) as
explained in
dtdILVnoise = (5-1)
The magnitude of the delta-I noise is proportional to the parasitic inductance and
power supply current variation. If the magnitude of the voltage drop becomes too large, it
results in the errors of the system. Therefore, the current variation should be reduced to
minimize the voltage drop and it can be achieved by choosing differential topology in
58
circuit design. Another way of reducing the delta-I noise is to minimize the parasitic
inductance with carefully selecting package and PCB. However, the delta-I noise is not
fully eliminated but partially reduced since the inductance has always a finite value in
bonding wires as well as in the package and PCB. Therefore, by placing the decoupling
capacitor near the internal power supply to provide charge during switching, delta-I noise
can be effectively reduced as illustrated in Figure 5.1.
Figure 5.1. The example of the delta-I noise in a circuit.
VpC_decouple
L_parasitics
Vin
59
5.2 Modeling of the parasitics
A lumped-element equivalent model (RLC) for the packaging parasitics is
developed to predict and analyze the behavior of the parasitics in the driver design. The
model includes package bonding wire impedance, PCB metal line impedance, and bias
wire impedance. The model and the values of the PCB impedance were generated and
extracted from Advanced Design System (ADS) design tool. And the inductive
impedance of bonding wires and bias wires were calculated [94] by
)1)4(ln(2
−+= δµπ
µr
o
dllL (5-2)
where µo is the permeability of free space, µr is the relative permeability of the bonding
wire material, d is diameter of the boding wire, l is the length of the bonding wire, δ is the
skin effect factor give by
)4tanh(25.0dds=δ , (5-3)
And the skin depth of the bonding wire material is given by
60
0µµπρ
rs
fd = (5-4)
where ρ is the resistivity of the bonding wire material and f is the frequency. The
resistive impedance of bonding wires is ignored since the length of bonding wires is very
short which means the associated resistance is very low.
To calculate the values of bonding wire impedance, the parameter values are
shown in Table 5.1. The material of bonding wires is gold.
Table 5.1. The parameter values for the model of bonding wires
Parameter Value Unit
µo 4π×10-7 H/m
µr 1 H/m
ρ 2.44×10-8 Ohms/m
l 3 mm
d 0.0363 mm
61
The PCB is specially designed and built for the driver testing. As shown in Figure
5.2, the board is designed as small as possible to minimize the parasitics. However, the
board has parasitic impedance in itself that should be modeled for realistic prediction of
the signal behavior. The size of the board is 4.5 cm × 4.5 cm. The model of metal strips
in the board is constructed by ADS with five-ladder structure. In the board, the metal
strip is partitioned into five parts as illustrated in Figure 5.3 for modeling since the metal
strip is tapered to fit SMA connectors and bonding wires.
Figure 5.2. The PCB for the driver testing.
62
Figure 5.3. The diagram of metal strip in PCB
To extract the values of the board impedance, the lengths and widths are shown in
Table 5.2. The material of the metal strip is tin.
Table 5.2. The length and width of metal strips in PCB
Parame
-ter l1 l2 l3 l4 l5 w1 w2 w3
Value 59.421
mil
16.745
mil
21.33
mil
27.735
mil
620.18
mil
10.01
mil
29.981
mil
49.894
mi.
l 2l 1 l 3 l 4 l 5
w 2w 1 w 3
63
Figure 5.4. The final equivalent model of packaging
L3
R3 C3
L2
R2 C2
L4
R4 C4
L5
R5 C5
L6
R6 C6
L7
L1
R1
Bia
s W
ire
Pri
nte
d C
ircu
itB
oa
rd T
race
Bo
nd
ing
Wir
e
64
The final equivalent model of packaging is shown in Figure 5.4. It consists of
bonding wire, board line, and bias wire parasitics. The value of parasitic impedance in the
model is given in Table 5.3.
Table 5.3. The value of parasitic model
Parameter Value Parameter Value
L1 105 nH C4 0.367874 pF
L2 1.38664 nH C5 0.367874 pF
L3 1.38664 nH C6 0.367874 pF
L4 1.38664 nH R1 0.1 Ω
L5 1.38664 nH R2 0.0280365 Ω
L6 1.38664 nH R3 0.0280365 Ω
L7 3.996 nH R4 0.0280635 Ω
C2 0.367874 pF R5 0.0280635 Ω
C3 0.367874 pF R6 0.0280635 Ω
65
5.3 Differential Topology
As described in Chapter 5.2, the performance of the IC is limited by the
packaging technology. To overcome the packaging restriction, the differential topology
can be used so as to greatly minimize the current ripples in power supply lines. Finally, it
results in reduction of delta-I noise.
To illustrate the stabilization of power supply lines in the differential topology,
the current ripple of a single-ended optical driver described in Figure 3.3 is compared
with that of the differential driver in Figure 4.2. These drivers have been simulated using
HSPICE. In Figure 13, the bias current of the single-ended version contains signal
components in it. However, the bias current of the differential version does not contain an
input signal component. Also, the ripple in the bias current is significantly reduced in the
differential version. These simulation shows a dramatic improvement in the current
fluctuation related performance of the differential driver over the single-ended design.
Hence, the differential topology should be used to reduce the effect of parasitic
inductance.
Although differential design is effective to reduce the effect of parasitic
inductance, current ripple in the differential version is small but clearly present as seen in
Figure 13. Therefore, if it is combined with the huge packaging parasitics, there is a
possibility that the output of the driver is corrupted.
66
(a) Current ripple of single-ended version
(b) Current ripple of differential version
Figure 5.5. Bias current comparison between single-ended and differential drivers
67
5.4 Decoupling Capacitors
As seen in Figure 5.5, the current ripple, which cause delta-I noise cannot be
eliminated fully although the differential topology is employed. Thus decoupling
capacitors are required to reduce the effect of the parasitics maintaining the constant dc
power supply levels. The effectiveness of the decoupling capacitors can be expressed by
the simple equation,
dtdVCI = , (5-5)
CI
dtdV = (5-6)
Equation (5-6) states that the voltage fluctuation in power supply line can be
suppressed by the capacitors. Therefore, by adding an additional proper decoupling
capacitance, the noise can be effectively reduced to the desirable level. In the ideal case
of capacitors, it is manifest that the improvement can be increased by using higher
capacitance according to equation (5-6). However, the value of decoupling capacitor
should be optimized since the real capacitors include a parasitic series resistance and an
inductance which is called the equivalent series resistance (ESR) and the equivalent
series inductance (ESL) as shown in Figure 5.6 [95,96]. In the presence of parasitics in
the capacitor model, it also causes voltage fluctuation although the magnitude is much
68
smaller than that of the case of the packaging parasitics. In addition, it causes resonance
that gives the signal attenuation because of the parasitic LC in the capacitor model.
Therefore, the value and the type of the decoupling capacitor for suppressing the delta-I
noise should be chosen carefully since some type of capacitors contains the higher
parasitic inductance than others. In this research, ceramic surface mount capacitors were
selected since it offers low parasitic inductance value and the value of the capacitance
was optimized using HSPICE simulation. On chip decoupling capacitor was embedded
on the circuit substrate as well to minimize the effect of the packaging parasitics.
Figure 5.6. The model of the capacitor
E S R
E S R
C
69
5.5 Parasitic effect simulation
The purpose of this simulation is to optimize the decoupling strategy, which
includes the placement, and value of capacitance required to minimize the effect of line
impedance to ensure that the circuit works in testing environment with real value of
parasitics such as line inductive impedance and board capacitive impedance. The model
values of the parasitic impedance were calculated as seen in Table 5.3. The parasitic
model is included between the power supply lines, Vdd and Vss.
In the simulation, ideal capacitor and the real capacitor model was compared each
other. It showed that the real model is practical since the simulation results with the real
model is consistent with the measured data. In the capacitor model, 1.12 nH of ESL,
10.015 nF of the capacitance, and 0.855 Ω of ESR provided by manufacturing company
was used. On-chip decoupling capacitor was embedded with a few tenth of pico farad but
it is not sufficient to suppress to the desired level of noise. Thus, the off-chip capacitor
was placed between bonding wire model and the board model in Figure 5.4 as well as the
on-chip capacitor. The simulation was performed at 1 Gbps by HSPICE using 0.35 µm
BSIM level 4 model parameter provided by national semiconductor. The simulation
results show that 10 nF of decoupling capacitor is enough to reduce the noise.
70
Figure 5.7. Parasitic impedance effect simulation
The figure above 5-7 shows the effect of the parasitic impedance. It was simulated
the parasitic model with no decoupling capacitance at all. The output affected by this
effect is shown in transient response analysis (the middle trace) and eye diagram (the
bottom trace). As shown in the simulation result, the output is totally distorted and the
eye is completely closed due to the effect of parasitic inductance and current ripples in
the power supply lines. This shows the importance of the decoupling capacitance
although the differential topology is employed. The simulation result illustrated that even
though the circuit may work in the simulation without considering the bias line parasitics,
it will not work in the real world where the parasitics are exhibited. To prevent this
71
unwanted situation, it is necessary to consider and predict the effect of the parasitics that
can come into real test environment and check the valid functionality of the driver.
(a) 1 nF capacitance
(b) 10 nF capacitance
Figure 5.8. Output signal with the ideal decoupling capacitor
72
To find the optimal value of decoupling capacitors to suppress the delta-I noise in
the driver, the simulation was performed with various values of capacitance. The figure
5.8 show the results of 1 nF and 10 nF decoupling capacitor with the parasitic model. The
simulation shows that 1 nF of capacitance is not sufficient to eliminate the effect of the
parasitics. Even with this small capacitance of 10 nF, the output was fully recovered to
the desired one, which has the same performance as shown in Figure 4.4. Therefore, 10
nF was selected for the optimal value for decoupling capacitor, which may be used in the
real test environment. However, since the ideal model of capacitor was used in this
simulation, the real model including parasitics should be incorporated in the simulation to
predict the realizable output of the driver.
Figure 5.9. Output signal with the real model of 10 nF decoupling capacitor
73
Figure 5.9 shows the result of the real capacitor model with the packaging
parasitics. In the simulation, it is found that the transient response seems a little slower
and the ringing cannot be eliminated perfectly unlike the result of the case of the ideal
capacitor model. But it still provides wide opened eye diagram and also shows the more
realistic result.
74
5.5 Chip Layout
As in the driver design in chapter 4, the driver was laid out carefully for
fabrication by MAGIC layout tool. Final layout has been exported into cadence layout to
be wired with existing static protection circuitry provided by nation semiconductor. In the
layout of this chip, the decoupling capacitor using metal1, metal2, metal3, and metal4
was embedded to prevent unwanted power supply ripple as the signal goes through the
driver circuitry.
The Figure 5.10 shows the layout of the chip submitted to national semiconductor
for fabrication performed in CADENCE tool. The lower side is driver part and the left
side is on-chip decoupling capacitor between Vdd and Vss. Two pads at upper part of the
driver are prepared for a thin-film laser integration. In the large space between two pads,
the laser will be integrated.
75
Figure 5.10. Cadence layout of the chip submitted to fabrication
The driver
Decoupling capacitor
76
5.5 Measurements
To verify the functionality of the driver, BER measurement was performed
observing time-domain transient output signal and eye-diagram at different speeds was
measured.
5.5.1. Test Setup
Before the optical test is performed, the electrical performance of the differential
driver has been measured since the laser has not been fully functional for the laser driver.
Figure 5.11 shows the test setup block diagram for the driver test. The test setup
consists of Tektronix 1400 Bit Error Rate Tester (BERT) which generates different
modes of pseudorandom digital pulse stream and measures the probability of an
transmitted data error rate through the device under test, Keithley 236 Source
Measurement Unit (SMU) to supply a precise modulation current, and Tektronix 11403A
oscilloscope to monitor the output of the driver and measure the eye diagram and pulse
waveform. An eye diagram and a pulse waveform of the driver were measured using 27-1
pseudorandom bit stream (PRBS).
77
Figure 5.11. The block diagram of the test structure
Clock for Transient output curve and BER synchronization
Microwave Logic
giga BERT-1400 TXLaser Driver
Microwave Logic
giga BERT-1400 RX
Tektronix 11403AOscilloscope
78
Figure 5.12. Microphotograph of the chip
The microphotograph of the chip before wire bonding is shown in the figure
above. The white area in the upper, rightmost, and leftmost sides is a metal on-chip
decoupling capacitor to help stabilizing unwanted bias ripple through the biases.
Decoupling capacitor The driver circuit
79
Figure 5.13. Test board with a bonded chip
Figure 5.13 shows the test board. To overcome the speed limitation of commercial
package, Chip-on-Board (COB) technology was employed. The board was previously
tested and experimentally showed no apparent distortion up to 1.5 Gbps. In this board,
the decoupling capacitor should be placed as close as possible to the chip. Otherwise, it
causes large parasitic inductance induced by the metal line between the chip and the place
where the decoupling capacitor was located.
80
5.5.2. BER and Eye Diagram Measurement
Before the optical test is performed, the electrical performance of the differential
driver has been measured since the laser that has been developing in Georgia Tech has
not been fully functional for the laser driver (see Appendix IV). The laser has been shown
huge threshold current, which cannot be supplied by the laser driver and only 1% of
yield. Therefore, a 50 Ω resistor that is the typical value of the commercial laser was
placed between drain port of the driver and Vdd instead of the thin-film laser to measure
the performance of the driver. As seen in Table 2.1, the functionality of the drivers were
verified with electrical test in many laser drivers since it is hard to get the high-speed
light source such as a laser.
The Figure form 5-14 to 5-19 show the measurement results at different speeds
that are 622 Mbps, 900 Mbps, and 1 Gbps. In each figures of pulse waveform, the top
trace is the trigger pulse and the bottom one represents the measured output signal of the
driver. For eye diagram, the top waveform is the clock signal and the bottom one is the
measured eye diagram at output of the driver. The figures 5-14, 16, 18 are pulse
waveform (bottom trace) of output from the driver and the Figures 5-15, 17, 19 show the
eye diagram at each speed operation. As shown in the first two figures, the driver could
work well enough to provide 10-11 BER with clearly opened eye diagram. However, as
speed goes higher, the eye starts closing as shown in the next figures and shows some
errors. Even though some researchers have reported the relationship between shape and
81
size of eye and BER, it is illustrated from the experimental results that the BER was
dependent on the opening size of clear area rather than the shape of eye diagram.
To get a certain BER, 10 times more bits were sent to make sure the functionality
of circuit operation, for example to have 1×10-11 BER performance, at least 1012 bits were
sent to the driver input. In this test, BER was measured up to 10-11 from 622 Mbps to 1
Gbps. 10-11 is a minimum BER that could be achieved due to the easiness and time
limitation of test. 10-11 BER from 622 Mbps to 800 Mbps, 0.2×10-11 at 900 Mbps, and 5.9
×10-11 at 1 Gbps was achieved respectively.
82
Figure 5.14. 622 Mbps pulse waveform
Figure 5.15. 622 Mbps eye diagram
83
Figure 5.16. 900 Mbps pulse waveform
Figure 5.17. 900 Mbps eye diagram
84
Figure 5.18. 1 Gbps pulse diagram
Figure 5.19. 1Gbps eye diagram
85
CHAPTER VI
A DIFFERENTIAL LASER DRIVER FOR LVDS
STANDARD
6.1 Introduction and Applications
For the demand for high-speed data rate and low power consumption in
computing, Low-Voltage Differential Signals (LVDS) IEEE standard (see appendix III)
was developed. This standard described a physical layer specification for drivers and
receivers in low-cost workstation and personal computer application. LVDS standard
employed low-voltage swing at maximum 400 mV to minimize power dissipation and to
enable high-speed operation. Also differential signals are used to reduce noise and
electromagnetic emissions.
In chapter 3 and 4, the differential laser driver has been introduced. The main
objective was to show the possibility that the digital differential driver was feasible for
high-speed operation. However, it is not suitable for LVDS standard since it needs high
input voltage to sustain high-speed operation. Therefore, the laser driver compatible with
86
LVDS standard was designed in this chapter. The driver has been laid out in magic layout
tool and fabricated using TSMC 0.25 µm technology.
The design specification of the driver was determined as in the table below.
Table 6-1. Design specification of the differential laser driver for LVDS
Specification Predetermined Goal of Design
Speed Up to 1Gbps
Input magnitude 100 – 400 mV
Power supply 2.5 V
Output current DC range: 0 – 30 mA
AC range: 0 – 40 mA
Current density Less than 30uA/1um square meter
87
6.2 Differential Transmitter Design for LVDS Standard
The silicon CMOS LVDS compatible differential laser driver circuit described
herein was designed to meet the predetermined specification. This driver design consists
of pre-driving stage and a laser driving stage. The laser driving stage structure is the same
as the one in chapter 3 but the size of the transistor was optimized for 40 mA modulation
current of the laser. This stage cannot be operated at 1 Gbps speed with the input
magnitude less than 400 mV due to the large input transistor size for high output current.
Therefore, the pre-driving stage was added with two-stage tapered differential amplifiers
to supply the enough input voltage to the laser driving stage.
For the maximum speed and gain, additional current source was included in the
pre-driver design. In developing pre-driver circuitry, the common differential amplifier
was considered initially. However, the speed is limited even with the maximum current
bias it can handle. Thus, the differential amplifier was newly developed containing
additional current providing component. Figure 6.1 illustrates a differential amplifier,
which is used as a pre-driver before the laser driving stage. The gain of the common
differential amplifier is determined given [97] by
Dmoxn
Dmoxn
m
mv
ILWCILWC
ggA
3
1
3
1
)/(2)/(2
µµ
== (6-1)
88
where gm1 and gm3 are the transconductances of transistors, M1 and M3,
respectively, µn is the electron mobility, Cox is the oxide capacitance, and W/L is the
aspect ratio of the MOS transistor. The idea of additional current is that the voltage gain
of the common differential amplifier is determined by two transistors but to have an
enough gain, input transistor, M1, should be large or output load transistor, M3, should be
small. However, there are two main restrictions here, if the input transistor is increased,
the parasitic capacitance will be also increased accordingly and this lowers bandwidth. In
addition, if the output load transistor size is attempted to diminish, the transistor size is
limited by the current bias since there is a limitation that one transistor can afford. So, to
have enough gain while keeping input transistor sizes same, additional circuitry was
needed to provide additional current to the input gm transistor.
As seen in the equation (6-1), the gain is gm1/gm3 and gm is root-square
proportional to device size (aspect ratio) and ID current. So, if 3 times bigger current is
flowing into input gm transistor than into the load transistor, this makes the gain to be
about 3 without requiring 3 times bigger input transistor size. In this research, the
additional current source, I2, is adjustable from the external source to control the gain of
each amplifier for maximum speed operation of the whole system.
In the design of the driver for LVDS standard, fully differential topology has been
used in the overall system to minimize delta-I noise, too.
89
Figure 6.1. The differential amplifier for the pre-driver stage
The overall driver schematic is shown in Figure 6.2. Two buffers in pre-driver
stage is tapered to the left to drive the last stage since the input transistor of the last stage
is big which means that there is a speed bottleneck due to the large parasitic capacitance
of the transistor. Therefore, the size of two buffers is scaled with the factor of 3 for
maximum bandwidth.
V1
VDD
VSS
M9M7 M3 M4 M8
M1 M2
M5M6
V2
I1
I2 Out-Out+
90
Figure 6.2. The overall schematic of the driver for LVDS
V1
M1
8
M1
6M
12M
13
M1
7
M1
0M1
1
M1
4M
15
I3
I4
M9
M7
M3
M4
M8
M1
M2
M5
M6
V2
I1
I2
VD
D
D2
M1
9M2
0
M2
4
M2
3
M2
5M
21
M2
2
I5I6
VS
S
Z1
91
6.2 Simulation and Layout
The HSPICE simulation on the overall driver has been performed using 0.25 µm,
BSIM level 4 model parameters (see Appendix III) provided by MOSIS service.
Figure 6.3 illustrates the transient response of the overall driver shown in Figure
6.2 for the bandwidth of 1 Gbps. The top trace represents the pulse waveform of input to
the pre-driver circuitry and the middle trace shows the pulse train of output from the laser
driving stage. This trace was shown to prove that there was not any missing bit, which
cannot be revealed in simple eye diagram. Also, the shape of the output pulse indicates
that the driver is fast enough to track the input pulse pattern. The bottom one is the
equivalent eye diagram of output to show how well the driver complies with the
incoming bit stream. In the simulation, the pattern of the input signal was 27-1 PRBS with
LVDS signal size and power supply voltage between Vdd and Vss was 2.5 V. And the
voltage gain of 2 was used in pre-driver stage.
As shown in the simulation result, the output works well enough for LVDS
standard at 1 Gbps speed operation.
92
Figure 6.3. Transient response of LVDS compatible differential laser driver at 1 Gbps
The driver was laid out carefully for fabrication using magic layout tool as shown
in Figure 6.4. During the layout, every effort was made to minimize the parasitic
capacitance of the transistors.
In the final layout of this chip, the decoupling capacitor using metal1, metal2,
metal3, and metal4 was embedded to prevent unwanted power supply ripple as the signal
goes through the driver circuitry.
93
Figure 6.4. The layout of the overall driver for LVDS
The Figure 5.10 shows the final layout of the chip submitted to MOSIS for
fabrication performed in magic tool. The lower side is driver part and the left side is on-
chip decoupling capacitor between Vdd and Vss. Two pads at upper part of the driver are
prepared for thin-film laser integration. In the large space between two pads, the laser
will be integrated. The right upper part is receiver part and the circuitry located in the left
side of on-chip decoupling capacitor is DAC for the autobias of receiver and transmitter
respectively.
94
Figure 6.5. The final layout of the whole chip submitted to farbrication
Receiver
Transmitter
DAC Decoupling Capacitor
95
Figure 6.6. Microphotograph of the chip for LVDS compatible driver
Figure 6.6 shows the microphotograph of the chip before wire bonding. The test
procedure, method, and setup are almost the same as for the laser driver in chapter 3 and
4. However, the experimental results not available at the time of this writing because of
the wire bonding problem using COB technology.
96
CHAPTER VII
CONCLUSIONS
AND
PROPOSED FUTURE RESEARCH
In this chapter, conclusions regarding the accomplished work and contribution of
this research in development of optical transmitter using standard digital CMOS process
are discussed. Finally, future research in this area is directed.
6.1 Contribution
The optical transmitters were developed for free-space optical communication
using available standard digital CMOS technology such as 0.35µm and 0.25µm. These
transmitters worked up to 1 Gbps speed with 10-11 BER performance. They were first
digital CMOS transmitters to date running at these speeds with high modulation current
97
greater than 100 mA. Table 7.1 shows the performance comparison between this
transmitter and the recently published optical transmitters that are listed in Table 2.1.
This comparison is limited to optical transmitters made only by CMOS technology.
Table 7.1. The performance comparison of the transmitter
in this research with recently published transmitters
Ref. Process Channel Length
[µm]
Speed [Gbit/s]
Max. Output Current
[mA]
Eye Diagram BER Remark
This Work CMOS 0.35 1 180 Yes Yes
-Measure in packaging
-Electrical test
This Work CMOS 0.25 1 40 No No
-Only simulation
results
[9] CMOS 0.5 µm 2.5 1.6 Yes Yes -On-wafer measure
-Optical test
[10] CMOS 1.2 µm 1 1.2 Yes Yes -Optical test
[11] CMOS 1.0 µm 0.622 40 Yes No -On-wafer measure
-Optical test
[33] CMOS 0.8 µm 2.5 40 No No
-On-wafer measure
-Electrical test
[34] CMOS 0.35 µm 1 NA No No -Only
simulation results
98
In this research, the usefulness of differential topology of optical transmitter and
decoupling capacitor to eliminate current ripples that produce the delta-I noise has been
proved. The model of the packaging was implemented including bonding wires and bias
wires and the model was included in the design procedure to predict actual performance
of the driver. Also, the real model of decoupling capacitor was used to know the real
effectiveness. Finally, the performance was measured in terms of BER and eye diagrams
even though most of recent researches provided only scope captured data or eye-diagram
without BER data.
Besides the development of the transmitter for high dI/dt, the transmitter
compatible with LVDS standard was also developed with new differential amplifier
which provides high gain and high speed.
Thus, two design topologies with characterized data can lead to a one-chip optical
transmitter solution supporting high speed and high output power.
99
6.3 Future Research
This research covered three schemes of optical transmitter circuit, which is the
single-ended LED driver, the differential laser driver, and the differential LVDS
compatible laser driver up to 10 Gbps speed operation. However, for the high-speed,
external modulator has been widely used in the optical communication. Thus, for future
research, modulator driver implementation is necessary. To drive the modulator, the
transmitter circuit should provide voltage output to the modulator instead of providing
current output to the laser. Also, other technologies such as InP HBT and SiGe BiCMOS
might be applied to the design of optical transmitter since the speed greater than 10 Gbps
is challenging in the current CMOS technology. In addition, more accurate model of
packaging parasitics is required for future research since the effect of unwanted parasitics
is more critical as the speed is increased.
As mentioned in chapter 2, the characteristics of the laser is changed depending
on the temperature and device aging. In this research, since the biases for threshold
current and modulation current for the laser are adjusted manually using external current
source to compensate the degradation of the laser due to the temperature and aging, an
automatic bias control circuit is necessary for the future research.
In addition to optical transmitter, other function blocks are necessary such as
multiplexer to serialize the low-speed parallel incoming data stream to high-speed serial
100
signals or pre-distorter circuits to compensate the chromatic dispersion of the optical
fiber. Also, the optical receiver circuitry, which can be compatible with the transmitters
in this research, is needed to implement a transceiver system. It is the most probable tht
both circuits will coexist on a single digital CMOS chip.
101
6.3 Conclusions
A through-silicon optical communication system including single-ended
transmitter was demonstrated as an example of free-space optical communication and it
showed the restriction for high-speed operation. Thus, A differential optical transmitter
meeting high-speed requirement were designed and tested. The transmitter was fabricated
using standard digital CMOS technology through National Semiconductor under
minimum feature size gate length, 0.35 µm. The performance of this transmitter has been
verified along with BER measurement result and eye diagrams at the data rate of 1 Gbps
non-returen-to-zero pseudorandom bit stream. This transmitter was scalable since any
passive components were not used in the design. So, as the minimum geometry size of a
transistor shrinks, the transmitter performance improvement is expected in accordance
with reduced feature size of transistors as shown in chapter 4.5.
For the transmitter design, the significance of the effect of unwanted packaging
parasitics was discussed in chapter 5. The accurate model of packaging parasitics was
developed and incorporated in the simulation to predict the actual behavior in the real test
environment. The simulation results showed the output corruption in the presence of the
parasitics. To reduce the effect of parastics, differential topology was employed and
decoupling capacitor was suggested. The effectiveness of these methods was verified in
the simulation results and the measurement result.
102
In chapter 6, a differential transmitter with a pre-driver for LVDS, one of
common logic family, has been designed and fabricated with a 0.25 µm standard digital
CMOS technology through MOSIS foundry to support 1 Gbps data rate. The transmitter
consists of two differential amplifiers with additional current source for high-speed and
high gain at the pre-driver stage and laser driver at later stage. This transmitter has not
been tested at the time of writing.
179
APPENDIX A
Brief LVDS Specifications
Appendix A.1 Driver dc specification for general purpose link
Symbol Parameter Min Max Units
Voh Output voltage high 1475 mV
Vol Output voltage low 925 mV
|Vod| Output differential voltage 250 400 mV
Vos Output offset voltage 1125 1275 mV
180
Appendix A.2 Driver dc specification for reduced range link
Symbol Parameter Min Max Units
Voh Output voltage high 1375 mV
Vol Output voltage low 1025 mV
|Vod| Output differential voltage 150 250 mV
Vos Output offset voltage 1150 1250 mV
105
APPENDIX B
EDEGE EMITTING LASER FABRICATED IN GT
In this research, two kinds of lasers are implemented. One is a double
heterojuction (DH) and another a multiple quantum well (MQW) of InP/InGaAsP for 1.3
um wavelength [98]. With the DB laser, stimulated emission is obtained with relatively
small threshold currents since the optical confinement of the DH structure reduces the
cavity loss. Typically, the DB laser has a thickness of 0.1 to 0.3 um in the active layer.
There are several ways to produce lasers using double heterojunction structures such as
the broad area laser, the gain guided laser, the weak index guided laser, and the buried
heterostructure laser. Since the DH laser was fabricated to test the quality of the material
and to gauge the light efficiency of the material, the broad area laser (the simplest design)
was used. The broad area laser has contacts on the p and n side and then cleaves. These
kinds of lasers lead to high threshold currents and nonlinearities in its light versus current
characteristics since they do not have transverse mode confinement or current
confinement. The layer structure of the InP substrate-based DH laser that has been grown
at Georgia Tech is shown in Table B.1.
106
Table B.1. Layer structure of the DH laser
Layer Thickness in µm
In0.53Ga0.47As-p+-2×1019 0.1
p-InP-5×1017 1.7
InGaAsP-Cladding layer 0.1
InGaAsP-Undoped 0.1
InGaAsP-Cladding layer 0.1
n-InP-5×1017 1.6
In0.53Ga0.47As-n+-5×1018 0.2
InGaAs-n=1017 0.2
n-InP-1×1018 4
n-InP substrate
With this structure, the DH laser was fabricated on a wafer and cleaved as shown
in Figure B.1 and Figure B.2 respectively. The output versus current characteristics of the
fabricated laser was measured and shown in Figure B.4. In Figure B.3, threshold current
is in the range of 120 mA, and 1 mW optical power at 140 mA input current.
107
Figure B.1. The Fabricated DH Laser Figure B.2. The Cleaved DH Laser
Figure B.3. Measured light-current characteristics of the DH laser
0
0.5
1
1.5
2
2.5
3
0 100 200input current(mA)
outp
ut p
ower
(mW
)
108
For the hybrid thin film process, the MQW structure is employed. The MQW
laser has active regions of ~100 nm thick. The MQW laser band structure is shown in
Figure B.4.
Figure B.4. MQW band structure
It typically consists of a quantum well region, an inner cladding, and an outer
cladding, although one additional stop etch layer should be added to the process for the
fabrication of a thin-film laser. The light is emitted from the active regions, which are in
the quantum well region. Outer and Inner cladding confine a high density of injected
carriers and photons to produce stimulated emission at a low input power. A thin-film
laser that has the MQW structure has been fabricated at Georgia Tech and will be
Outer cladding Inner cladding
Quantum wells region
Z direction
Energy
109
integrated onto the driver circuits and tested. The layer structure of the MQW laser is
shown in Table B.2.
Table B.2. Layer structure of the MQW laser
Layers Thickness in µm
p+-In0.53Ga0.47As-2×1019 0.1
p-InP-1×1019 (Be) 1
In0.84Ga0.16As0.33P0.67 0.2
InAs0.33P0.67 0.004
In0.84Ga0.16As0.33P0.67 0.02
InAs0.33P0.67 0.0041
In0.84Ga0.16As0.33P0.67 0.02
InAs0.33P0.67 0.0041
In0.84Ga0.16As0.33P0.67 0.2
n-InP-1×1019 (Si) 1
InP 0.1
InGaAs-1×1017 0.5
n-InP substrate
110
The output versus current characteristics of the fabricated laser was measured and
shown in Figure B.5. In Figure B.5, threshold current is in the range of 210 mA.
Figure B.5. Measured light-current characteristics of the MQW laser
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 50 100 150 200 250 300
Input current(mA)
Out
put p
ower
(mW
)
111
APPENDIX C
HSPICE INPUT CONTROL FILES AND BSIM MODEL
PARAMETERS USED IN SIMULATION
Appendix C.1. BSIM Model Parameter Used in chapter 4 and 5
********************************************************************************
SPICE BSIM3 PARAMETERS
NSC 0.35 µm process
Temperature parameters=Default
********************************************************************************
. .MODEL NMOS NMOS ( LEVEL = 49
+Tox=7.00000E-09 Xj=1.0000000E-07 Nch=3.3644000E+17
+lln=0.00 lwn=1.0000000 wln=1.0000000 wwn=1.2350000
+lint=2.5000000E-08 ll=7.4641730E-11 wint=1.15E-07
+ww=-1.3117622E-15 Mobmod=1 binunit=2 Dwg=3.9968030E-15
+Dwb=3.9968030E-15 Vth0=0.5752980 K1=0.7150000 K2=-2.6116744E-02
+K3=17.5394080 Dvt0=3.4999880 Dvt1=0.3978510 Dvt2=-5.0000000E-02
+Dvt0w=-4.3896440E-02 Dvt1w=8.5083410E+04 Dvt2w=0.00 Nlx=1.2410904E-07
+W0=1.7371252E-06 K3b=-7.2379680 Vsat=9.3500000E+04 Ua=-1.3432969E-09
+Ub=2.7800000E-18 Uc=8.9720000E-11 Rdsw=4.8045270E+02 Prwb=6.0000000E-03
+Prwg=-9.9999980E-02 Wr=0.6949863 U0=3.2631520E-02 A0=1.0001768
+Keta=-8.0000000E-03 A1=0.00 A2=0.9900000 Ags=0.2412180
112
+B0=6.0000000E-08 B1=0.00 Voff=-0.1130000 NFactor=1.2126000
+Cit=0.00 Cdsc=1.0000000E-10 Cdscb=2.8000001E-04 Cdscd=0.00
+Eta0=8.9606450E-02 Etab=-6.5917600E-02 Dsub=0.4135655
+Pclm=1.4301770 Pdiblc1=1.1277000E-03 Pdiblc2=2.4813999E-04
+Pdiblcb=8.9971000E-02 Drout=7.7836970E-03 Pscbe1=5.6448000E+08
+Pscbe2=1.3766100E-05 Pvag=1.0752020 Delta=1.0000000E-02
+Alpha0=4.8038320E-05 Beta0=31.5666010 kt1=-0.3100000
+kt2=-4.7000000E-02 At=5.1700000E+04 Ute=-1.1500000 Ua1=3.5300000E-09
+Ub1=-4.5000000E-18 Uc1=-5.5100000E-11 Kt1l=-1.0E-08 Prt=0.00
+Cj=.000672 Mj=.407 Pb=.825 Cjsw=2.19E-10 Mjsw=.264 Php=.629
+Cta=0 Ctp=0 Pta=0 Ptp=0 JS=1.00E-4 Dlc=3.5E-8 Cgdo=1.42E-10
+Cgso=1.42E-10 Cgbo=4.3e-11 Capmod=2 NQSMOD=0 Elm=5 Xpart=1
+Cgsl=0 Cgdl=0 Ckappa=0.6 Cf=0 Clc=1E-7 Cle=0.6
+NoiMod=2 NoiA=1.508309e18 NoiB=5.030324e5 NoiC=9.014809e-12
+EM=4.1e7 EF=0.7691789 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+Tox=7.00000E-09 Xj=1.5000001E-07 Nch=2.3615000E+17
+lln=1.1819875 lwn=0.9500000 wln=1.0000000 wwn=-0.4865745
+lint=-2.5000000E-08 ll=3.9180390E-16 lwl=-2.4801771E-23
+wint=2.4000000E-08 ww=1.2377800E-06 Mobmod=1 binunit=2
+Dwg=5.0000000E-10 Dwb=-6.6959450E-10 Vth0=-0.7600000
+K1=0.6170700 K2=-4.0250000E-02 K3=1.2248999 Dvt0=4.2579680
+Dvt1=0.4418320 Dvt2=-4.2500000E-02 Dvt0w=9.7680010
+Dvt1w=1.8321000E+06 Dvt2w=0.00 Nlx=1.7350369E-07
+W0=1.0150001E-06 K3b=-7.0928000 Vsat=1.2902500E+05
+Ua=1.1400000E-10 Ub=1.2628350E-18 Uc=-1.3575000E-11
++Rdsw=1.3341750E+03 wRdsw=-1.4000001E-03 pRdsw=4.2000000E-10
+Prwb=-1.0000000E-03 Prwg=0.00 Wr=1.0146334 U0=1.3271000E-02
+A0=0.6440000 Keta=-1.0000001E-02 A1=0.00 A2=0.4000000
+Ags=0.1773206 B0=2.1450019E-08 B1=1.0000000E-07
+Voff=-0.2212500 NFactor=5.2430400 Cit=-4.5400000E-03
+Cdsc=1.0000000E-03 Cdscb=4.2000000E-04 Cdscd=5.6000010E-04
+Eta0=2.7270000E-02 Etab=-6.3000000E-04 Dsub=0.2200600
+Pclm=3.6630000 Pdiblc1=2.0463699E-03 Pdiblc2=9.9620830E-04
+Pdiblcb=4.9049970E-02 Drout=0.5376000 Pscbe1=5.3452250E+08
113
+Pscbe2=1.0000000E-20 Pvag=0.00 Delta=1.0000000E-02
+Alpha0=1.5000000E-09 Beta0=20.0000000 kt1=-0.5162000
+kt2=-5.9000000E-02 At=2.4700000E+04 Ute=-1.1000000
+Ua1=8.5900000E-10 Ub1=-1.4100000E-18 Uc1=-5.8600000E-11
+Kt1l=0.00 Prt=0.00 Cj=.000794 Mj=.495 Pb=1 Cjsw=3.1E-10
+Mjsw=.327 Php=.726 Cta=0 Ctp=0 Pta=0 Ptp=0 JS=1.00E-04
+Dlc=1E-8 Cgdo=1.54E-10 Cgso=1.54E-10 Cgbo=4.7E-11 Capmod=2
+NQSMOD=0 Elm=5 Xpart=1 Cgsl=0 Cgdl=0 Ckappa=0.6 Cf=0 Clc=1E-7
+Cle=0.6 NoiMod=2 NoiA=1.35993e16 NoiB=6.503177e5
+NoiC=1.605921e-11
+EM=4.1e7 EF=0.8827707 )
* ********************************************************************************
114
Appendix C.2. BSIM Model Parameter Used in chapter 6
********************************************************************************
SPICE BSIM3 PARAMETERS
TSMC 0.25 µm process
Temperature parameters=Default
********************************************************************************
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.408619
+K1 = 0.4144712 K2 = 0.0122732 K3 = 1.000752E-3
+K3B = 0.8229319 W0 = 1.000961E-7 NLX = 2.808104E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.211976 DVT1 = 0.0981279 DVT2 = -0.0733355
+U0 = 345.4738707 UA = -6.65353E-10 UB = 2.037713E-18
+UC = 3.117558E-11 VSAT = 8.99117E4 A0 = 0.631435
+AGS = 0.1288136 B0 = 3.658209E-7 B1 = 1.05362E-6
+KETA = 6.322964E-3 A1 = 9.606552E-4 A2 = 1
+RDSW = 120 PRWG = 0.5 PRWB = -0.2
+WR = 1 WINT = 1.765394E-9 LINT = -2.126447E-8
+XL = 3E-8 XW = 0 DWG = -2.42828E-9
+DWB = 9.185176E-9 VOFF = -0.0976674 NFACTOR = 0
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0491777 ETAB = 3.125491E-3
+DSUB = 0.2870242 PCLM = 1.8534523 PDIBLC1 = 0.6857768
+PDIBLC2 = 0.01 PDIBLCB = 0.050458 DROUT = 1
+PSCBE1 = 8E10 PSCBE2 = 2.278455E-8 PVAG = 0.2666656
+DELTA = 0.01 RSH = 4.7 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = -1.22182E-16
+WWN = 1.2127 WWL = 0 LL = 0
115
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.4
+CGDO = 6.27E-10 CGSO = 6.27E-10 CGBO = 1E-12
+CJ = 1.916804E-3 PB = 0.99 MJ = 0.4744225
+CJSW = 4.549787E-10 PBSW = 0.99 MJSW = 0.3235275
+CF = 0 PVTH0 = -8.631195E-3 PRDSW = 0
+PK2 = 3.5315E-3 WKETA = -4.378878E-3 LKETA = -0.0351436 )
*
.MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.556523
+K1 = 0.5416631 K2 = 0.0245545 K3 = 0
+K3B = 8.6601778 W0 = 6.279195E-6 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 4.3499141 DVT1 = 0.7927238 DVT2 = -0.072391
+U0 = 134.7042677 UA = 1.795355E-9 UB = 1E-21
+UC = -1E-10 VSAT = 2E5 A0 = 1.0980036
+AGS = 0.1869313 B0 = 1.602029E-6 B1 = 5E-6
+KETA = 0.0127477 A1 = 1.818942E-3 A2 = 0.576764
+RDSW = 1.418086E3 PRWG = 0.0500478 PRWB = -0.2753995
+WR = 1 WINT = -1.899142E-8 LINT = 2.725798E-8
+XL = 3E-8 XW = 0 DWG = -7.677822E-9
+DWB = 3.679257E-9 VOFF = -0.0925825 NFACTOR = 0
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.2 ETAB = -0.0740874
+DSUB = 1.1514586 PCLM = 1.8859363 PDIBLC1 = 0
+PDIBLC2 = 0.0969061 PDIBLCB = -1E-3 DROUT = 0.3487536
+PSCBE1 = 2.171928E10 PSCBE2 = 6.262781E-9 PVAG = 15
+DELTA = 0.01 RSH = 3.5 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.4
+CGDO = 5.59E-10 CGSO = 5.59E-10 CGBO = 1E-12
116
+CJ = 1.883133E-3 PB = 0.9807855 MJ = 0.4655692
+CJSW = 3.733241E-10 PBSW = 0.7634647 MJSW = 0.3208898
+CF = 0 PVTH0 = 6.146287E-3 PRDSW = -9.6506777
+PK2 = 3.091063E-3 WKETA = 6.365227E-3 LKETA = -0.0103601 )
*
117
Appendix C.3. SPICE Netlist and Input Control File
Appendix C.3.1. NSC Differential Transmitter Netlist
***** Subcircuit from file ./acsource1.ext
.SUBCKT acsource1 1 2 3 4 5
M1 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M2 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M3 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M4 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M5 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M6 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M7 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M8 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M9 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M10 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M11 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M12 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M13 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M14 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M15 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M16 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M17 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M18 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M19 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M20 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M21 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M22 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M23 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M24 3 5 4 2 NMOS W=80.0U L=0.4U
118
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M25 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M26 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M27 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M28 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M29 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M30 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M31 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M32 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M33 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M34 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M35 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M36 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M37 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M38 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M39 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M40 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M41 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M42 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M43 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M44 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M45 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M46 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M47 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M48 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M49 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M50 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M51 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M52 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M53 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M54 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M55 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M56 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M57 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M58 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M59 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M60 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M61 4 5 3 2 NMOS W=80.0U L=0.4U
119
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M62 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M63 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M64 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M65 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M66 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M67 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M68 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M69 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M70 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M71 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M72 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M73 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M74 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M75 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M76 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M77 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M78 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M79 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M80 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M81 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M82 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M83 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M84 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M85 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M86 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M87 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M88 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M89 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M90 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M91 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M92 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M93 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M94 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M95 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M96 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M97 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M98 3 5 4 2 NMOS W=80.0U L=0.4U
120
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M99 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M100 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M101 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M102 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M103 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M104 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M105 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M106 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M107 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M108 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M109 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M110 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M111 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M112 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M113 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M114 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M115 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M116 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M117 4 5 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=245.2U AS=0.0P PS=242.0U
M118 3 5 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=242.0U AS=0.0P PS=245.2U
M119 4 5 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.5U AS=0.0P PS=26.0U
M120 5 5 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=26.0U AS=0.0P PS=24.5U
M121 4 5 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.5U AS=0.0P PS=26.0U
M122 5 5 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=26.0U AS=0.0P PS=24.5U
M123 4 5 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.5U AS=0.0P PS=26.0U
M124 5 5 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=26.0U AS=0.0P PS=24.5U
M125 4 5 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.5U AS=0.0P PS=26.0U
M126 5 5 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=26.0U AS=0.0P PS=24.5U
M127 4 5 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.5U AS=0.0P PS=26.0U
M128 5 5 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=26.0U AS=0.0P PS=24.5U
C1 5 3 5.2F
C2 4 5 13.4F
C3 4 0 473.4F
C4 3 0 922.9F
C5 5 0 143.3F
*** Node Listing for subckt: acsource1
** 0 Node 0 is the global ground node
** 1 Vdd!
** 2 GND!
** 3 a_n1062_679#
** 4 a_n1080_669#
** 5 IdcLast
121
.ENDS
***** Subcircuit from file ./dcsource.ext
.SUBCKT dcsource 1 2 3 4 5 6
M1 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M2 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M3 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M4 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M5 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M6 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M7 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M8 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M9 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M10 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M11 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M12 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M13 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M14 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M15 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M16 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M17 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M18 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M19 5 3 3 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M20 3 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M21 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M22 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M23 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M24 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M25 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M26 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M27 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M28 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M29 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M30 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M31 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M32 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M33 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M34 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
122
M35 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M36 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M37 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M38 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M39 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M40 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M41 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M42 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M43 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M44 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M45 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M46 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M47 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M48 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M49 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M50 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M51 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M52 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M53 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M54 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M55 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M56 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M57 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M58 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M59 5 3 4 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M60 4 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M61 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M62 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M63 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M64 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M65 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M66 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M67 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M68 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M69 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M70 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M71 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
123
M72 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M73 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M74 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M75 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M76 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M77 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M78 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M79 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M80 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M81 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M82 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M83 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M84 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M85 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M86 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M87 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M88 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M89 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M90 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M91 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M92 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M93 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M94 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M95 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M96 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M97 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M98 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
M99 5 3 6 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=25.0U AS=0.0P PS=24.0U
M100 6 3 5 2 NMOS W=8.0U L=0.4U
+ AD=0.0P PD=24.0U AS=0.0P PS=25.0U
C1 3 4 4.0F
C2 3 6 4.0F
C3 5 3 10.1F
C4 5 0 100.7F
C5 3 0 118.9F
C6 6 0 36.0F
C7 4 0 36.0F
*** Node Listing for subckt: dcsource
** 0 Node 0 is the global ground node
** 1 Vdd!
** 2 GND!
** 3 Ilast_load
** 4 a_n23_167#
** 5 a_n41_71#
** 6 a_n23_87#
124
.ENDS
***** Subcircuit from file ./input.ext
.SUBCKT input 1 2 3 4 5 6 7 8 9 10 11 12 13 14
15 16 17 18 19 20 21
+ 22 23 24 25 26 27 28 29 30 31
M1 29 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=400.0U AS=0.0P PS=240.0U
M2 17 31 28 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M3 28 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M4 17 31 18 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M5 18 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M6 17 31 16 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M7 16 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M8 17 31 15 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M9 15 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M10 17 31 14 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M11 14 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M12 17 31 27 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M13 27 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M14 17 31 19 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M15 19 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P
PS=240.0U
M16 17 31 13 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M17 13 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M18 17 31 12 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M19 12 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M20 17 31 11 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M21 11 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M22 17 31 26 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M23 26 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M24 17 31 20 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M25 20 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M26 17 31 10 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M27 10 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M28 17 31 9 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M29 9 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M30 17 31 8 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M31 8 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M32 17 31 25 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M33 25 31 17 2 NMOS W=80.0U L=0.4U
125
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M34 17 31 21 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M35 21 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M36 17 31 7 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M37 7 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M38 17 31 6 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M39 6 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M40 17 31 5 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M41 5 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M42 17 31 24 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M43 24 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M44 17 31 22 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M45 22 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M46 17 31 4 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M47 4 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M48 17 31 3 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M49 3 31 17 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=240.0U
M50 17 31 23 2 NMOS W=80.0U L=0.4U
+ AD=0.0P PD=240.0U AS=0.0P PS=400.0U
C1 31 17 2.2F
C2 9 0 6.5F
C3 29 0 6.5F
C4 8 0 6.5F
C5 25 0 6.5F
C6 21 0 6.5F
C7 7 0 6.5F
C8 18 0 6.5F
C9 3 0 6.5F
C10 28 0 6.5F
C11 23 0 6.6F
C12 30 0 29.0F
C13 12 0 6.5F
C14 11 0 6.5F
C15 26 0 6.5F
C16 20 0 6.5F
C17 10 0 6.5F
C18 6 0 6.5F
C19 5 0 6.5F
C20 16 0 6.5F
C21 24 0 6.5F
C22 22 0 6.5F
C23 15 0 6.5F
C24 17 0 195.9F
C25 4 0 6.5F
C26 14 0 6.5F
C27 27 0 6.5F
C28 31 0 49.4F
C29 19 0 6.5F
C30 13 0 6.5F
*** Node Listing for subckt: input
** 0 Node 0 is the global ground node
** 1 Vdd!
** 2 GND!
** 3 a_418_404#
** 4 a_398_404#
** 5 a_338_404#
** 6 a_318_404#
126
** 7 a_298_404#
** 8 a_238_404#
** 9 a_218_404#
** 10 a_198_404#
** 11 a_138_404#
** 12 a_118_404#
** 13 a_98_404#
** 14 a_38_404#
** 15 a_18_404#
** 16 a_n2_404#
** 17 a_n52_404#
** 18 a_n22_404#
** 19 a_78_404#
** 20 a_178_404#
** 21 a_278_404#
** 22 a_378_404#
** 23 a_438_404#
** 24 a_358_404#
** 25 a_258_404#
** 26 a_158_404#
** 27 a_58_404#
** 28 a_n42_404#
** 29 a_n60_404#
** 30 a_n76_396#
** 31 a_n65_397#
.ENDS
****** top level cell is ./nsc_tx1.ext
xacsource1_0 1 2 3 4 5 acsource1
xdcsource_0 1 2 6 7 4 8 dcsource
xinput_1 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 8 3 3 3 3
3 3 3 3 3 3 3 3
+ 4 9 input
xinput_0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 7 3 3
3 3 3 3 3 3 3 3 3 3
+ 4 10 input
C1 8 3 5.1F
C2 8 3 5.2F
C3 8 3 5.2F
C4 8 3 5.2F
C5 8 3 5.2F
C6 3 8 5.2F
C7 8 3 5.2F
C8 8 3 5.2F
C9 8 3 5.2F
C10 8 3 5.2F
C11 8 3 5.2F
C12 9 8 1.3F
C13 7 0 398.5F
C14 8 0 388.6F
C15 10 0 6.2F
C16 9 0 4.0F
C17 4 0 807.9F
C18 6 0 1.1F
*** Node Listing for subckt: nsc_tx1
** 0 Node 0 is the global ground node
** 1 Vdd!
** 2 GND!
** 3 input_1/a_398_404#
** 3 input_0/a_298_404#
** 3 input_0/a_n2_404#
** 3 input_1/a_378_404#
** 3 input_0/a_278_404#
** 3 input_1/a_358_404#
** 3 input_0/a_18_404#
** 3 input_0/a_258_404#
** 3 input_1/a_338_404#
** 3 input_0/a_38_404#
127
** 3 input_0/a_238_404#
** 3 input_0/a_n60_404#
** 3 input_1/a_318_404#
** 3 input_0/a_58_404#
** 3 input_0/a_218_404#
** 3 input_1/a_198_404#
** 3 input_0/a_78_404#
** 3 input_1/a_178_404#
** 3 input_0/a_98_404#
** 3 input_1/a_158_404#
** 3 input_1/a_138_404#
** 3 input_1/a_118_404#
** 3 input_0/a_398_404#
** 3 input_0/a_378_404#
** 3 input_0/a_358_404#
** 3 input_1/a_n2_404#
** 3 input_1/a_438_404#
** 3 input_1/a_n42_404#
** 3 input_0/a_338_404#
** 3 input_1/a_418_404#
** 3 input_1/a_n22_404#
** 3 input_1/a_18_404#
** 3 input_0/a_318_404#
** 3 input_1/a_298_404#
** 3 input_1/a_38_404#
** 3 input_0/a_198_404#
** 3 input_1/a_278_404#
** 3 input_1/a_58_404#
** 3 input_0/a_178_404#
** 3 input_1/a_258_404#
** 3 input_1/a_78_404#
** 3 input_0/a_158_404#
** 3 input_1/a_238_404#
** 3 input_1/a_n60_404#
** 3 input_1/a_98_404#
** 3 input_0/a_138_404#
** 3 input_1/a_218_404#
** 3 input_0/a_118_404#
** 3 acsource1_0/a_n1062_679#
** 3 input_0/a_438_404#
** 3 input_0/a_n42_404#
** 3 input_0/a_418_404#
** 3 input_0/a_n22_404#
** 4 acsource1_0/a_n1080_669#
** 4 input_1/a_n76_396#
** 4 dcsource_0/a_n41_71#
** 4 Vss
** 4 m1_1022_43#
** 4 input_0/a_n76_396#
** 4 m1_429_n459#
** 5 acsource1_0/IdcLast
** 5 Iac
** 6 dcsource_0/Ilast_load
** 6 Idc
** 7 out1
** 7 dcsource_0/a_n23_167#
** 7 input_0/a_n52_404#
** 8 input_1/a_n52_404#
** 8 out2
** 8 dcsource_0/a_n23_87#
** 9 vin2
** 9 input_1/a_n65_397#
** 10 vin1
** 10 input_0/a_n65_397#
.END
128
Appendix C.3.2. NSC Differential Transmitter Input Control File
.options ACCURATE post list
.param v_1=2 v_2=1 v_0=1.5 bps=1n slope=0.001n
*power supply
*-------------
VVdd 100 0 dc 3v
Vvdd2 1 0 dc 3v
VGND 2 0 dc 0v
Vss 4 0 dc 0v
*input & output
*----------------
V_in1 200 0 pwl
+ (0ns,'v_1') ('2*bps-slope','v_1')
+ ('2*bps','v_2') ('9*bps','v_2')
+ ('9*bps+slope','v_1') ('10*bps','v_1')
+ ('10*bps+slope','v_2') ('11*bps','v_2')
+ ('11*bps+slope','v_1') ('18*bps','v_1')
+ ('18*bps+slope','v_2') ('19*bps','v_2')
+ ('19*bps+slope','v_1') ('20*bps','v_1')
+ ('20*bps+slope','v_2') ('22*bps','v_2')
+ ('22*bps+slope','v_1') ('23*bps','v_1')
+ ('23*bps+slope','v_2') ('24*bps','v_2')
+ ('24*bps+slope','v_1') ('26*bps','v_1')
+ ('26*bps+slope','v_2') ('28*bps','v_2')
+ ,R
v_in2 300 0 pwl
+ (0ns,'v_2') ('2*bps-slope','v_2')
+ ('2*bps','v_1') ('9*bps','v_1')
+ ('9*bps+slope','v_2') ('10*bps','v_2')
+ ('10*bps+slope','v_1') ('11*bps','v_1')
129
+ ('11*bps+slope','v_2') ('18*bps','v_2')
+ ('18*bps+slope','v_1') ('19*bps','v_1')
+ ('19*bps+slope','v_2') ('20*bps','v_2')
+ ('20*bps+slope','v_1') ('22*bps','v_1')
+ ('22*bps+slope','v_2') ('23*bps','v_2')
+ ('23*bps+slope','v_1') ('24*bps','v_1')
+ ('24*bps+slope','v_2') ('26*bps','v_2')
+ ('26*bps+slope','v_1') ('28*bps','v_1')
+ ,R
R_in1 200 10 25
R_in2 300 9 25
VDeye eye 0 pulse 0v 1v 0n '3*bps-slope/100000' 'slope/100000' 0n '3*bps'
Reye eye 0 1T
d1 emt1 1000 d1n3600
d2 emt1 2000 d1n3600
vout1 vled1 0 dc 3v
vd1 1000 7 dc 0v
vd2 2000 8 dc 0v
*bias currents & voltage
*-----------------------
idc 6 0 dc 2m
iac 100 5 dc 1.6m
*parasitic for Vdd
*-------------------------
Lwire1 intw1 vled1 105n
Rint1 intr1 intw1 0.01
xLboard1 ibrd1 intr1 pad
Lbond1 emt1 ibrd1 1n
*parasitic for Vss
*-------------------------------------
Lwire1vss intw1vss 5000 105n
130
Rint1vss intr1vss intw1vss 0.01
xLboard1vss ibrd1vss intr1vss pad
Lbond1vss 4 ibrd1vss 1n
.subckt pad 1 2
* L in nH, C in pF
L1 1 3 1.38664N
R1 3 4 0.0280365
C1 4 0 0.367874P
L2 4 5 1.38664N
R2 5 6 0.0280365
C2 6 0 0.367874P
L3 6 7 1.38664N
R3 7 8 0.0280365
C3 8 0 0.367874P
L4 8 9 1.38664N
R4 9 10 0.0280365
C4 10 0 0.367874P
L5 10 11 1.38664N
R5 11 2 0.0280365
C5 2 0 0.367874P
* end of sub-circuit
*decoupling capacitor
*10ncap
*Lcap emt1 nlc 1.12n
*Rcap nlc ncr 0.438
*Ccap ncr 4 10n
.include 'nsc035bsim3_typ.lib'
.include 'diode.lib'
.op
.tran 0.01ns 48ns
.include 'nsc_tx1.spice'
.END
131
Appendix C.3.3. LVDS Compatible differential Transmitter Netlist
***** Subcircuit from file
./yama_direct_flat.ext
.SUBCKT yama_direct_flat 1 2 3 4 5 6 7 8 9 10
M1 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M2 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M3 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M4 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M5 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M6 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M7 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M8 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M9 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M10 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M11 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M12 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M13 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M14 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M15 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M16 10 6 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M17 8 6 10 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M18 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M19 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M20 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M21 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M22 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M23 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M24 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M25 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M26 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M27 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M28 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M29 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
132
M30 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M31 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M32 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M33 8 7 9 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=185.7U
M34 9 7 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=185.7U AS=0.0P PS=184.1U
M35 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M36 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M37 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M38 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M39 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M40 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M41 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M42 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M43 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M44 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M45 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M46 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M47 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M48 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M49 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M50 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M51 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M52 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M53 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M54 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M55 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M56 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M57 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M58 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M59 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M60 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M61 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M62 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M63 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M64 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M65 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M66 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
133
M67 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M68 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M69 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M70 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M71 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M72 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M73 4 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.8U
M74 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M75 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M76 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M77 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M78 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M79 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M80 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M81 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M82 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M83 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M84 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M85 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M86 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M87 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M88 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M89 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M90 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M91 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M92 10 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M93 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M94 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M95 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M96 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M97 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M98 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M99 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M100 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M101 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M102 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M103 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
134
M104 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M105 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M106 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M107 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M108 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M109 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M110 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M111 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M112 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M113 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M114 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M115 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M116 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M117 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M118 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M119 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M120 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M121 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M122 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M123 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M124 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M125 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M126 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M127 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M128 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M129 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M130 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M131 9 4 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.6U AS=0.0P PS=18.8U
M132 3 4 4 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.0U
M133 3 4 10 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M134 3 4 9 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=18.6U
M135 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M136 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M137 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M138 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M139 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M140 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
135
M141 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M142 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M143 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M144 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M145 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M146 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M147 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M148 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M149 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M150 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M151 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M152 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M153 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M154 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M155 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M156 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M157 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M158 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M159 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P
PS=184.1U
M160 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M161 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M162 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M163 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M164 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M165 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M166 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M167 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M168 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M169 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M170 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M171 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M172 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M173 3 5 8 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=188.1U AS=0.0P PS=184.1U
M174 8 5 3 11 NMOS W=60.0U L=0.3U
+ AD=0.0P PD=184.1U AS=0.0P PS=188.1U
M175 3 5 5 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.8U AS=0.0P PS=19.5U
M176 5 5 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=19.5U AS=0.0P PS=18.8U
M177 3 5 5 11 NMOS W=6.0U L=0.3U
136
+ AD=0.0P PD=18.8U AS=0.0P PS=19.5U
M178 5 5 3 11 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=19.5U AS=0.0P PS=18.8U
C1 4 9 9.2F
C2 4 10 9.2F
C3 5 8 9.2F
C4 3 9 11.5F
C5 3 10 11.5F
C6 3 8 107.8F
C7 9 8 56.2F
C8 9 7 4.3F
C9 10 8 45.1F
C10 5 3 11.8F
C11 10 6 4.3F
C12 8 7 4.5F
C13 4 3 29.0F
C14 8 6 4.1F
C15 10 0 91.1F
C16 9 0 89.7F
C17 6 0 9.5F
C18 7 0 6.1F
C19 3 0 239.7F
C20 5 0 14.6F
C21 4 0 35.7F
C22 8 0 201.2F
*** Node Listing for subckt: yama_direct_flat
** 0 Node 0 is the global ground node
** 1 Vdd!
** 2 GND!
** 3 Vss
** 4 Idc
** 4 Ilast_load
** 5 IdcLast
** 5 Iac
** 6 vin1
** 7 vin2
** 8 vac
** 9 out2
** 10 out1
** 11 Gnd!
.ENDS
****** top level cell is ./yama_logic2.ext
xyama_direct_flat_0 1 2 3 4 5 6 7 8 9 10
yama_direct_flat
M1 11 11 12 1 PMOS W=6.0U L=0.3U
+ AD=0.0P PD=24.0U AS=2.5P PS=19.3U
M2 13 11 12 1 PMOS W=6.0U L=0.3U
+ AD=6.1P PD=24.0U AS=2.5P PS=19.3U
M3 14 11 12 1 PMOS W=6.0U L=0.3U
+ AD=6.2P PD=24.0U AS=2.5P PS=19.3U
M4 13 12 12 15 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=35.1U
M5 14 12 12 15 NMOS W=6.1U L=0.3U
+ AD=0.0P PD=18.5U AS=0.0P PS=35.9U
M6 16 16 12 1 PMOS W=4.0U L=0.3U
+ AD=0.0P PD=16.2U AS=1.7P PS=13.0U
M7 17 16 12 1 PMOS W=12.2U L=0.3U
+ AD=11.7P PD=48.6U AS=5.1P PS=39.0U
M8 18 16 12 1 PMOS W=12.2U L=0.3U
+ AD=11.7P PD=48.6U AS=5.1P PS=39.0U
M9 17 12 12 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.4U AS=0.0P PS=71.0U
M10 18 12 12 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.4U AS=0.0P PS=71.0U
M11 19 19 12 1 PMOS W=4.0U L=0.3U
+ AD=0.0P PD=16.2U AS=1.7P PS=13.0U
M12 7 19 12 1 PMOS W=12.2U L=0.3U
+ AD=10.4P PD=32.4U AS=5.1P PS=39.0U
M13 12 19 7 1 PMOS W=12.2U L=0.3U
+ AD=5.1P PD=39.0U AS=10.4P PS=32.4U
M14 6 19 12 1 PMOS W=12.2U L=0.3U
137
+ AD=10.4P PD=32.4U AS=5.1P PS=39.0U
M15 12 19 6 1 PMOS W=12.2U L=0.3U
+ AD=5.1P PD=39.0U AS=10.4P PS=32.4U
M16 7 19 12 1 PMOS W=12.2U L=0.3U
+ AD=10.4P PD=32.4U AS=5.1P PS=39.0U
M17 6 19 12 1 PMOS W=12.2U L=0.3U
+ AD=10.4P PD=32.4U AS=5.1P PS=39.0U
M18 7 12 12 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=71.0U
M19 6 12 12 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=71.0U
M20 12 12 7 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=71.0U AS=0.0P PS=43.7U
M21 7 12 12 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=71.0U
M22 12 12 6 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=71.0U AS=0.0P PS=43.7U
M23 6 12 12 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=71.0U
M24 20 21 13 15 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.4U AS=0.0P PS=18.0U
M25 13 21 20 15 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.4U
M26 20 21 13 15 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.4U AS=0.0P PS=18.0U
M27 20 22 14 15 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.4U AS=0.0P PS=18.0U
M28 14 22 20 15 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.0U AS=0.0P PS=18.4U
M29 23 14 17 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.6U AS=0.0P PS=36.4U
M30 17 14 23 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.4U AS=0.0P PS=36.6U
M31 20 22 14 15 NMOS W=6.0U L=0.3U
+ AD=0.0P PD=18.4U AS=0.0P PS=18.0U
M32 23 14 17 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.6U AS=0.0P PS=36.4U
M33 23 13 18 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.6U AS=0.0P PS=36.4U
M34 18 13 23 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.4U AS=0.0P PS=36.6U
M35 23 13 18 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=36.6U AS=0.0P PS=36.4U
M36 24 18 7 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M37 7 18 24 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=29.3U
M38 24 18 7 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M39 7 18 24 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=29.3U
M40 24 18 7 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M41 7 18 24 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=29.3U
M42 24 18 7 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M43 24 17 6 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M44 6 17 24 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=29.3U
M45 24 17 6 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M46 6 17 24 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=29.3U
M47 24 17 6 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M48 6 17 24 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=43.7U AS=0.0P PS=29.3U
M49 24 17 6 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=29.3U AS=0.0P PS=43.7U
M50 3 25 24 15 NMOS W=24.3U L=0.3U
+ AD=0.0P PD=80.2U AS=0.0P PS=58.6U
M51 24 25 3 15 NMOS W=24.3U L=0.3U
138
+ AD=0.0P PD=58.6U AS=0.0P PS=80.2U
M52 3 26 26 15 NMOS W=4.0U L=0.3U
+ AD=0.0P PD=13.4U AS=0.0P PS=19.2U
M53 3 26 20 15 NMOS W=12.2U L=0.3U
+ AD=0.0P PD=40.1U AS=0.0P PS=37.2U
M54 3 27 27 15 NMOS W=4.0U L=0.3U
+ AD=0.0P PD=13.4U AS=0.0P PS=17.4U
M55 3 27 23 15 NMOS W=24.3U L=0.3U
+ AD=0.0P PD=80.2U AS=0.0P PS=73.2U
M56 3 25 25 15 NMOS W=4.0U L=0.3U
+ AD=0.0P PD=13.4U AS=0.0P PS=17.4U
M57 3 25 24 15 NMOS W=24.3U L=0.3U
+ AD=0.0P PD=80.2U AS=0.0P PS=58.6U
C1 23 17 2.5F
C2 6 12 5.7F
C3 6 7 6.6F
C4 7 12 5.4F
C5 23 13 4.3F
C6 24 6 5.9F
C7 18 12 1.6F
C8 6 17 1.6F
C9 17 12 1.6F
C10 14 13 3.1F
C11 3 24 4.9F
C12 7 18 1.6F
C13 24 7 5.9F
C14 3 23 1.6F
C15 24 18 1.5F
C16 18 17 7.7F
C17 20 14 1.3F
C18 24 17 5.4F
C19 23 18 2.5F
C20 19 12 1.0F
C21 20 13 1.3F
C22 10 0 1.2F
C23 9 0 1.1F
C24 14 0 12.8F
C25 13 0 15.5F
C26 19 0 1.6F
C27 6 0 25.8F
C28 7 0 41.0F
C29 23 0 20.5F
C30 12 0 34.1F
C31 20 0 11.3F
C32 24 0 14.6F
C33 3 0 206.4F
C34 25 0 1.4F
C35 18 0 19.6F
C36 17 0 23.0F
*** Node Listing for subckt: yama_logic2
** 0 Node 0 is the global ground node
** 1 Vdd!
** 2 GND!
** 3 yama_direct_flat_0/Vss
** 3 Vss
** 4 yama_direct_flat_0/Ilast_load
** 4 Iload_last
** 5 Idc_last
** 5 yama_direct_flat_0/IdcLast
** 6 vdiff_out1
** 6 yama_direct_flat_0/vin1
** 7 vdiff_out2
** 7 yama_direct_flat_0/vin2
** 8 yama_direct_flat_0/vac
** 9 out2
** 9 yama_direct_flat_0/out2
** 10 out1
** 10 yama_direct_flat_0/out1
** 11 Iload3
** 12 Vdd
** 13 vdiff3_in2
** 14 vdiff3_in1
** 15 Gnd!
139
** 16 Iload2
** 17 vdiff2_in2
** 18 vdiff2_in1
** 19 Iload1
** 20 a_n952_299#
** 21 vin1
** 22 vin2
** 23 a_n569_299#
** 24 a_n68_234#
** 25 Idc1
** 26 Idc3
** 27 Idc2
.END
140
Appendix C.3.4. LVDS Compatible Differential Transmitter SPICE Input
Control File
nsc transmitter last stage test
.options ACCURATE post list
.param v_1=1.30 v_2=1.20 v_0=1.25 bps=5n slope=0.001n
*power supply
*-------------
VVdd 100 0 dc 2.5v
Vvdd2 1 0 dc 2.5v
Vdd3 12 0 dc 2.5v
VGND 2 0 dc 0v
Vss1 15 0 dc 0v
Vss 3 0 dc 0v
*input & output
*----------------
v_in1 21 0 pwl
+ (0ns,'v_1') ('2*bps-slope','v_1')
+ ('2*bps','v_2') ('9*bps','v_2')
+ ('9*bps+slope','v_1') ('10*bps','v_1')
+ ('10*bps+slope','v_2') ('11*bps','v_2')
+ ('11*bps+slope','v_1') ('18*bps','v_1')
+ ('18*bps+slope','v_2') ('19*bps','v_2')
+ ('19*bps+slope','v_1') ('20*bps','v_1')
+ ('20*bps+slope','v_2') ('22*bps','v_2')
+ ('22*bps+slope','v_1') ('23*bps','v_1')
+ ('23*bps+slope','v_2') ('24*bps','v_2')
+ ('24*bps+slope','v_1') ('26*bps','v_1')
+ ('26*bps+slope','v_2') ('28*bps','v_2')
+ ,R
141
v_in2 22 0 pwl
+ (0ns,'v_2') ('2*bps-slope','v_2')
+ ('2*bps','v_1') ('9*bps','v_1')
+ ('9*bps+slope','v_2') ('10*bps','v_2')
+ ('10*bps+slope','v_1') ('11*bps','v_1')
+ ('11*bps+slope','v_2') ('18*bps','v_2')
+ ('18*bps+slope','v_1') ('19*bps','v_1')
+ ('19*bps+slope','v_2') ('20*bps','v_2')
+ ('20*bps+slope','v_1') ('22*bps','v_1')
+ ('22*bps+slope','v_2') ('23*bps','v_2')
+ ('23*bps+slope','v_1') ('24*bps','v_1')
+ ('24*bps+slope','v_2') ('26*bps','v_2')
+ ('26*bps+slope','v_1') ('28*bps','v_1')
+ ,R
VDeye eye 0 pulse 0v 1v 0n '3*bps-slope/100000' 'slope/100000' 0n '3*bps'
Reye eye 0 1T
d1 vled1 10 d1n3600
d2 vled2 9 d1n3600
vled1 vled1 0 dc 2.5v
vled2 vled2 0 dc 2.5v
*bias currents & voltage
*-----------------------
idc1 100 25 dc 150u
iload1 19 0 dc 120u
idc2 100 27 dc 150u
iload2 16 0 dc 120u
idc3 100 26 dc 150u
iload3 11 0 dc 120u
iload_last 100 4 dc 1m
idc_last 100 5 dc 0.3m
142
.include 'tsmc024.lib'
.include 'diode.lib'
.options nopage opts interp list post=2 ingold=2 newtol
.tran 0.01ns 14ns
.include 'yama_logic2.spice'
.END
143
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