A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs
1
10 -2 10 0 10 1 10 2 Scaling factor N orm alized pow er = 0 (low speed) 10 -2 10 0 10 1 10 2 Scaling factor = 1 (high speed) 1b/s 2b/s 3b/s 4b/s 5b/s 0 0.01 0.02 0.03 0.04 -200 0 200 400 [ps] 0 0.01 0.02 0.03 0.04 0 0.5 1 Tim e [s] S am pling C lock Skew A D C C onversion Error A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs Pingli Huang and Yun Chiu Illinois Center fo Wireless Systems Introduction • Modern wireless communication systems demand low-power pipeline ADCs – Bluetooth, IEEE 802.11a/b/g, DVB-T, and etc. – SHA-less pipeline ADC can be used in IF sampling applications for DVB-T systems • Pipeline ADC architectural power efficiency – SHA-less multi-bit-per-stage architecture is the most power efficient – Severe performance degradation at high input frequencies due to sampling clock skew n 1 bits Stage1 n 1 bits Stage K V 2 n K bits S/H A/D D/A + ×2 n 1 V 1 V 2 SHA V 1 + SHA Noise Gain=1 V in Calibration Algorithm (I) • Sampling clock skew in SHA-less Architecture S/H A/D D/A Clock t t V in skew ΔV t+δt t+δt – Effectively creates dynamic offsets in the sub-ADC – Problem exacerbates with large input slew rates • Proposed approach – Calibrate sampling clock skew – Improve the viability of SHA-less multi-bit-per-stage architecture at high input frequencies S/H A/D D/A Clock t V in 3 bits V out 2 2 0 -V ref 0 V ref V ref 0 1 2 34 5 6 2 ref V 2 ref V 2.5-b/s TF Pipeline AD C 1 st stage V in V out t+δt t t+δt ΔV skew ΔV skew S/H A/D D/A Clock t V in 3 bits V out 2 2 0 -V ref 0 V ref V ref 0 1 2 34 5 6 2 ref V 2 ref V 2.5-b/s TF Pipeline AD C 1 st stage V in V out t+δt t t+δt ΔV skew ΔV skew S/H A/D D/A Clock t V in 3 bits V out 2 2 0 -V ref 0 V ref V ref 0 1 2 34 5 6 2 ref V 2 ref V 2.5-b/s TF Pipeline AD C 1 st stage V in V out t t Without sampling clock skew, residues are bounded between ±V ref /2 With sampling clock skew, some residues are pushed exceeding ±V ref /2 ADC Conversion errors occur when residues exceed ±V ref The larger the sampling clock skew, the more residues exceed ±V ref /2 Calibration Algorithm (II) S/H A/D D/A Clock D igital C alibration t V in Delay V out 3 bits t-Δt 1 t+Δt 2 t Delay 2 2 Two sub-ADC sampling timings are initially apart, with S/H sampling timing in between. t t-Δt 1_initial t+Δt 2_initial t t-Δt 1_initial t+Δt 2_initial The sub-ADC timing resulting in more out-of-bound residues is stepped towards the other In steady state, both sub- ADC timings converge to the S/H sampling timing. Calibration implementation About 1800 gates, 8-bit digital delay control, 2000-Sample/upda Simulation Setup Simulation Results Simulator SIMULINK Simulated architecture 2.5-b/s with calibration Sine-wave Input signal Full range 500 MHz Comparator offset (σ) 15 mV Comparator noise (σ) 5 mV Clock skew among comparators (σ) 5 ps LSB size of the digital delay line 4 ps No. of samples observed per update 1000 0 0.01 0.02 0.03 0.04 0.05 100 150 200 250 [ps] 0 0.01 0.02 0.03 0.04 0.05 100 150 200 250 Tim e [s] [ps] A tim e-varying S/H clock Sub-AD C clock Convergence of the algorithm Conversion error free in tracking t t-Δt 1_initial t+Δt 2_initial 1: error 0: correct MUX COMP ∑ Err C ontrol code 1 C ontrol C odes Update ADC 1 st Stage Delay C ircuit clk C ontrol C ode 1 ∑ Err C ontrol code 2 C ontrol C ode 2 Error R esidue out-of-range
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A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs Pingli Huang and Yun Chiu. Illinois Center for Wireless Systems. Calibration Algorithm (I). Introduction. Modern wireless communication systems demand low-power pipeline ADCs - PowerPoint PPT Presentation
Transcript of A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs
10-2
100
101
102
Scaling factor
Nor
mal
ized
pow
er
= 0 (low speed)
10-2
100
101
102
Scaling factor
= 1 (high speed)
1b/s
2b/s
3b/s
4b/s
5b/s
0 0.01 0.02 0.03 0.04-200
0
200
400
[ps]
0 0.01 0.02 0.03 0.040
0.5
1
Time [s]
Sampling Clock Skew
ADC Conversion Error
A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs
Pingli Huang and Yun Chiu
Illinois Center forWireless Systems
Introduction• Modern wireless communication systems demand low-power
pipeline ADCs– Bluetooth, IEEE 802.11a/b/g, DVB-T, and etc.– SHA-less pipeline ADC can be used in IF sampling applications for
DVB-T systems
• Pipeline ADC architectural power efficiency– SHA-less multi-bit-per-stage architecture is the most power efficient– Severe performance degradation at high input frequencies due to
sampling clock skew
n1 bits
Stage1
n1 bits
Stage KV2
nK bits
S/H
A/D D/A
+×2n1
V1 V2
SHAV1
+
SHANoise
Gain=1Vin
Calibration Algorithm (I)
• Sampling clock skew in SHA-less Architecture
S/H
A/D D/A
Clockt
t
Vin
skewΔV
t+δtt+δt
– Effectively creates dynamic offsets in the sub-ADC
– Problem exacerbates with large input slew rates
• Proposed approach– Calibrate sampling clock skew – Improve the viability of SHA-less multi-bit-per-stage architecture at high input
frequencies
S/H
A/D D/A
Clockt
Vin
3 bits
Vout22
0-Vref
0
Vref
Vref
0 1 2 3 4 5 62refV
2refV
2.5-b/s TFPipeline ADC 1st stage
Vin
Vout
t+δtt t+δt
ΔVskew
ΔVskew
S/H
A/D D/A
Clockt
Vin
3 bits
Vout22
0-Vref
0
Vref
Vref
0 1 2 3 4 5 62refV
2refV
2.5-b/s TFPipeline ADC 1st stage
Vin
Vout
t+δtt t+δt
ΔVskew
ΔVskew
S/H
A/D D/A
Clockt
Vin
3 bits
Vout22
0-Vref
0
Vref
Vref
0 1 2 3 4 5 62refV
2refV
2.5-b/s TFPipeline ADC 1st stage
Vin
Vout
tt
Without sampling clock skew, residues are bounded between ±Vref/2
With sampling clock skew, some residues are pushed exceeding ±Vref/2
ADC Conversion errors occur when residues exceed ±Vref
The larger the sampling clock skew, the more residues exceed ±Vref/2
Calibration Algorithm (II)S/H
A/D D/A
Clock
Digital Calibration
t
Vin
Delay
Vout
3 bits
t-Δt1 t+Δt2
t
Delay
22
Two sub-ADC sampling timings are initially apart, with S/H sampling timing in between.
tt-Δt1_initial t+Δt2_initial
tt-Δt1_initial t+Δt2_initial
The sub-ADC timing resulting in more out-of-bound residues is stepped towards the other
In steady state, both sub-ADC timings converge to the S/H sampling timing.
Calibration implementation
About 1800 gates, 8-bit digital delay control, 2000-Sample/update
Simulation Setup
Simulation Results
Simulator SIMULINK
Simulated architecture 2.5-b/s with calibration
Sine-wave Input signal Full range 500 MHz
Comparator offset (σ) 15 mV
Comparator noise (σ) 5 mV
Clock skew among comparators (σ) 5 ps
LSB size of the digital delay line 4 ps
No. of samples observed per update 1000
0 0.01 0.02 0.03 0.04 0.05100
150
200
250
[ps]
0 0.01 0.02 0.03 0.04 0.05100
150
200
250
Time [s]
[ps]
A time-varying S/H clock
Sub-ADC clock
Convergence of the algorithm Conversion error free in tracking
tt-Δt1_initial t+Δt2_initial
1: error
0: correct
MUXCOMP
∑ Err Control code 1 Control
Codes Update
ADC 1st Stage
Delay Circuit
clk
Control Code 1
∑ Err Control code 2
Control Code 2
Error Residue out-of-range
