A GENERAL S-DOMAIN HIERARCHICAL NETWORK REDUCTION ALGORITHM

Sheldon X.-D. Tan

Department of Electrical EngineeringUniversity of California, Riverside, CA 92521, USA

stan@ee.ucr.edu

ABSTRACTThis paper presents an efficient method to reduce complexities ofa linear network in s-domain. The new method works on circuitmatrices directly and reduces the circuit complexities by eliminat-ing subcircuits in a hierarchical way. The resulting admittancesin the reduced networks are kept as rational functions of s withreduced order. Some theoretical results are characterized for thepresence of common factors coming from the suppression of sub-circuits. A novel common factor removal (de-cancellation) strat-egy based on a graph-based hierarchical subcircuit reduction pro-cess is proposed. The resulting reduction algorithm is applicableto any linear circuits in s-domain. The stability of the reduced sys-tem is enforced by applying the Hurwitz polynomial approxima-tion. The reduced systems can be used for fast s-domain analysisand for time domain waveform evaluation. Experimental resultson both linear analog circuits and RLC circuits, and comparisonwith SPICE in s-domain analysis are also provided.

1. INTRODUCTION

As feature size keeps shrinking and clock rate continues roaring,physical effect related signal integrity issues become more severe[1].Fast and accurate evaluation and modeling of analog/mixed-signaland interconnect circuits are critical for top-down mixed-signalSoC designs and interconnect-centered physical design and opti-mization [7, 8].

Due to the importance of many on-chip global interconnectslike power /ground grid, global signal nets and clock trees, a num-ber of projection-based model-order reduction based techniqueshave been introduced [4, 5, 6, 11, 12, 17, 18] to analyze the tran-sient behavior of interconnects. Asymptotic Waveform Evaluation(AWE) algorithm was first proposed [12, 13] where explicit mo-ment matching was used to compute the dominant poles at lowfrequencies. But AWE method is numerically unstable for higherorder approximation. Thereafter a number of other projection-based model-order reduction methods based on implicit momentmatching (via Krylov subspace projection) were developed. Ex-amples are Pade via Lanczos (PVL) [4], Matrix PVL [5], Arnoldimethod [17], Arnoldi Transformation method [18], PRIMA [11]and SyPVL algorithm [6]. The projection-based algorithms re-quire the computations of the moments or Krylov subspace basevectors before reduction. So at least one DC solution of the wholecircuit is required, which may not be efficient for highly connectedstructures like mesh-structured power distribution networks withmillions of nodes. Also those projection-based methods are notefficient for circuits with many independent sources as indepen-dent sources can not be reduced by those methods in general.

Another approach to circuit complexity reduction is by meansof local node reduction. The main idea is to reduce the number

of nodes in the circuits and approximate the left elements in thecircuit matrix in reduced rational forms. The major advantage ofthose methods over projection-based methods is that the reduc-tion can be done in a local manner and no overall solutions ofthe whole circuit are required (with some realization techniques),which makes those methods very amenable to attack large linearnetworks. This idea has been explored by approximate Gaussianelimination for RC circuits [3], by direct truncation of the trans-fer function algorithm (DTT) [10] for tree-structured RLC circuitsand an extended DTT method for non-tree structured RLC cir-cuits [21]. Recently a topology based node-reduction method wasproposed [14], in which nodes are reduced one at a time (topologi-cally it is called Y -∆ transformation) and the generated admittancein the reduced network is represented as an order-reduced ratio-nal function of s. This method is equivalent to symbolic Gaus-sian elimination (s is the only symbol) but the reduction is doneon circuit topologies only. The stability is enforced by Hurwitzpolynomial approximation. But this method only works for lin-ear circuits with limited element types (RCLK-VJ) and cannot beapplied to reduce general linear circuits.

In this paper, we propose a new approach to reducing the com-plexities of linear circuits in s-domain. The new method performsthe node reduction directly on the circuit matrices and hence it isgeneral enough to reduce any linear circuits. Furthermore, insteadof reducing one node at a time as done in [14]. The new methodallows elimination of multiple nodes simultaneously. This leadsto a general hierarchical s-domain analysis technique as we cansuppress subcircuits, which consist of a number of nodes, one at atime in a hierarchical and an independent way. The new methodthus is able to exploit the naturally hierarchical structures inher-ent in many linear circuits. Such a hierarchical node reductionis made possible by means of a graph based symbolic analysistechnique for computing the new admittances and removing thecommon factors (de-cancellation) in determinants [15, 16] – thekey operations in the new hierarchical node algorithm. Hurwitzpolynomial approximation is also performed on the order-reducedtransfer functions to enforce stability. The resulting algorithm canperform efficient s-domain analysis and time-domain analysis onany linear network with very high accuracy.

This paper is organized as follows. Section 2 reviews thematrix-based node reduction approach and concepts of DDDs ands-expanded DDDs for driving transfer functions of linear networks.Section 3 presents some theoretical results for the presence of com-mon factors during subcircuit reduction processes. Section 4 presentsour new approaches to the circuit complexity reduction on linearcircuits. Experimental results are described in Section 5. Section 6concludes the paper.

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2. SUBCIRCUIT REDUCTION AND DDD GRAPHS2.1. Subcircuit Reduction

In this section, we briefly review how nodes in a subcircuit can besuppressed in the matrix form. Consider a subcircuit with some in-ternal structures and terminals. The circuit unknowns—the node-voltage variables and branch-current variables—can be partitionedinto three disjoint groups xI , xB, and xR, where the superscripts I,B, R stand for, respectively, internal variables, boundary variablesand the rest of variables. Internal variables are those local to thesubcircuit, boundary variables (also called tearing variables) arethose related to both the subcircuit and the rest of the circuit. Notethat boundary variables include those variables required as the cir-cuit inputs and outputs. With this, the system-equation set Ax = b,can be rewritten in the following form:

AII AIB 0ABI ABB ABR

0 ARB ARR

xI

xB

xR

=

BI

BB

BR

. (1)

The matrix, AII , is the internal matrix associated with internalvariable vector xI .

Subcircuit suppression is to eliminate all the variables in xI ,and to transform (1) into the following reduced set of equations:

[

ABB∗ ABR

ARB ARR

][

xB

xR

]

=

[

BB∗

BR

]

, (2)

where

ABB∗ = ABB −ABI(AII)−1AIB, (3)

= ABB −1

det(AII)ABI [∆II

u,v]T AIB, (4)

where [∆u,v]T is called the adjoint matrix of A, ∆u,v is the first-

order cofactor of det(A) with respect to au,v, and matrix Aau,v isthe (n− 1)× (n− 1)-matrix obtained from matrix A by deletingrow u and column v and

BB∗ = BB −ABI(AII)−1BI , (5)

= BB −1

det(AII)ABI [∆II

u,v]T BI . (6)

Subcircuit suppression can be performed for all the subcir-cuits by visiting the circuit hierarchy in a bottom-up fashion. Sup-pose that the number of internal variables is m, and the numberof boundary variables is l. Eq.(4) and (6) can be written in thefollowing expanded forms:

aBB∗u,v (s) = aBB

u,v(s)−1

det(AII(s))

m

∑k1 ,k2=1

aBIu,k1

(s)∆IIk2,k1

(s)aIBk2 ,v(s), (7)

where u,v = 1, ..., l and

bB∗u (s) = bB

u (s)−1

det(AII(s))

m

∑k1 ,k2=1

aBIu,k1

(s)∆IIk2,k1

(s)bIk2

(s), (8)

where u = 1, ..., l. From Equations (7) and (8), we can observethat admittance aBB∗

u,v and input stimuli bB∗u at boundary nodes will

become rational functions of s once the subcircuit is suppressed.In order to obtain the rational functions for aBB∗

u,v (s) and bB∗u (s),

we need to compute the rational function for a determinant whoseelements may again be rational functions of s. This task can beachieved via determinant decision diagrams (DDDs), which was

proposed originally for symbolic analysis of large analog circuits [15,20]. We will show how the DDD graphs can be modified to com-pute the rational function for a determinant in the later sections.

An important issue is that we can only keep limited order ofs for each rational function of s during the subcircuit reductionprocess. That implies that no common factors, which are functionsof s, are allowed between the numerator and denominator of therational functions in aBB∗

u,v (s) and bB∗u (s). Otherwise, the reduced

order is not correct. Such a cancellation-free rational functionsbear the real order of the rational functions. Actually accordingto the definition of a determinant, it can be seen that the true (orcancellation-free) order of s in the denominators of both aBB∗

u,v (s)

and bB∗u (s) depends only on the product terms with the highest

order of s in det(AII(s)), which in turn depends on the numberof nodes reduced in the subcircuit, not on how those nodes arereduced. Notice also that the order of s changes from terms toterms, but the number of basic admittance from circuit devicesin the denominators of the those newly generated terms are samefor all the composite admittance terms. The number is called theadmittance order of the term in the sequel.

But if the nodes in the subcircuit are reduced in different sub-circuits at different hierarchical circuit-levels and are reduced atdifferent time as shown later, common factors will automaticallybe generated in aBB∗

u,v (s) and bB∗u (s). This has been observed al-

ready when nodes are reduced one at a time in Y −∆ transforma-tion algorithm [14]. As a result, how to remove those commonfactors (de-cancellation) in the rational functions of aBB∗

u,v (s) andbB∗

u (s) in general becomes a key issue for the subcircuit reductionprocess. Fortunately, such cancellation-free rational functions canbe obtained by efficient DDD graph operations. The DDD conceptwill be briefly reviewed in the following subsection.

2.2. Determinant Decision Diagrams

Determinant Decision Diagrams [15] are compact and canonicalgraph-based representation of determinants. A DDD is a signed,rooted, directed acyclic graph with two terminal vertices, namelythe 0-terminal vertex and the 1-terminal vertex. Each non-terminalDDD vertex is labeled by a symbol in the determinant denoted byai, and a positive or negative sign denoted by s(ai). It originatestwo outgoing edges, called 1-edge and 0-edge. Each vertex ai rep-resents a symbolic expression D(ai) defined recursively as follows:D(ai) = ai s(ai) Dai + Dai , where Dai and Dai represent, respec-tively, the symbolic expressions of the vertices pointed by the 1-edge and 0-edge of ai. The 1-terminal vertex represents expression1, whereas the 0-terminal vertex represents expression 0. Such aDDD is called a complex DDD as each DDD node is function ofcomplex frequency variable s.

To exploit the DDD to derive transfer rational functions of s,we need to directly represent circuit parameters not matrix en-tries. To this end, s-expanded DDDs are introduced [16]. Thes-expanded DDD can be constructed from the complex DDD lin-early in the size of the original complex DDD [16]. Once a coef-ficient DDD is constructed, its numerical value can be easily ob-tained by simply traversing all the vertices in the coefficient DDDgraph and carrying out one addition and one multiplication at eachvertex [15]. In this way, we can derive the rational function of sfor any given determinant.

For our problem, some elements (in admittance forms) of acircuit matrix will become a rational function of s during the hier-archical subcircuit reduction process. As a result, the construction

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of the rational function for such a determinant will be differentfrom the method used for s-expanded DDDs [16]. A new DDDgraph, called Y-expanded DDDs (YDDDs) are introduced for thistask, which will be explained in Section 4.

3. CANCELLATION IN SUBCIRCUIT REDUCTION

In this section, we explain how cancellation happens from circuitdevices and at different circuit levels and give some theoreticalresults.

3.1. Cancellation Due to Circuit Devices

The common factors will be introduced when the same circuit pa-rameter will appear more than once in a circuit matrix in MNAformulation for subcircuits. Two cancellation patterns are shownin Fig. 1.

−x x

x −x

−x x

x −x

j

l k

i

Case 2Case 1

j

i

i j

Figure 1: Matrix patterns causing term cancellation.

Case 1 comes from the rectangular appearance of a floatingresistor in a admittance matrix and case 2 reflects the pattern froma voltage controlled current source (VCCS). As a result, all theproduct terms consisting of elements at (i, i) and at ( j, j) will can-cel all the terms consisting of elements at (i, j) and at ( j, i) forcase 1. The same is true for Case 2. Those canceling terms cancause two problems. First if the values of canceled terms are sig-nificantly larger than the actual values of some coefficients of ra-tional functions, it will introduce large errors due to round-off er-rors. Second, notice that x and −x are in the same row or column,they will be in different product terms and added together later.If x is a rational function (for example, we use 1/sL for induc-tance) a common factor among the numerator and the dominatorwill be introduced in the resulting rational function. For instance,let’s consider addition of two rational functions a1/b1 + a2/b2 =(a1 ∗ b2 + a2 ∗ b1)/(b1 ∗ b2). If there is a common term c in bothb1 = x∗c and b2 = y∗c, c will become a common factor in both thenumerator and the denominator of the resulting rational function.

Cancellation due to case 1 and case 2 in Fig. 1 can be easilyremoved during or after YDDD construction which is similar tos-expanded DDDs [16].

3.2. Cancellation at Middle Circuit Levels

Once a subcircuit has been suppressed, new cancellation patternsare created. This is illustrated in Fig.2

Nodes at (k1,k2) and at (t1,t2) are the internal nodes in a sub-circuit to be suppressed. Nodes at (u1,u2) and at (v1,v2) are bound-ary nodes. Their connections with the two internal nodes are shownin the right-hand side of Fig. 2. As a result, admittances au1 ,k2 ,ak1,u2 , av1,t2 and at1,v2 are not zero. According to Eq.(7) we have,

a′v1,u2= av1,u2 −

av1 ,t2∆Ik1,t2

ak1,u2

det(AI), (9)

a′u1,v2= au1 ,v2 −

au1 ,k2 ∆It1,k2

at1,v2

det(AI), (10)

subckt

b b

b

````

k1 ,k2

t1, t2

u1 ,u2

u1 ,k2

t1,v2

u1 ,v2

v1 , t2 v1 ,u2 v1 ,v2

k1 ,u2

k1 ,k2

u1 ,u2

v1 ,v2

t1, t2

t1,k2

k1 , t2

subckt

b

Figure 2: Cancellation patterns at middle circuit levels

a′u1 ,u2= au1,u2 −

au1,k2 ∆Ik1,k2

ak1,u2

det(AI), (11)

a′v1,v2= av1,v2 −

av1,t2 ∆It1,t2 at1,v2

det(AI), (12)

where, a′x,y is the new admittance at (x,y). det(AI) is the inter-nal system determinant of the subcircuit suppressed and ∆I

x,y isthe first-order cofactor of det(AI) with respect to element (x,y).av1 ,t2 ∆I

k1 ,t2ak1 ,u2

det(AI) terms is called composite admittance in the sequel.Since the four new composite admittances appear in two rows andtwo columns, they will cause new cancellations when node (u1,u2)and (v1,v2) are suppressed as the internal nodes in the upper levelsubcircuits. Specifically, we will have the following product termsin the internal system determinant of the upper-level subcircuit ac-cording to the definition of a determinant.

a′u1,u2a′v1 ,v2

−a′v1,u2a′u1,v2

=

Rx +au1 ,k2 av1,t2 ∆I

k1,k2∆I

t1,t2 ak1,u2 at1,v2

det(AI)det(AI)

−au1,k2 av1,t2 ∆I

k1,t2∆I

t1,k2ak1,u2 at1,v2

det(AI)det(AI)(13)

where Rx is the rest of other terms when the products of the new ad-mittances are expanded. We have two scenarios to consider. First,if nodes (k1,k2) and (t1,t2) are the same node, i.e. k1 = t1,k2 = t2,the last two terms in (13) will cancel each other as ∆I

k1,k2∆I

t1,t2 =

∆Ik1,t2

∆It1,k2

. Second, more generally if those two nodes are differ-ent internal nodes, we will show that the combined last two termsin (13) has a common factor in the numerator and the denominator.To see this, we first introduce the following theorem.

Theorem 1 Given a matrix A and its four elements at rows i, jand columns m,n as shown in Fig. 3, we have

∣

∣

∣

∣

∆im ∆in∆ jm ∆ jn

∣

∣

∣

∣

= ∆im∆ jn −∆in∆ jm = det(A)∆i,m, j,n, (14)

where ∆im, jn is

∆im, jn = (−1)i+m(−1) j+ndet(Aim jn), (15)

which is the second-order cofactor with rows i, j and columns m,nremoved from det(A).

The proof of the theorem is omitted due to limited space. Instead,we illustrate the theorem using the following 3 × 3 full matrix

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i

A =

m n

aim ain

a jm a jnj

Figure 3: Illustration of Theorem 1

A3×3.

A3×3 =

a11 a12 a13a21 a22 a23a31 a32 a33

Let’s consider the following 4 first order cofactors with respect toa21,a22,a31, and a32 respectively:

∆21 = −

∣

∣

∣

∣

a12 a13a32 a33

∣

∣

∣

∣

∆22 =

∣

∣

∣

∣

a11 a13a31 a33

∣

∣

∣

∣

∆31 =

∣

∣

∣

∣

a12 a13a22 a23

∣

∣

∣

∣

∆32 = −

∣

∣

∣

∣

a11 a13a21 a23

∣

∣

∣

∣

Then we have∆21∆32 −∆22∆31

= (a12a11a23a33 −a12a13a21a33 −a13a11a23a32 +a213a32a21)

−(a11a12a23a33 −a11a13a22a33 −a12a23a13a31 +a213a31a22)

= a213(a32a21 −a31a22)+a12a13(a23a31 −a21a33)+

a11a13(a22a33 −a23a32)

= a13[a13(a32a21 −a31a22)+a12(a23a31 −a21a33)

+a11(a22a33 −a23a32)]

= det(A3×3)a13

= det(A3×3)∆21,32

As a result, we know that det(AI) is a common factor in thecombined last two terms in (13), which will become

au1,k2 av1,t2 ∆Ik1,k2,t1,t2

ak1,u2 at1,v2

det(AI)(16)

after the common factor det(AI) in the numerator and the denom-inator cancels.

For any four composite admittances appearing at four rectan-gular positions (at two rows and columns), their corresponding∆k1,k2 may have different position patterns in the original circuitmatrix. If they appear also at four rectangular positions, the result-ing product (becoming higher order terms) of those composite ad-mittances will merge (after removal of common factors in numera-tors and denominators) as predicted by Theory 1. Otherwise (theyonly appear in only one row or one column or just one position)the two product terms will cancel out (become zero when addedtogether) as ∆I

k1,k2∆I

t1,t2 are identicial to ∆Ik1,t2

∆It1,k2

in Eq.( 13).In general, if the composite admittances from the suppression

of one subcircuit populate more than two rows and columns, theircorresponding first order cofactors ∆k1,k2 may also appear morethan two rows and columns in the original circuit matrix. Detailed

j1

A =

ai1 j1 ai1 jkai1 jm

aik j1 aik jkaik jm

aim j1 aim jkaim jm

i1

ik

im

jk jm

Figure 4: Illustration of Theorem 2

study shows if the number of rows or columns occupied by thosefirst order cofactors are less than that of their composite admit-tances in the original circuit matrix, those higher-order admittanceterms will eventually cancel out. But if the number of rows orcolumns of those first order cofactors equals to that of their cor-responding composite admittances, we have the following moregeneral theorem.

Theorem 2 Given a matrix A and its m × m elements at rowsi1, ..., im and columns j1, ..., jm as shown in Fig. 4, we have

∣

∣

∣

∣

∣

∆i1 j1 ... ∆i1 jk ... ∆i1 jm∆ik j1 ... ∆ik jk ... ∆ik jm∆im j1 ... ∆im jk ... ∆im jm

∣

∣

∣

∣

∣

= det(A)m−1∆i1 j1,...,im, jm ,

(17)where ∆i1 j1,...,im , jm is mth order cofactor with rows i1, ..., im andcolumns j1, ..., jm removed from det(A).

Notice that for a n × n matrix A, we have A−1 = 1det(A)

[∆u,v]T ,

where [∆u,v]T is the adjoint matrix of A. We have

det(A−1) =1

det(A)n det([∆u,v]T ])

=1

det(A)n det([∆u,v]] (18)

Given that det(A−1)×det(A) = 1, we have

det([∆u,v]) = det(A)n−1 (19)

This is the exact case in Theory 2 when m equals the matrix size nand ∆11,...,nn = 1. In summary, we have the following result.

Corollary 1 Let AI be the internal system matrix of an immedi-ate subcircuit, then det(AI)(k−1) will be the common factor of thenumerator and the denominator for all the terms consisting of kfirst-order cofactors of det(AI) when they are added together dur-ing the computation of the determinant consisting of those terms ifthey can’t cancel out.

As a result, we can see that any higher order terms coming frommultiplications of composite admittances will eventually merge orcancel out with other same-order terms so that the resulting termswill have the correct admittance order. This is also consistent withthe observation that no matter how internal nodes are reduced, theadmittances in the reduced circuit should have the same admittanceorder given the same set of reduced nodes.

Also if the boundary nodes like (u1,u2) connect more thanone internal nodes, the new admittances for the boundary nodes

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will have more than one composite terms. But det(AI)k will stillbe the common factor when those boundary nodes are suppressedat the next circuit level. To efficiently remove the common fac-tors, we combine all the composite admittances with the samedet(AI) in their denominator into one composite admittance. Sothe maximum number of merged composite admittances are equalto the number of immediate subcircuits suppressed at present cir-cuit level at each element of circuit matrix. Each of the combinedcomposite admittance will be represented by a YDDD node inthe reduced circuit matrix. In this way, we can explicitly handlethe cancellation situations via DDD-based graph operations to beshown in Section 4.

3.3. Cancellation at Different Circuit Levels

If the nodes (u1,u2) and (v1,v2) in Fig. 2 are reduced in differ-ent subcircuits at different circuit hierarchical levels, cancellationwill happen when those composite admittance from different sub-circuits are merged. To see this, suppose that only node (u1,u2)is selected to be suppressed in subcircuit II. As a result, the newelement value at node (v1,v2), which is not suppressed, become

a′′v1 ,v2= a′v1 ,v2

−a′v1 ,u2

∆IIu1,u2

a′u1 ,v2

det(AII)(20)

We also notice that

det(AII) = a′u1 ,u2∆II

u1,u2+RII

u1,u2.

As a result, we have

a′′v1 ,v2= a′v1 ,v2

−a′v1 ,u2

∆IIu1 ,u2

a′u1 ,v2

a′u1 ,u2∆II

u1,u2+RII

u1,u2

=(a′u1,u2

a′v1 ,v2−a′v1 ,u2

a′u1 ,v2)∆II

u1 ,u2+a′v1 ,v2

RII

a′u1 ,u2∆II

u1 ,u2+RII (21)

Notice that (a′u1 ,u2a′v1,v2

− a′v1,u2a′u1 ,v2

) is just Eq.(13). Thereforewe know that det(AI) is the common factor in the numerator andthe denominator of the resulting rational function. After the com-mon factor det(AI) is removed, a′′v1,v2

will become cancellation-free.

If det(AI) is also in the denominator of ∆IIu1,u2

, this means thatmore than two first-order cofactors of det(AI) are present. Thecancellation will happen exactly the same way as at the middlecircuit levels and det(AI)k is still the common factor. Those can-cellation will happen when all the composite terms from subcircuitI in a′′v1,v2

are added together.In our algorithm, when a matrix element consists of composite

admittances from different subcircuit suppressions and those sub-circuits are hierarchically related (they come from the same toplevel subcircuit call), we will merge them into one composite ad-mittance and remove the common factor, det(AI)k, where k = 1or 2. k will not be more than 2 because determinants or cofac-tors can be computed in a cancellation-free manner such that theresulting admittances are always in the correct admittance orderas shown in Section 4. Such a merging or de-canceling processshould have such an effect that the resulting rational compositeadmittance should be the same regardless of how those suppressedinternal nodes are eliminated (one by one or subcircuit by subcir-cuit).

4. NEW S-DOMAIN HIERARCHICAL NETWORKREDUCTION ALGORITHM

In this section, we detail our network reduction algorithm basedon cancellation rules discussed in early sections. In order to effi-ciently compute the rational function of a determinant and handlecancellations in the composite admittances, which are also ratio-nal function of s, an new DDD graph called Y-expanded DDDs(YDDD) is first introduced.

4.1. Y-expanded DDDs

Y-expanded DDDs are also DDD graphs where each DDD noderepresents a circuit parameter in admittance form as shown in Fig. 5.

0−edge

a

bs

c

dsf

1 0

e

c+dsa+bs

e f

1−edge

Figure 5: A determinant and its YDDD

Note that some circuit parameter admittances are function ofthe complex frequency variable s. This is different from the s-expanded DDD graphs where s is explicitly extracted [16]. Themain propose of introduction of YDDDs is that we can easilyhandle aforementioned cancellation situations as this will becomeclear later. Similar to s-expanded DDD [16], the YDDDs canbe constructed from the complex DDD in linear time in the sizeof the original complex DDDs and are free from the symbolicmultiplication-induced cancellation from circuit devices.

4.2. Construction of Cancellation-Free Y -Expanded DDDs

Once a YDDD is constructed for a determinant, we need to com-pute the cancellation-free rational function from the YDDD. Thiscan be done in a bottom up fashion. At each YDDD node P, wecompute the rational function from the YDDD tree rooted at Precursively. Let Pr = NPr /DPr denote the rational function of ad-mittance that the YDDD node P itself represents. P1 = NP1/DP1

and P0 = NP0/DP0 represent the rational functions of the YDDDsubtree rooted at nodes pointed by the 1-edge and 0-edge of Prespectively. The rational function of the tree rooted at P will be-come [15]

FP = sign(P)Pr(s)P1(s)+P0(s)

= sign(P)NPr (s)DPr (s)

NP1(s)DP1(s)

+NP0(s)DP0(s)

. (22)

With Eq. (22), the rational function at the root of the whole YDDDcan be computed recursively. But if there are common factorsamong denominators of Pr, P1 and P0, the common factors haveto be taken care of.

Specifically, we need to look at two situations where the com-mon factors are introduced into the numerators and denominatorsof resulting rational functions. The first one comes from multipli-cation of Pr(s) and P1(s) according to Corollary 1. The secondone is due to the addition of two rational functions, in Eq.(22),with common factors in their denominators. Those two situationsare handled separately in our method.

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1. Cancellation due to multiplication. For cancellation fromcircuit devices, cancellation can be handled by dynamicallyremoving all the canceling terms via DDD-based symbolicoperations [15].For cancellation at middle circuit levels due to subcircuitsuppressions, we observe that the new composite admit-tance will always have correct admittance order when allcancellations are carried out (for both cancellations betweennumerators and denominators, and cancellation among dif-ferent product terms). Also for order-correct admittance,we notice that only det(AI)k and k = 1 will be present inthe denominator of the final composite admittances for eachsubcircuit from a circuit hierarchy, where AI is the internalsystem determinant of an immediate subcircuit. This mo-tivates a very simple cancellation strategy: whenever wesee admittance order is increased due to multiplication oftwo terms that both have det(AI)k in their denominators,we divide the resulting numerator by det(AI)k. In this way,the resulting admittance terms are always in the correct ad-mittance order and the actual cancellation will be carriedout implicitly when all the resulting terms are visited andadded together. Such a constant admittance strategy is ableto handle all the multiplication-induced cancellations with-out explicitly considering how the cancellation is carriedout and what kind of cancellations they are.

2. Cancellation due to addition. For the addition-induced can-cellation, the cancellations from circuit devices and at mid-dle circuit levels are handled in the same way. The idea isthat when adding of two rational admittances takes place,we explicitly watch for the devices which have no trivialdominators (trivial dominator is 1) such that their domina-tors will not appear twice in the resulting new admittance.For composite admittances, this rule requires that only onedet(AI) for each subcircuit from a circuit hierarchy existsin the denominator of the resulting admittance.

Now we are ready to present the whole rational admittancecomputation method for a determinant represented by its YDDDtree. For each YDDD node P, we keep two things: the numera-tor polynomial of the computed rational admittance for the subtreerooted at P – denoted by N(P) and a set of YDDD indexes whosedenominators are not trivial and unique – denoted by SD(P). Inthis way we do not need to keep the denominator polynomial foreach YDDD node explicitly and it also easy to watch the cancella-tion situations. P(D) denotes the rational admittance for the DDDsubtree rooted at D. D.index is the index of the DDD node D. Fol-lowing the conversion of DDD operations, we use D.1 and D.0 torepresent the DDD subtrees pointed by 1-edge and 0-edge of DDDvertex D respectively. The resulting algorithm is shown Fig. 6.

The algorithm basically visits every YDDD node once in abottom-up fashion and computes the new rational admittance foreach subtree rooted at the YDDD node visited. So the time com-plexity of the algorithm is O(|DDD|∗k), where |DDD| is the num-ber of YDDD nodes and k is the highest order of all the rationaladmittance. It was shown that YDDD representation is more com-pact than sequence of expressions [9, 20], which essentially rep-resent the complexity of symbolic node-by-node Gaussian elimi-nation process. Hence time complexity of our reduction is betterthan Y −∆ reduction algorithm [14], which is based on Gaussianelimination.

Another advantage of the new algorithm over the existing Y −∆ reduction algorithm is that the reduction history for each node

COMPRAFUNC(P)1 if ( P = zero or P = one or computed already)2 return3 COMPRAFUNC(P.0)4 COMPRAFUNC(P.1)5 N1 = N(P.1)6 N0 = N(P.0)7 if (P(P)’s denominator is not trivial and not exist in SD(P.1))8 S1 = SD(P.1)∪P.index9 else10 S1 = SD(P.1)11 S0 = SD(P.0)12 N1 = sign(P)∗N(Pr)∗N1

13 if (both Pr and P(P.1) contain det(AI ))14 N1 = N1/det(AI )15 if (both Pr and P(P.1) consist of devices with

non-trivial denominator Ddvs)16 N1 = N1/Ddvs17 Compute N(P) from N1, N0 , and SD(P) from S1 and S0

such that det(AI) and each device appear once in SD(P).

Figure 6: Computation of the rational function from a YDDD.

(the neighborhood nodes reduced before the node) are not required.Our reduction process only requires the knowledge of the imme-diate subcircuits seen at present circuit level as the effects of allthe lower level subcircuits will be merged into those immediatesubcircuits and the internal system determinants det(AI) of thoseimmediate subcircuit are the only common factors for higher levelcircuit reduction (except for common factors from circuit devices).Such a reduction-history independent feature can leads to signifi-cant memory save for reduction of large linear networks comparedwith Y −∆ reduction algorithm.

For de-cancellation at different circuit levels shown in Fig. 20,the constant admittance strategy is still followed so that the mergedadmittance from different subcircuits has the same admittance or-der by dividing the common factor det(AI).

4.3. Hurwitz Approximation To Enforce Stability

As stated in [22], Hurwitz approximation is an effective method toenforce the stability of the order-reduced transfer functions of theRLC circuit system. A polynomial is called a Hurwitz polynomialif all its roots have negative real parts [2]. For a given RLC systemwith a rational transfer function H(s). H(s) is stable if and only ifits denominator is a Hurwitz polynomial [2].

Suppose the transfer function for a RLC system is

H(s) =N(s)D(s)

=1+a1s+a2s2 + . . .+apsp

b0 +b1s+b2s2 + . . .+bqsq , (23)

Without losing generality, let q be even. We use m(s) and n(s) torepresent the even and odd parts of D(s) respectively:

m(s) = b0 +b2s2 + . . .+bqsq, (24)

n(s) = b1 +b3s3 + . . .+bq−1sq−1. (25)

Then the fraction n(s)/m(s) can be written as the following form:

n(s)m(s)

=1

c0s−1 + 1c1s−1+ 1

...+ 1cq−1s−1

, (26)

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where D(s) is said to be a Hurwitz polynomial if the coefficientsc0, c1, . . .,cq−1 are all positive. To find a kth-order Hurwitz ap-proximation Hk(s) for a given transfer function H(s), we can keepall the positive coefficients c0 up to ck and ignore all the othercoefficients, and then re-calculate the odd and even parts of the de-nominator Dk(s) of Hk(s) according to equation (26). Once we ob-tain the stable new denominator Dk(s), the new numerator, Nk(s),

in the final approximated rational function Hk(s) =Nk(s)Dk(s)

can beobtained with explicit moment matching by which the first k mo-ments are equivalent in Hk(s) and H(s), or H(s)−Hk(s) = O(sk).The new transfer function Hk(s) is the kth-order Hurwitz approxi-mation of the original system and is guaranteed to be stable. Notethat the explicit moment matching here is numerical stable for veryhigh orders as no ill-conditioned matrix is solved as is the case forAWE [12].

4.4. Overview of The Reduction Algorithm

After describing several critical aspects of the reduction algorithm,we are ready to give an overview of the whole reduction algorithmin this subsection. We assume that the circuit hierarchy has beendefined already.

The General Hierarchical Network Reduction Algorithm

1. Build the complex DDDs for each subcircuit system matrixand all the required cofactors in a bottom up way.

2. If the present circuit has subcircuits, perform the reductionon each subcircuit first.

3. In the present circuit, identify all the admittances, which areeither from circuit parameters or are composite admittancedue to subcircuit suppression.

4. Merge all the composite admittances from subcircuits atdifferent circuit hierarchical levels and remove common fac-tors by dividing the numerators by det(AI), which is theinternal system determinant of an immediate subcircuit atlower circuit level. The merging process is done from thelowest level to the highest level.

5. Derive the YDDDs from complex DDDs for the internalsystem determinant and all the cofactors for upper levelcircuits or for required transfer function using COMPRA-FUNC()

6. Perform Hurwitz approximation on the reduced transfer func-tions.

5. EXPERIMENTAL RESULTS

The proposed algorithm is implemented in C++. We perform thereduction on a number of linear analog circuits. Here we presentthe exact transfer function for a second order linear filter shownin Fig. 7 obtained from our reduction program. In this circuit, wehave R1 = 1kΩ, R2 = 2kΩ, R3 = 5kΩ, C1 = 10nF , C2 = 20nF ,A0 is an Opamp circuit, a simple implementation of it is shown inFig. 8. The transfer function obtained by our program is shown inthe following:

H(s) =Vout(s)Vin(s)

=

5.33×10−7+2.68×10−15s+3.72×10−19s2

1.02×10−3+2.66×10−6s2.66×10−7+9.07×10−11s+5.46×10−16s2+7.47×10−23s3

1.02×10−3+2.66×10−6s

Vin

C2

A0+

− VoutR1 R2

C1

Figure 7: A second-order active filter

V2

+

Ri2

V1Rii

Ri1

R1

g1V1 g2V2

Rld

−−3

1

C1

+

−

42

Figure 8: A linear model of an Opamp circuit.

Note that both the numerator and the denominator become ra-tional functions of s due to suppression of subcircuit A0. But theyshare a common denominator which is actually the internal systemdeterminant – det(AA0) of the subcircuit A0. After the commondenominator is removed, the transfer function is exactly the sameone as we obtain from the flatten filter circuit. We also notice thatthe highest order of the transfer function of the second order filterbecomes 3. But if Opamp A0 is a ideal voltage controlled currentsource with infinite gain, the highest order will be 2.

We also notice that since the admittance orders (the number ofadmittances of circuit devices in the denominator) of new admit-tances are preserved, the numerical magnitudes of the coefficientsat varying orders of s in both numerators and denominators of thenew admittance will grow or decrease very fast with number ofnodes reduced. As a result, proper scaling of input data is requiredfor reduction of very large linear networks.

Second, we test the proposed algorithm on a number of RLCcircuits, some of the circuits are extracted clock wires and busstructure coupled wires. The experimental results are obtained ona Linux workstation with dual 1GHz P-III CPUs and 2G mem-ory. In our examples, 15th order is the highest order kept for thegenerated admittances.

The statistics are summarized in the table 1. The first columngives the names of the circuits, ckt1 to ckt4 are general RC circuitswith many coupling capacitors; ckt tree5 and ckt tree6 are RCLtree circuits. Column #nodes gives the number of nodes in eachcircuit. To obtain the responses from SPICE, the largest numberof nodes in a circuit is about 80k. Column #level shows the highesthierarchical level in each circuits. The hierarchical structures areobtained via an automatic partitioning algorithm [19]. Column #Cand #L are the number of capacitors and inductors in each circuit.Column new method (CPU) is the CPU time for the new algorithmto perform the reduction and to perform the s-domain analysis onthe reduced network on 100 sampling points. The last column isthe CPU time used by SPICE for the same s-domain analysis task.

From Table 1, we can observe that the new reduction algorithmis one or two order of magnitudes faster than Spice3f4. It can belogically expected that the speedup will be even more significantfor larger RLC circuits.

Figure 9 gives the responses for different orders of Hurwitz ap-proximations for a small coupled RLC circuit where we can obtainthe exact transfer functions. As the approximation order increases,

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Table 1: Statistics for some RLC circuitsCkt #nodes #level #C #L new

method(CPU)

SPICE(CPU)

ckt1 90 3 120 0 0.26 0.03ckt2 762 6 1016 0 0.76 0.28ckt3 12282 10 16376 0 7.3 47.25ckt4 49146 12 65528 0 27.3 816.15

ckt tree5 20470 10 10235 10235 2.74 388.45ckt tree6 81910 12 40955 40955 10.32 717.720

the approximation gets better.

0 10 20 30 40 50 60 70 80 90 100−0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (ps)

V (

volts

)

Transient Step Respone

exact10th Hurwitz6th Hurwitz3th Hurwitz

Figure 9: Transient step responses given by the new reduction al-gorithm for different order Hurwitz approximation for a coupleRLC circuit.

6. CONCLUSION

In this paper, we have proposed a general hierarchical linear net-work reduction technique in s-domain. The reduction is done bysubcircuit suppression in a hierarchical way and by rational func-tion approximation, which generates order-reduced cancellation-free admittances in the reduced network matrices. The new methodworks on circuit matrices directly and can be applied to any linearcircuits. On the theoretical side, we studied how common fac-tors are generated in the general subcircuit reduction process andpresented some theoretical results. On the practical side, we pro-posed a novel de-cancellation strategy based on determinant deci-sion diagrams to derive the order-reduced rational functions for de-terminants and cofactors generated from subcircuit reductions in acancellation-free manner. The stability is enforced by Hurwitz ap-proximation on the order-reduced transfer functions. Experimentalresults validate the proposed method on some linear analog circuitsand large RLC circuits. For the given RLC linear circuits, the newmethod has shown to offers two orders of magnitude speedup overSpice3f4 in s-domain analysis.

ACKNOWLEDGEMENT

The author would like to thank Dr. Zhanhai Qin and Prof. Chung-Kuan Cheng for discussions on the Y − ∆ transformation algo-rithm, Junjie Yang for implementation of Hurwitz approximationand anonymous reviewers for their constructive comments. Thiswork is partially funded by University of California AcademicSenate Research Fund.

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