A Front End ASIC for the read out of the PMT in the KM3NeT Detector

D. Gajanana TWEPP 2010 1

A Front End ASIC for the read out of the PMT in the KM3NeT Detector

NIKHEF, (National Institute of Subatomic Physics)

Amsterdam, The Netherlands

21-09-2010

Topical Workshop on Electronics for Particle Physics

20-24 September 2010

Aachen, Germany


Introduction to the KM3NeT Experiment. KM3NeT Detector Concept. Read out electronics. Specifications of the ASIC. The Circuit. Test Results. Conclusions & Future.

Contents

21-09-2010


Neutrinos are unique messengers from the most violent, highest-energy processes in our Galaxy and far beyond.

Neutrino astronomy is experimentally highly demanding, requiring vast volumes of target material, such as water or ice & dark environment.

KM3NeT Experiment

21-09-2010

Toulon (France) Pylos (Greece)

Capo Passero (Italy)


The detection of high‐energy muon neutrinos exploits the emission of Cherenkov light by the muon and other charged secondary particles produced in a neutrino interaction.

Photo-Multiplier-Tubes (PMTs) housed in glass spheres (optical modules), are deployed in the deep sea.

KM3NeT Detector concept

21-09-2010

320m


2

switch

I2CDecoder+ Cntrl

3V3switchswitch

Converterboard

12+19

PMT-base

cpld

Signalcollectionboard

Storey-logicboard

ID

Aux.electr.

LVDS

BOB

Photons

HV

apd

2

Comprtr

ThresholdDAC

Pre-amp

osc.1HVDAC

feedback

S

i2c

i2c

FPGA

380V

12V

12V 5V3V3 (Aux. electr.)

opamp

Read-Out Electronics

21-09-2010

ASIC

P. Timmer’s talk

31 ASICs per Optical Module


Time resolution : 2ns (Photon arrival time accuracy) Time-over-Threshold : 1pe → 25ns (800 000 e-)..10pe → 350ns (8000000e-) Number of channels : several hundred thousands. LVDS signaling. I2C slow control. Comparator threshold adjustment: 0…375 000 e- → Vin

com = ±200mV Resolution : 8bits (bin size=1500 e- / 1.2mV)

Reference voltages for High Voltage circuit:

2.0V …2.8V (resolution 8bits)→ High Voltage: -700V …-1500V Power consumption : ~ 20mW Technology: 0.35μm CMOS (AustriaMicroSystems) Immunity to dirty Power supplies Immunity to voltage breakdowns originated in the PMT

Specifications of the ASIC

21-09-2010


Introduction to the KM3NeT Experiment. KM3NeT Detector Concept. Read out electronics. Specifications of the ASIC. The Circuit. Test Results. Conclusions & Future.

Contents

21-09-2010


Analog Part

21-09-2010

•Virtuoso Schematic Entry

Schematic Entry

•ADE / Spectre

Simulation •Virtuoso Layout Editor

Layout

Bandgap1.2V

Bias Block +

Threshold setting DAC for

Comparator

HV setting DAC+

Opamp for HV feedback

Preamp Comparator Buffers LVDS

DAC settings from I2CDAC settings from I2C

From PMT LVDS

DAC outputOpamp outputOpamp input(HV circuit on PCB)

Prototyped before


Preamplifier

21-09-2010

Two-stage charge preamplifier with RC feedback.

Time-to-Threshold

2 photons

1 photon

IN REF. Preamp 1V

OUT

0.5 mA 125 μA

15kΩ

300 fF

Time-over-Threshold


Comparator

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Single Stage comparator.

IN

OUT

Threshold0.8 – 1.2V

375 μA


LVDS Driver

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Conventional LVDS driver, single stage CMFB circuit. 3.5mA * 100Ω = 350mV differential signal.

Pbias

Pbias

Nbias

Nbias

X

X

IN+ IN-

OUT- OUT+

CM REF.1.2V

0.5 mA

3.5 mA

100k 100k


•VHDL, VERILOG

•Text Editor, EASE, EALE

Design Entry

•ModelSim•Simvision

Simulation •Synopsys

Synthesis

•ModelSim•Simvision

Simulation •Synopsys

Scan Chain Insertion

•SOC Encounter

Physical Layout •ModelSim

•Simvision

Simulation

Digital Part

21-09-2010

Clock Generator ~ 10MHz

POR

PROM 20Bits I2C Decoder + PROM Control Logic

I2C BUSBurn Enable

Clk Enable

To DACs

Scan Chain Analog Chain TestHV on-off

Verilog Netlist

Verilog Netlist

Data

Control

Verilog Netlist+SDF files


Digital Simulations - Example

21-09-2010

I2C

PROM

DAC + HV + Control & Test

Post Layout simulations with SDF files (Digital Part only). Tools Used : Modelsim, ncSim suite, Synopsys.


Analog Bondpad Modifications

21-09-2010

Previous pad

Present pad

Possible Solution

Vdd

I/O

Gnd

Internal Circuitry

Power Clamp

Vdd

I/O

Gnd

Internal Circuitry

Power Clamp

Time jitteron the falling

edge

Power supply ripples = ±40mV

Unavoidable – From HV Supply on PCB

Problem

~0.23pF


Layout & Integration

21-09-2010

Band

gap

Bias B

lock

HV Con

trol

Block

Prea

mp

Compa

rato

r +

Buffer

s

LVDS

Clock Genrtr

POR

I2C Decoder+PROM Control

PROM

1.8 mm

Digital Part

Analog Part

Pads, Scribe lines

Final Layout


Mixed-Signal Simulation Results

21-09-2010

Post Layout including Bondpads simulations. Tools Used : AMS environment (Ultrasim/spectre and ncSim suite).

Final Simulation Results

Pads, Scribe lines

Analog Part

Digital Part

I2C

Comparator DAC

HV DAC

LVDS


Preliminary tests only. 3 samples packaged and tested. I2C communication successful. DAC settings changeable. Analog chain functional.

Test Setup

21-09-2010


Test Results

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1 2 5

15

15.5

16

16.5

17

17.5

18

18.5

Time to Threshold Measurements (Vdd variations)

Time to Threshold_#1_3.0V



No. of Photons

Tim

e t

o T

hre

sho

ld (

ns)

1 2 5

14.5

15

15.5

16

16.5

17

17.5

18

18.5

Time to Threshold Measurements (Vdd = 3.3V)




No. of Photons

Tim

e t

o T

hre

sho

ld (

ns)

Time-to-Threshold

2 photons

1 photon

Time walk=3 ns


Test Results

21-09-2010

1 2 5

15

20

25

30

35

40

Time over Threshold Measurements (Vdd variations)

Time over Threshold_#1_3V

Time over Thresh-old_#1_3.3V


No. of Photons

Tim

e o

ve

r T

hre

sho

ld (

ns)

1 2 5

20

25

30

35

40

45

50

Time over Threshold Measurements (Vdd = 3.3V)




No. of Photons

Tim

e o

ve

r T

hre

sho

ld (

ns)

Time-over-Threshold

2 photons

1 photon


An ASIC to read out the PMT was successfully designed, simulated, fabricated and tested.

Preliminary “Test results” are satisfactory & in line with simulation results and future functionality is being tested.

More intensive tests need to be performed on the ASIC. We aim an engineering run during Q1 of 2011, allowing for a

production ramp-up in Q1 of 2012.

Conclusions & Future

21-09-2010


KM3NeT project team, V. Gromov, Eric Heine, Ruud Kluit, John Hug, Jan-Willem Schmelling, P. Jansweijer, V. Zivkovic, P. Timmer, Joop Rovekamp, ET colleagues at NIKHEF.

Thank You

21-09-2010

References www.km3net.org/CDR/CDR-KM3NeT.pdf www.km3net.org/TDR/Prelim-TDR-KM3NeT.pdf Prof. Sansen “Analog Design Essentials” Springer, 2006. Chang ZY, Sansen W. “Low-noise wide band amplifiers in Bipolar and CMOS

technologies” Springer, 1996. Tajalli et. al. “A Slew Controlled LVDS Output Driver Circuit in 0.18 μm CMOS

Technology”, JSSC, Feb. 2009. www.national.com/LVDS J.Vandenbussche et. al. “A fully integrated Low-Power CMOS Particle Detector Front-

End for space applications”, IEEE Trans. on Nuclear Science, Aug. 1998.

http://www.km3net.org/CDR/CDR-KM3NeT.pdf

http://www.km3net.org/TDR/Prelim-TDR-KM3NeT.pdf

http://www.national.com/LVDS

A Front End ASIC for the read out of the PMT in the KM3NeT Detector

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