All DPLLs Based on Fuzzy PI Control Algorithm Changhong Shan, Zhongze Chen, Yong Li, Hua Yuan

Institute of Electrical Engineering University of South China

Hengyang, China e-mail: shanch801@126.com

AbstractAn all DPLL(All-Digital Phase Locked Loop) based on fuzzy PI control algorithm is proposed in this paper. On analyzing system performance of a second-order PI control based PLL(Phase Locked Loop), the relationship between noise bandwidth with PI control parameters is derived, and fuzzy controller of the system is designed. Under the Matlab/Simulink environment, system-level PLL is directly modeled by using DSP Builder, and then is represented by using VHDL. Software simulation confirms the correctness of the design. The PLL can automatically adjust noise bandwidth according its working state, and it is characteristic of its fast lock speed, small phase jitter, outstanding anti-interference performance and prone to integration and so on.

Keywords- fuzzy PI control; all-digital phase locked loop; noise bandwidth

I. INTRODUCTION With the development of communication and control in

discrete direction, its becoming necessary to make signals be phase locked in digital mode. And digital PLLs have already been widely used in digital communications, radars, radio electronics, instruments, high-speed computer and navigation systems. In traditional DPLLs, a low-pass filter is usually adopted as a loop filter for processing a pulse train. The filter makes a count operation on the phase error pulse produced by its front phase detector, and outputs as control parameters of back-end controlled oscillator[1-4]. However, the method for counting the pulse sequence by the low pass filter is a complex nonlinear process, it is difficult to convert it approximately to linear one, or the design parameters of the PLL can not be determined by using transfer function based analysis method, and thus decoupling control of phase range, speed and stability for phase-locked PLL can not be achieved. PI control algorithm based DPLL overcome the shortcomings by traditional DPLL, and it is characteristic of its simple structure, flexible control, high tracking accuracy and good steady-state performance[5-6]. In practical applications, however, the PLL is always accompanied by noise and interference, and if the noise is strong enough, the working state of the system will be completely destroyed. To improve performance of the PLL on resisting disturbance, the equivalent noise bandwidth of the loop should be limited to a narrow range through proper system design, for the more narrow the equivalent noise bandwidth, the stronger noise inhibition ability the loop owns, and the greater the improvement of signal to noise ratio; but reducing the equivalent noise bandwidth of the loop leads to lowering acquisition performance, reducing the capture bandwidth, and increasing the capture time, which is a contradiction. In a PI control algorithm based DPLL, proportional-integral control parameter is fixed, so the noise

bandwidth remains the same once it be selected, therefore, the performance of this kind of DPLL on disturbance resistance is weak, and dynamic features is bad.

To resolve these problems, we propose a new method for designing all-digital phase-locked loop. In this method, fuzzy control and PI control are combined to adopt a kind of variable bandwidth technology, i.e. at the beginning of capturing signals, a wide noise bandwidth is used, which will facilitate the increase of capture bandwidth, and reduce the capture time; while after the loop is locked, a narrow noise bandwidth is used in order to reduce the phase jitter, and enhance anti-interference ability. In this paper, the performance of DPLLs is analyzed, a design method of fuzzy PI control based DPLL is proposed, implementation of design and system simulation under the MATLAB and by using EDA technologies are given.

II. ANALYSIS OF DPLL SYSTEM PERFORMANCE

A. Performance analysis of second-order PLL based on PI control Model of PI control based second-order DPLL in discrete

domain is shown as Figure 1, and the closed-loop transfer function is as:

1 2 12

1 2 1

( ) ( )( )( ) ( 2) (1 )

outADPLL

ref

z K K z KH zz z K K z K

+ = ==

+ + + 1

where 1K means proportional control parameters, 2K integral control parameters, they have following

relationship with parameters n and : 1

2 22

2 n

n

K TK T

== 2

Where n denotes the system's natural frequency, the damping oefficient, and T the sampling period.

Figure 1 Model of PI control based second-order DPLL in

discrete domain

7150978-1-4244-9439-2/11/$26.00 2011 IEEE

Closed-loop transfer function of second-order analog PLL can also be represented by the standard closed-loop transfer function of second-order system:

2

2 2

( ) 2( )( ) 2

+= =

+ +out n n

APLLin n n

s sH ss s s

The above transfer function of second-order PLL in continuous domain can be transformed into the following discrete domain transfer function by using bilinear transformation method:

( ) ( ) ( )( ) ( ) ( )

2 2 21 2

2 2 21 2

[4 ] 2 [ 4 ]( )

[4 4 ] [2 8] [4 4 ]n n n n n

ADPLLn n n n n

T T T z T T zH z

T T T z T T z

+ + + =

+ + + + + +

4 On comparing equation (1) and (4), we found that the two

expressions are for the same system, and then obtain the expression about parameters 1K and 2K as following:

( )( )

( )

1 2

2

2 2

84 4

44 4

n

n n

n

n n

TKT T

TK

T T

= + += + +

5 B. Performance analysis of fuzzy PI control based DPLL

System architecture of DPLL based on fuzzy PI control is shown as figure 2. The DPLL includes a digital phase detector (DPD), a fuzzy controller, a digital loop filter (DLF) and a numerically controlled oscillator (NCO). In the figure,

)(nrfe represents the input signal, )(nout output signal, )(nerr error signal (including a phase error e and change

rate of phase error 'e ).

Figure 2 System model of second-order DPLL based on

fuzzy PI control

When the PLL begins to work or some external disturbances occur, the phase error e and change rate of the phase error 'e are both high, fuzzy control parameter LB will be increased by the fuzzy controller, and also an increase to the loop noise bandwidth, and thus through PI control the

system dynamic process as well as the process of arriving phase-locked state is sped up; when PLL is locked in a phase steady state, e and 'e are both relatively small, fuzzy control parameter LB will be decreased by the fuzzy controller, and followed by an decrease to the loop noise bandwidth, and through the PI control steady state error is eliminated, while anti-interference ability is enhanced and the phase jitter is reduced.

Noise hemi-bandwidth of the loop is defined as:

( ) 20

LB H j df

= 6 In equation (3), let js = , we obtain frequency

response )( jH of the closed-loop system, with which and from Eq (6) the loop noise bandwidth is represented as:

2(1 4 )8

nLB

= + 7

Under MATLAB, the relationship of n

LB

and can

be obtained according to

841 2+

=

n

LB and shown as curve

in Figure 3. As can be seen from the figure, given a narrow-band Gaussian white noise, LB of the ideal second-order PLL has a unique minimum nLB 5.0min = , when 5.0= holds, and from the point view of noise suppression, the best damping coefficient of the ideal second-order PLL system should be selected as 5.0= . Considering that the transient response of second-order system should not last too long, its best to make the system work in the critical damping state, so we take 707.0= , when

nLB 53.0min = , almost the same with the minimum value. Taken together, the system damping coefficient can be chosen as 707.0= .

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 20

0.10.20.30.40.50.60.70.80.9

11.11.21.31.41.51.61.71.81.9

2

BL/

n

BL/n--

Figure 3 Curve for relationship / ~L nB

7151

Substitute 14

82 +

=

LnB into equation (5) we have:

22222

2

1 )(64)41(32)14(464

TBTBTBK

LL

L

++++=

8

22222

2

2 )(64)41(32)41(4)(256

TBTBTBK

LL

L

++++=

9

From above analysis we have, once and T are chosen, the relationship between LB and 1K also 2K is determined. Therefore, when the loop noise bandwidth

LB changes, the proportional and integral control parameters 1K and 2K would change accordingly, and then through

the digital loop filter the NCO is controlled.

III. DESIGN OF PHASE LOCK SYSTEM

A. Design of Fuzzy Controller

Since the relationship between the error signal and the

loop noise bandwidth is difficult to be accurately modeled, a fuzzy scheme is used [7-9]. Here we adopt a two-input single-output fuzzy controller. Membership functions of input and output variables are all chosen as trigonometric functions, the linguistic variables for the input phase error

e and change rate of phase error '

e are both defined as {PB, PM, PS, ZE, NS, NM, NL}, while output linguistic variables as {ZE, PSS, PS, PSM, PM, PMB, PB, PBB}. Given

e and 'e , the self-tuning of parameter

LB should meet the following rules:

(1) if e and 'e are large, a large LB should be

taken in order to speed up system response; (2) if

e and 'e are medium, an appropriate

LB should be taken so that the system has a small overshoot;

(3) if e and 'e are small, a small LB should be

taken to avoid shock in the vicinity of the equilibrium point, through which the system has good performance on steady-state as well as anti-interference state. According to the above three rules we get a set of fuzzy rules as shown in table 1.

Table 1 Control rules table

LB PB PM PS ZE NS NM NB

PB PBB PB PB PMB PB PB PBB

PM PB PMB PM PSM PM PMB PB

PS PMB PM PS PSS PS PM PMB

ZE PM PS PSS ZE PSS PS PM

NS PMB PM PS PSS PS PM PMB

NM PB PMB PM PSM PM PMB PB

NB PBB PB PB PMB PB PB PB

B. Simulation of the fuzzy PI controller by Using Matlab/Simulink

Structure model of the Fuzzy PI control based PLL is

constructed under MATLAB/Simulink [10]. And simulation result is as Figure 4.

Figure 4 Step response of PI control based PLL

The solid line in Figure 4 means step response curve

of an optimal PLL based on fuzzy PI control, while the dashed

line is step response curve of an optimal PLL based on

conventional PI control. As can be seen from the figure, the

step response of PLL based on conventional PI control has an

overshoot %45% , and response time sTs 175 ; while

step response of PLL based on fuzzy PI control has an

overshoot %18% , and response time sTs 80 . Thus,

PLL based on fuzzy PI control has much better dynamic

performance than that of PLL based on conventional PI

e'

e

7152

control.

IV. DESIGN OF PLL HARDWARE DSP Builder is a set of tools for DSP development

provided by Altera. As a toolbox under Matlab/Simulink, it make the design of complex digital systems be implemented through graphical user interface. As a third-party software of Quartus II and Matlab, DSP Builder provides module named Signal Compiler as interface for Quartus II and Matlab, with this interface module system-level model can

be easily established and then be compiled into VHDL source code. After simulation under Quartus II environment, compiled code can be downloaded to an FPGA chip, which may be our target circuit.

Above mentioned ADPLL can be automatically converted to VHDL code by using DSP Builder, under Quartus we get simulation results of ADPLL based on fuzzy PI control (as Figure 5). The simulation results indicate that when a jump occurs on the frequency of input signal, the system can arrive phase re-locked state in a few clock cycles.

Figure 5: simulation results of ADPLL based on fuzzy PI control

V. CONCLUSIONS This paper presents a fuzzy PI control algorithm based

DPLL, including performance analysis and design methods of this kind of DPLL. Under Matlab/ Simulink environment, system-level model is also established by using DSP Builder, modeling and simulation results have been obtained under Quartus . Software simulation confirms the correctness and feasibility of the design. The PLL can automatically adjust the noise bandwidth according to the system working conditions, through which overcomes the contradiction between increasing the speed of PLL for arriving phase locked state and enhancing system performance on anti-Interference, and it is characterized small phase jitter, outstanding anti-Interference performance and prone to integration. Furthermore, it can be as modules embedded within the SOC, and owns a wide range of applications.

REFERENCES [1] Huachun Hu, Yu Hu. Principle and applications of digital phase locked

loop [M]. Shanghai: Shanghai Science and Technology Press, 1990 (In Chinese).

[2] Juesheng Zhang. Phase Lock Technology [M]. Xi'an: Xidian University Press, 1994 (In Chinese).

[3] Changhong Shan, XieYuan Meng. Design of DPLL based on FPGA [J]. Electronic Technology Application, 2001 (9): 58 ~ 60 (In Chinese).

[4] Wenli Wang, Zhang Xia. Design of DPLL based on FPGA[J]. Electronic Design Engineering, 2009 17 (1): 39 ~ 43 (In Chinese).

[5] Hao Pang, sky ZU, Zan-ji Wang. A new all-digital phase-locked loop [J]. CSEE, 2003,23 (2) :37-41 (In Chinese).

[6] Changhong Shan, Yan Wang, Chen Wen-Guang, Zhongze Chen. Design and implementation of FPGA-based high-order ADPLL[J]. Circuits and Systems .2005,10 (3): 76 ~ 79 (In Chinese).

[7] Yao-nan Wang, Wei SUN. Intelligent Control Theory and Applications[M]. Machinery Industry Press, 2008 (In Chinese).

[8] Xue-Yi Qi, Yijiang Cai, Jiang Wu. Simulation of Air Conditioner System with Variable Air Volume Based on Fuzzy PID Control[J]. Jiangsu University (Natural Science), 2005,26 (4) :364-368 (In Chinese).

[9] J. Kim, M.A. Horowitz, and G. Wei, Design of CMOS adaptive-bandwidth PLL/DLLs: A general approach, IEEE Trans.CIircuits and SystemsII: Analogand Digital Signal Processing,Vol. 50, pp. 860-869, Nov. 2003.

[10] Jinkun Liu. Advanced PID control and simulation under Matlab[M]. Electronic Industry Press, 2003 (In Chinese).

7153

/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 200 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages false /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 400 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 600 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile (None) /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

/CreateJDFFile false /Description >>> setdistillerparams> setpagedevice