A DRY ELECTRODE LOW POWER

CMOS EEG ACQUISITION SOC FOR

SEIZURE DETECTION

TEAM 6: MATTHIEU DURBEC, VALENTIN BERANGER,

KARIM ELOUELDRHIRI

ECE 6414 – SPRING 2017

• Project motivation

• Design overview

• Body-Electrode Interface

• Voltage references

• Chopper Stabilized LNA

• Low Pass filter

• ADC Driver

• SAR-ADC

• Conclusion

OUTLINE

Epilepsy neurological disorder Abnormal firing in a group of neurons Clinical onset:

Loss of coherence/cognition Loss of motor control Convulsions

Objective: sense these signals and establish correlation with clinical onset

Use of machine learning techniques and training to patient-specific data

PROJECT MOTIVATION

Multi Channel EEG Acquisition system Wireless low power chip Digitized EEG signals transmitted for

processing Machine learning algorithm for processing

channel signals IC design specifications

DESIGN OVERVIEW

Dry-electrode model: Gel free solution Increased impedance in the skin-electrode interface

Circuit model: Resistor : body Resistor & Capacitance: Stratum Corneum

Electrode offset voltage (EOV): 10-100mV EEG Signals: 10-50 μV EEG frequency range: 0.5 - 100 Hz

BODY-ELECTRODE INTERFACE

A chopper stabilized amplifier system consists of modulating and demodulating carriers with period T= 1/fchop, where fchop is the chopper frequency.

DC servo loop uses for high pass filter and cancel residual offset

Chopping reduces the DC input impedance of the sensing front-end. The low input impedance can result in attenuation of the weak input signals and degradation in noise performance

Chopper-stabilized LNA

Chopping -> reduces the flicker noise

Upmodulated flicker noise and offset show up as ripples at the output of the amplifier

Sol :a parallel-RC impedance is added immediately after the 1st stage.

A fully differential chopper amplifier

The EEG signal bandwidth is in the range 0.5-100 Hz

Pseudo-resistor larger than 100 GΩ in the feedback loop. Proccess variations (factor of 100).

Duty-cycled resistors to enable high linearity and reliability

DC servo loop

Chopping reduces the DC input impedance of the sensing front-end

-> Impedance boosting.

Auxialiary path

Impedance boosting

The auxiliary-path used charges the input caps Cin at the beginning of every chopping phase using aux-buffers reducing the charge provided by the input voltage, thus boosting Zin.

Impedance boosting

Vin provides zero charge ->

Problem : Amplification of aux-buffer offset and flicker noise

Impedance boosting

Sol: Voff is up-modulated to fc/4 by using mixers M1 and M2

Voff creates a benign ripple instead of a DC offset.

Storage capacitors Caux=8pF assist the aux-buffers at the beginning of the pre-charge phase.

Higher input impedance without increasing power consumption

Impedance boosting

Results

Results

Metrics Target SpecificationVoltage Supply 3.1V

Power consumption 67µWGain 43.5dBBW 0.5Hz-10kHz

CMRR 55dBInput impedance 8GΩ @1Hz

Input-referred noise 0.75µVRMS (1-200Hz)5.27µVRMS(200-10kHz)

Ripple rejection yesProcess 0.6 um

Power supply: 3.7V Rechargeable Polymer Li-Ion

battery Tenergy model PL 401225

Bandgap Reference Circuit: Constant Vref independent of

temperature swings CTAT, PTAT and Start-up circuit

Generated Vref: 3.14V at Vdd

VOLTAGE REFERENCES: BGR

VOLTAGE REFERENCES: BGR

Voltage Regulator: Ensures constant voltage across the

system Negative feedback control loop Supplies reference voltage to the

entire chip Output of the regulator 95% the

voltage reference generated by BGR

VOLTAGE REFERENCES: REGULATOR

VOLTAGE REFERENCES: REGULATOR

VOLTAGE REFERENCES: REGULATOR

Fully differential topology with common mode feedback and gain enhancement

Provide frequency cut off for EEG signals and gain

Low pass filter specifications

LOW PASS FILTER

LOW PASS FILTER

Drive capacitance sample & hold of the ADC

Fully differential amplifier with common mode feedback and gain enhancement

Additional gain to reach the ADC dynamic range

ADC Driver specifications

ADC DRIVER

ADC DRIVER

ADC DRIVER

12-bit successive approximation register converter

6-bit main-DAC and 6-bit sub-DAC architecture, both implemented as passive charge-redistribution capacitor arrays, providing an inherent sample and hold function

Energy per conversion down to very low speeds (i.e., around 600 S/s)

SAR ADC Design

Three steps: purging, auto-zeroing and sampling

Management of clocking is crucial in this design

Use of a consequent number of switches

SAR ADC Operation Principle

Charge scaling DAC

Unit capacitance - 500fF

Importance of transmission gate

Digital to Analog Converter (DAC)

Successive Approximation Register

Specifications

Comparison with State of the Art

CONCLUSION

[1] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag and A P. Chandrakasan, “A Micro Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System,” IEEE journal of solid-state circuits, vol.45, no. 4, April 2010.

[2] S. Lim, C. Seok, H. Kim, H. Song and H. Ko, “A Fully Integrated EEG Analog Front-End IC with Capacitive Input Impedance Boosting Loop”, IEEE Custom Integrated Circuits Conference (CICC), 2014.

[3] YM. Chi, T-P Jung, G Cauwenberghs, “Dry-contact and Noncontact Biopotential Electrodes: Methodological Review,” IEEE Reviews in Biomedical Engineering, vol. 3, 2010.

[4] A. Bragin I. Fried R. J. Staba, C. L.Wilson and Jr J. Engel, “Quantitative analysis of high-frequency oscillations (80500 hz) recorded in human epileptic hippocampus and entorhinal cortex,” J. Neurophysiol., vol. 88, pp. 1743 – 1752, 10 2002.

[5] F. Shahrokhi, K. Abdelhalim, D. Serletis, P.L. Carlen, and R. Genov, “The 128-channel fully differential digital integrated neural recording and stimulation interface,” Biomedical Circuits and Systems, IEEE Transactions on, vol. 4, no. 3, pp. 149–161, June 2010.

[6] N.Verma and A.P.Chandrakasan, “An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes,” IEEE J. Solid- State Circuits, vol. 42, no. 6, pp. 1196–1205, Jun. 2007.

[7] G. Promitzer, “12-bit low-power fully differential noncalibrating successive approximation ADC with 1 MS/s,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138–1143, Jul. 2001.

[8] T. Denison, et al., “A 2 μW 100 nV/rtHz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,” IEEE J.Solid-State Circuits, vol. 42, no. 12, pp. 2934–2945, Dec. 2007.

[9] R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, 3rd Edition, IEEE Press Series on Microelectronic Systems, 2010.

[10] Q. Fan, F. Sebastiano, J. H. Huijsing, and K. A. A. Makinwa, , “A 1.8 μW60 nV/√Hz capacitively-coupled chopper instrumentation amplifier in 65 nm CMOS for wireless sensor nodes,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1534–1543, Jul. 2011.

[11] J. Xu et al., “A 160 μW 8-channel active electrode system for EEG monitoring,” IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 6, pp. 555–567, Dec. 2011.

[12] H. Chandrakumar et.al, “A Simple Area-Efficient Ripple-Rejection Technique for Chopped Biosignal Amplifiers,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 62, no. 2, pp.189-193, Feb. 2015.

[13] H. Chandrakumar, et al., “A 2μW 40mVpp Linear-Input-Range Chopper-Stabilized Bio-Signal Amplifier with Boosted Input Impedance of 300MΩ and Electrode-Offset Filtering,” ISSCC, pp. 96-97, Feb. 2016.

[14] H. Chandrakumar, et al., “2.8μW 80mVpp-Linear-Input-Range 1.6GΩ-Input Impedance Bio-Signal Chopper Amplifier Tolerant to Common-Mode Interference up to 650mVpp” IEEE International Solid-State Circuits Conference (ISSCC) 2017

REFERENCES

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