A Control Strategy for Parallel Operation of Single-Phase Voltage Source Inverters ... em...

2194 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 6, JUNE 2013

A Control Strategy for Parallel Operation ofSingle-Phase Voltage Source Inverters: Analysis,

Design and Experimental ResultsTelles B. Lazzarin, Member, IEEE, Guilherme A. T. Bauer, and Ivo Barbi, Fellow, IEEE

Abstract—This paper describes a theoretical and experimentalstudy on a control strategy for the parallel operation of single-phase voltage source inverters (VSI), to be applied to uninterrupt-ible power supply. The control system for each inverter consistsof two main loops, which both use instantaneous values. The first(parallelism control) employs the feedback of the inductor currentfrom the output filter to modify the input voltage of the samefilter and, therefore, to control the power flow of each inverterto the load. Additionally, the second loop (voltage control) isresponsible for controlling the output voltage of the LC filter,which coincides with the output voltage of the VSI. Due to the factthat there is no exchange of information among the VSIs regardingtheir operation points, it is easier to obtain redundant systems.Furthermore, the connection (or disconnection) of inverters in aparallel arrangement is carried out directly, without connectionimpedance, and can occur at any operation point of the system.The proposed control strategy ensures the proper sharing of theload current and avoids current circulation among the invertersduring transient and steady-state operation. Moreover, its designand implementation are very simple. The control technique wasverified through experimental results with a maximum load of 10kVA supplied by three parallel-connected inverters.

Index Terms—Control strategy, parallelism, single-phase, unin-terruptible power supply (UPS), voltage source inverters (VSIs).

NOMENCLATURE

C Capacitance of the LC filter. [See Fig. 5].Cv Transference function of the voltage controller.Gi Transfer function of the input, Vpc, to the output IL.Gv Transfer function of the input, IL, to the output V0.Gv2 Transfer function of the input, Vvc, to the output V0.IL Inductor current L. [See Fig. 5].ILo Load current. [See Fig. 5].Kcv Voltage controller gain.KGv2 Static gain of Gv2.KIL Gain of the parallelism controller. [See Fig. 5].

Manuscript received February 22, 2011; revised November 18, 2011 andFebruary 15, 2012; accepted March 22, 2012. Date of publication April 6, 2012;date of current version February 6, 2013.

T. B. Lazzarin and I. Barbi are with the Power Electronics Institute(INEP), Department of the Electrical Engineering (EEL), Federal Univer-sity of Santa Catarina (UFSC), 88040-970 Florianópolis-SC, Brazil (e-mail:[email protected]; [email protected]; www.inep.ufsc.br).

G. A. T. Bauer was with the INEP, EEL, UFSC, 88040-970 Florianópolis-SC,Brazil. He is currently with Companhia Estadual de Distribuição de EnergiaElétrica (CEEE-D), 91410-400 Porto Alegre-RS, Brazil (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2012.2193856

Kinv Static gain of the inverter and the PWM modulator.Kv Voltage sensor gain.L Inductance of the LC filter. [See Fig. 5].Le External inductance added for the LC filter.Ll Leakage inductance of transformer. [Seen from high-

voltage side].Lm Magnetizing inductance of transformer. [Seen from

high-voltage side].n Transformer ratio. [See Fig. 5].p1 Pole 1 of the voltage controller.Px_y Active power flow from “x” to “y”.Qx_y Reactive power flow from “x” to “y.”Ro Resistive load.V0 Output voltage of the inverter. [See Fig. 5].VAB Voltage between points A–B of the inverter. [See

Fig. 5].Vac Electric utility system voltage.Vdc dc link voltage.Vpc Parallelism controller signal. [See Fig. 5].Vvc Voltage controller signal. [See Fig. 5].Vi IL current feedback signal. [See Fig. 5].Vp Peak value of PWM carrier.Vref Voltage reference. [See Fig. 5].XLX Impedance of L inductor in the inverter “x.”z1 Zero 1 of the voltage controller.z2 Zero 2 of the voltage controller.Zo Load.θx_y Phase between the voltages “x” and “y.”ξGv2 Damping of Gv2.

I. INTRODUCTION

THE parallel operation of voltage source inverters (VSIs)is a configuration that allows the processed load power

to be shared among the converters, creating redundant systemsand making the power expansion flexible. These characteristicshave led to the use of this configuration in an uninterruptiblepower supply (UPS), mainly to build a redundant and modularsystem. In applications for UPS, the inverters must operatein parallel independently of each other, which requires anappropriate control strategy that ensures the system operation.

In the literature, there are many publications based on thefollowing techniques: master-slave [1]–[3], central mode con-trol [4]–[6], distributed control [7]–[12] and without controlinterconnection [13]–[24]. The master-slave and central mode

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LAZZARIN et al.: CONTROL STRATEGY FOR PARALLEL OPERATION OF SINGLE-PHASE VOLTAGE SOURCE INVERTERS 2195

control techniques offer an effective current-sharing control,but they do not allow true redundancy because a failure inthe master or in the central unit would shut down the wholesystem. In distributed control, each inverter has its own controlsystem for parallel operation, improving the redundancy andmodularity of the system in comparison to the two previoustechniques. In this strategy, all units are connected througha communication bus, which is employed for data exchangeamong the inverters. Therefore, the control system of eachinverter knows the operation point of all converters, and it usesthis information to determine its operation point. It then sendsthis information to other units. However, a failure in the data buscan cause the system to shutdown. The strategy that gives trueredundancy, in which the inverters are completely independentof each other, is without control interconnection. It is basedon frequency and voltage droop principles of power systems,and the control is carried out using average power values. Thisstrategy is difficult to implement due to the calculation of theaverage powers. Furthermore, it has a slow dynamic responseand admits a larger error in the distribution of power betweenthe inverters than the previous techniques. However, studiesreported in [17], [19], [22] demonstrate strategies to minimizethese disadvantages.

Taking these facts into account, it can be to conclude thatthere is still no standard solution in the literature for the paralleloperation of VSIs applied to UPS. In this context, this paperproposes a control strategy that utilizes the principles of distrib-uted and droop controls, resulting in a new strategy which canbe classified as an evolution of the classic distributed control.The proposed strategy has been classified as distributed controlbecause it has a signal common to all VSIs, which definesthe amplitude, frequency, and phase of the reference voltagesin the inverters. However, the VSIs do not need to exchangeinformation on their operation points. One unit works in theparallelism with no knowledge of how many VSIs are con-nected in parallel and whether they are operating. The proposedparallelism control is carried out in each inverter employingonly internal information on its own VSI, and it is based onthe instantaneous droop control. All of these characteristics arestudied in the following sections.

II. CONCEPTION OF THE CONTROL STRATEGY

A. Review

Before addressing the proposed control strategy, it is interest-ing to review some features of VSI under study. In this regard,Fig. 1 shows the typical structure of a VSI employed in theoutput stage of UPSs. The power circuit of the inverter in Fig. 1is composed of a pulse width modulation (PWM) inverter andan LC filter. The control system is designed using instantaneousvalue, which pursues a sinusoidal reference (Vref ) and regu-lates the output voltage V0 (voltage after of LC filter) correctly.Fig. 1 also shows the voltage VAB of the VSI, which is theoutput voltage of the PWM inverter (input voltage of LC filter).It is well-known that the fundamental component of voltageVAB is proportional to the control signal Vpc applied to thePWM modulator. Following some considerations, the power

Fig. 1. Basic circuit of a VSI employed in UPS.

Fig. 2. Equivalent circuit which represents the power stage and the PWMmodulator of a VSI.

stage and the PWM modulator of the VSI shown in Fig. 1 can berepresented by the equivalent circuit in Fig. 2. In this circuit, thePWM inverter and PWM modulator are simplified for a voltagesource (VAB) controlled through control signal Vpc. This briefreview and the definitions shown will be of assistance in thefollowing sections.

B. Principles of the Control Strategy

The purpose of this study is to implement the parallel connec-tion of VSIs as shown in Fig. 1 with no impedance connection.Therefore, the equivalent power circuit of “N” inverters inparallel connection can be presented as shown in Fig. 3. In thisconfiguration, the output voltages V0 of all inverters are directlyassociated, and, consequently, they become equal. Thus, thedifferences between in the voltages of the VSIs are seen in thevoltage before the LC filter (VAB) of each inverter.

From an analysis of the circuit in Fig. 3, the active andreactive power flow between two VSIs (1 and 2) are given by

PV AB2_V AB1

=|VAB2| · |VAB1| · sin(θV AB2_V AB1)

XL1 + XL2(1)

QV AB2_V AB1

=|VAB2|2 − |VAB2| · |VAB1| · cos(θV AB2_V AB1)

XL1 + XL2(2)

and these equations show that, if the magnitude and the phaseof the VAB voltages are different, power flow among the VSIscan occur.


Fig. 3. Equivalent circuit of power stage of an arrangement of “N” VSIsparallel connected with no connection impedance.

The active and reactive power flow from one inverter (exam-ple: VSI 1) to a common ac bus are given by

PV AB1_V 0 =|VAB1| · |V0| · sin(θV AB1_V 0)

XL1(3)

QV AB1_V 0 =|V0|2 − |VAB1| · |V0| · cos(θV AB1_V 0)

XL1. (4)

It can be observed that the magnitude and the phase of theVAB voltage have an effect on the power flows supplied by theinverter to the load.

According to (1)–(4), if a control strategy acts on the VAB

voltages properly, an equilibrium of the VAB voltages can beachieved, and, thus, this strategy will result in adequate sharingof the load power and avoid the power flow between the invert-ers. Based on this principle, the parallelism control proposed inthis paper acts on the VAB voltage in each inverter with the aimof ensuring adequate parallel operation of the VSIs.

Thus, in each VSI, a control loop is added, called parallelismcontrol, which is placed in cascade with the voltage controllerCv , as shown in Fig. 4. This second loop enables the inverter towork in parallel. This new control modifies the output signalof the voltage controller, Vvc, with the aim of changing theVpc signal applied in the PWM modulator and, consequently,altering the VAB voltage of the VSI [25]. The parallelismcontrol employs the feedback of inductor current L from theLC filter, called Vi, to modify the Vvc signal. Therefore, eachVSI utilizes only the feedback of its own inductor current toensure its proper parallel operation.

A relevant point is that the proposed strategy is based on asingle reference voltage (Vref ) for all VSIs, thus the outputvoltages of all inverters have only small deviations, whichare caused by parametric variations in the control and power

Fig. 4. Circuit of a VSI based on the proposed control strategy.

components of the inverters. Therefore, the parallelism controlhas the function of equalizing these small deviations to ensurepower sharing among the inverters.

It is important to note that the proposed control for theparallel operation of VSIs based on the feedback of the induc-tor current differs from the current control loop in multiloopcontrol [26], [27]. The current loop employed in multiloopcontrol is placed inside the voltage control loop to improve thedynamics and stability of the isolated VSI.

C. Proposed Control Strategy

The principles described above resulted in the proposed con-trol strategy for parallel-connected single-phase VSIs shownin Fig. 5. Each VSI is called a module, and in module 1 thecomplete structure, with power and control circuits, of one VSIis presented. The other modules are identical to module 1 andare shown as a block in Fig. 5.

The power circuit in module 1 is composed of an ac-dcconverter, a full-bridge dc-ac inverter, an isolator transformer,and an LC filter. This is the typical structure of a VSI employedin UPS.

The control system shown in module 1 is composed ofvoltage and parallelism controls. The two loops are designedusing instantaneous values and were introduced in the previoussections. The voltage control is responsible for controlling theoutput voltage of the LC filter, which coincides with the outputvoltage of the VSI and the connection point. The parallelismcontrol employs the feedback of the inductor current from theoutput filter to modify the input voltage of the same filter and,therefore, to control the power flow of each inverter to theload. This proposed strategy has the basic principles of droopcontrol, because it decreases the VAB voltage with increasinginductor current (IL). However, in this case, the droop controlwas carried out using instantaneous values, offering a dynamicresponse appropriate for parallelism control. Furthermore, theproposed strategy does not modify the voltage reference Vref ,as in the classic droop control. This is a great advantage becausethe control does not change the synchronism with the voltagereference and keeps the output voltage V0 imposed only by thevoltage loop.


Fig. 5. Power and control scheme of the VSIs connected in parallel.

Considering that only internal variables are employed in theparallelism control, such modules are independent structures.This characteristic makes it easier to connect and disconnect amodule to and from the common ac bus.

Nevertheless, before connecting the VSIs in parallel, theiroutput voltages need to be equal (same amplitude, frequency,and phase). This is achieved by imposing the same referencevoltage signal on all inverters through the communication bus,called the “voltage reference bus,” which transmits the voltagereference signal (Vref ) to the VSIs, as shown in Fig. 5. Thissignal originates from an independent and redundant circuit,which produces the voltage reference and synchronizes withthe electrical grid. This circuit sends an analog signal througha “voltage reference bus” to the inverters. However, the signalcould also be of another type, for example, a digital signal witha communication protocol. This bus is easy to build and can begenerated by an independent circuit, or one inverter or even allinverters.

Due to the presence of a communication bus for the VSIs,the proposed control strategy is classified as distributed control.However, in contrast to traditional distributed control, in thiscase, each VSI only needs to receive the Vref signal in orderto be connected in parallel. There is no exchange of informa-tion among the VSIs regarding their operation points, and theinformation flow occurs only in one direction, from the voltagereference bus to the VSI.

III. ANALYTICAL STUDY ON THE CONTROL STRATEGY

OF A SINGLE INVERTER FEEDING A RESISTIVE LOAD

As the modules shown in Fig. 5 are independent of eachother, the study of the proposed control strategy can be carriedout by analyzing the behavior of only one inverter. In each VSI,the proposed strategy has two control loops. The first loop con-trols the output voltage of the inverter (V0) and is a well-knownstrategy. The second loop is responsible for the parallelismcontrol and is the focus of this study. The following analysisconsiders the inverter feeding a resistive load to facilitate anunderstanding of the parallelism control.

A. Analytical Study of the Parallelism Control

In the inverter control system, shown in module 1 of Fig. 5,the parallelism loop obeys the control law

Vpc(t) = Vvc(t) − Vi(t). (5)

The parallelism control consists of subtracting a signal propor-tional to the inductor L current (Vi) from the output signal ofthe voltage control (Vvc). The signal Vi is given by

Vi(t) = IL(t) · KIL (6)

where KIL is the gain in the IL current feedback.


Fig. 6. Block diagram of voltage and parallelism loops for a single VSI.

Replacing (6) in (5), obtains

Vpc(t) = Vvc(t) − IL(t) · KIL. (7)

The Vpc signal is applied in the PWM modulator that gener-ates the VAB voltage. It is given by

VAB(t) = Kinv · Vpc(t) (8)

where Kinv is the static gain of the inverter and the PWMmodulator.

Since the Kinv gain is provided by

Kinv =Vdc

Vp(9)

where Vdc is the dc link voltage and Vp is the peak value of thePWM carrier.

Replacing (7) in (8), obtains

VAB(t) = Kinv · Vvc(t) − Kinv · KIL · IL(t) (10)

which it shows that instantaneous variations in IL cause instan-taneous variations in VAB . Equation (10) also demonstrates thevoltage droop caused by parallelism control in the VAB voltageas a function of the KIL gain. Therefore, this control can beunderstood as virtual resistance that is placed in series with theL inductor, and, thus, the greater the virtual resistance (KIL

gain), the higher the voltage droop with increasing inductorcurrent. Based on this principle, the parallelism control consistsof the proper adjustment of the KIL gain.

B. Model of One VSI With the Proposed Control Strategy

This section studies the characteristics introduced in the VSIsby control parallelism. For this, analysis of the complete controlsystem of one inverter is performed considering that it is feed-ing a load resistive. Fig. 6 shows the block diagram of the volt-age and the parallelism loops for one inverter. As the two loopshave similar dynamic responses, it is not possible to uncouplethem. Thus, the model of the inverter, which is used in the volt-age loop design, must take into account the parallelism control.

The model of the inverter, of the input, Vpc, to output, IL,defined as Gi (s), is given by

IL(s)Vpc(s)

= Gi(s) =

(s · C + 1

Ro

)· n · Kinv

s2 · L · C + s(

LRo

)+ 1

. (11)

The closed-loop transfer function of the parallelism loop,ICLTF (s), is shown in Fig. 6 and is considered without sim-plification in the model of the inverter for the voltage loop.

The transfer function

V0(s)IL(s)

= Gv(s) =1

s · C + 1Ro

(12)

defines the relation between the input IL and output V0. Themodel of the VSI, of the input, Vvc signal control, to the output,V0 voltage, considering the inverter feeding a resistive load, isrepresented by the open-loop transfer function (OLTF )Gv2(s),that is given by (see (13) at the bottom of the page).

On obtaining Gv2(s), it is possible to design Cv(s). Thevoltage controller selected was the

Cv(s) = Kcv · (s + z1) · (s + z2)(s + p1) · s

(14)

that is the classic PID applied in inverters. The block diagramof Fig. 6 shows in detail how all the transfer functions arerelated.

C. Principle Operation of the Proposed Parallelism Controlin Each VSI

Equation (13) shows that the parallelism control changesthe position of the poles of the voltage loop transfer functionaccording to the KIL gain value. Thus, the adjustment of theparallelism control changes the static and dynamic characteris-tics of the voltage inverter. This is verified in the static gain

KGv2 =n · Kinv

1 + KIL

Ro· n · Kinv

(15)

V0(s)Vvc(s)

= Gv2(s) =n · Kinv[

s2 · L · C + s ·(

LRo

+ KIL · C · n · Kinv

)+

(1 + KIL

Ro· n · Kinv

)] (13)


Fig. 7. Step response of Gv2 for low load (Ro = 100 Ω) with the parallelismcontrol enabled (KIL = 0.01) and disabled (KIL = 0).

TABLE IVSI SPECIFICATION OF 5 kVA

and the damping

ξGv2 =L

Ro+ KIL · n · Kinv · C (16)

of Gv2.Equation (15) shows that the parallelism control reduces the

static gain of the inverter when the KIL gain increases. More-over, (15) shows that the static gain decreases in proportion tothe load increase (Ro load reduction). Therefore, in nonloadoperation, the static gain is equal to Kinv , in other words, it isnot influenced by the parallelism control.

Equation (16) proves that the parallelism control alsochanges the dynamic response of the inverter, more specifically,the damping. In this case, the parallelism control adds theKIL · n · Kinv · C term to the damping equation. This term isnot dependent on Ro (load), and it is proportional to the KIL

gain. These characteristics ensure an increase in the inverterdamping, even in nonload operation.

The presence of the parallelism control in the VSI causesthe effects shown in the simulations of Figs. 7 and 8, whichillustrate the step response of the transfer function Gv2 indifferent situations. The parameters used to simulate the figuresare shown in Table I.

Fig. 7 shows low load situations (Ro = 100 Ω). The dynamicand static responses of Gv2 are compared in two cases: onewith the parallelism control enabled (KIL = 0.01) and anotherwith the parallelism control disabled (KIL = 0). The resultsobtained with the parallelism control enabled show lower over-shoot, setting time, and oscillations, and the steady state isachieved faster, these being typical characteristics of a damping

Fig. 8. Step response of Gv2 for nominal load (Ro = 10 Ω) with theparallelism control enabled (KIL = 0.01) and disabled (KIL = 0).

Fig. 9. Bode magnitude diagrams of Gv2 with different Ro (loads) and KIL

values.

increase. However, the V0 values in steady state were similarfor the two simulations.

Fig. 8 presents situations under nominal load (Ro = 10 Ω).The transient responses show that the case with the parallelismcontrol enabled again had overshoot and setting times lowerthan those of the case with the parallelism control disabled.As the load becomes greater, an interesting particularity isobserved in steady state, the case with the parallelism controlenabled presents a lower V0 value than the case where theparallelism loop is not present. This is because the parallelismcontrol based on current feedback reduces the inverter staticgain, as shown in (15).

Plotting the Bode diagrams of the transfer function Gv2 forthe same conditions presented in Figs. 7 and 8, the resultsfor magnitude (Fig. 9) and phase (Fig. 10) are obtained. Onanalyzing Curves A and C of Fig. 9, cases of low load, it canbe observed that the parallelism control enabled in Curve Creduces the gain in the resonance frequency area. Curves B andD of Fig. 9 show that, under nominal load, the inverter with theparallelism control enabled (Curve D) leads to an improvement


Fig. 10. Bode phase diagrams of Gv2 with different Ro (loads) and KIL

values.

in the damping of the resonance frequency and, also, there is adecrease in the gain for low frequencies.

The curves in Fig. 10 show that the presence of the currentfeedback also changes the phase diagram, which can improvethe phase margin of Gv2 and, as a consequence, its stability.

The characteristics introduced in the VSI with the parallelismcontrol loop are very important in terms of its parallel operation.The inverter damping increase allows the parallel connection ofinverters at any load level, with a smooth transient response inthe voltage output. The decrease in the static gain in proportionto the increase in the supplied load ensures the appropriate loadsharing among the inverters. In a situation with two or moreinverters connected in parallel, if there is a current disequilib-rium among them, the inverter that supplies the greatest currenthas a greater reduction in its static gain, and, as a consequence,the current supplied by this inverter will be decreased. Thus,the system achieves a working point according to the KIL

gain, which ensures adequate current load sharing among theinverters. Furthermore, correct adjustment of the KIL gain alsoallows inverters to be connected with different power levelsin parallel, ensuring that each one supplies the current to theload in proportion to its nominal power. Another relevant pointto note is that the parallelism control based on instantaneousvariables ensures a fast dynamic response, which is necessaryfor the parallel operation of VSIs.

IV. ANALYSIS OF TWO PARALLEL-CONNECTED

INVERTERS

In order to expand the study of the proposed control strat-egy, the arrangement of Fig. 5 with two parallel-connectedVSIs was analyzed. The steady-state analysis of the parallel-connected inverters proposed in [25] was employed to obtainthe steady-state model of the system. This methodology definesvoltage and current equations for each inverter in relationto the components of all VSI. Thus, the model allows thestudy of the distribution of power, sharing, and circulation ofcurrents among inverters in the case of parametric variation ofthe components, load variations, and controller modifications.Therefore, it can be used to find the appropriate value for the

Fig. 11. Magnitude of IL1 and IL2 currents of two parallel-connectedinverters, under resistive load.

Fig. 12. Phase of IL1 and IL2 currents of two parallel-connected inverters,under resistive load.

KIL gain, at which the system works properly. The modelwas applied to analyze two parallel-connected VSI with theparameters provided in Table I. A parametric variation of 1%was considered in the voltage sensor and 1% in the adjust-ment of the voltage controller, in order to cause deviationsin the output voltages of VSIs. A 5-kW resistive load wasconsidered.

Figs. 11 and 12 show the behavior of the IL1 and IL2

currents, in terms of changes in the KIL gains of the par-allelism controls, of the two parallel inverters. On analyzingthese figures, it can be noted that when the KIL gain is small,large imbalances in the currents appear. Furthermore, the IL2

current has a lag of 180◦ (Fig. 12), and thus this inverter isconsuming power. In this situation, the parallelism control doesnot have a good performance. On increasing the KIL gain,the parallelism control performance becomes more significant,and adequate equilibrium between the currents is obtained, asshown in Figs. 11 and 12.

Fig. 13 shows the behavior of the VAB1 and VAB2 voltagemagnitudes. With an increase in the KIL gains, the values of thevoltage magnitude become similar. The difference in voltagemagnitudes is the main cause of reactive power flow betweeninverters. Therefore, when the VAB voltage magnitudes areclose, the lag between the IL1 and IL2 currents decreases, ascan be seen in Figs. 12 and 13.

Fig. 14 demonstrates that an increase in the KIL gainsreduces the phase displacement between the VAB voltages.This phase displacement is the main cause of the active powerflow between the inverters. Thus, when the phase displacement


Fig. 13. Magnitude of VAB1 and VAB2 voltages of two parallel-connectedinverters, under resistive load.

Fig. 14. Phase of VAB1 and VAB2 voltages of two parallel-connectedinverters, under resistive load.

Fig. 15. Photograph of the prototype with three 5-kVA inverters connected inparallel.

between VAB voltages is eliminated in Fig. 14, the balance ofthe current magnitudes in Fig. 11 is obtained.

The analysis shown in Figs. 11–14 demonstrate the principlesof the proposed strategy: the proper adjustment of the paral-lelism control (KIL gain) changes the VAB voltages of VSIs ina way that ensures the sharing of load current between them.

V. SIMULATION AND EXPERIMENTAL RESULTS

A prototype was implemented to verify the control strat-egy, with three inverters of 5 kVA (modules 1, 2, and 3)and one inverter of 2.5 kVA (module 4). The photographin Fig. 15 shows the prototype with modules 1, 2, and 3.

TABLE IIVSI SPECIFICATION OF 2.5 kVA

Fig. 16. IL1, IL2, and IL3 under frequent load changes.

Tables I and II provide the main specifications for the designof the VSIs. In the inverter control system, analog circuits wereemployed. The PWM modulator was digitally implementedwith a PIC18F2331 microcontroller. For the power circuit, oneSemikron module 50B6U+SKS B2CI10V6 was used, and theswitching frequency was 10 kHz.

The proposed control strategy has been extensively tested insimulation and prototype approaches. Tests to verify the paralleloperation of VSIs in steady state and during disturbances suchas frequent load changes, a fault in the electrical grid, andconnection/disconnection of inverters were carried out.

In order to understand the tests, the operation criteria for theproposed control strategy are described as follows.

• Only one VSI will connect to the system (parallelism)after reading the voltage reference and will supply a stableoutput voltage;

• If there is any problem in the VSI, it must be disconnectedfrom the system;

• The voltage reference signal must be normally maintainedduring a fault in the electrical grid.

Three inverters connected in parallel were simulated underfrequent load changes. The simulation results in Fig. 16 showthat during changes from 0% to 100% load, and vice versa,the inductor currents of the VSIs have a fast response, quicklyfind a new steady-state operation point, and remain balanced.In steady state (under nonload and under resistive load), thecurrents are balanced.


Fig. 17. IL1 and IL2 (20 A/div., 2 ms/div.) and V0 (100 V/div., 2 ms/div.)under resistive load.

Fig. 18. IL1 and IL2 (10 A/div., 2 ms/div.) and V0 (100 V/div., 2 ms/div.)under inductive load.

The prototype was tested with two and three inverters con-nected in parallel, and the maximum load supplied was 10 kVA,since an N + 1 redundant configuration was designed. Theexperimental results in Figs. 17 and 18 were obtained withthe modules 1 and 2 in parallel. The experimental results inFigs. 19–22 were obtained employing modules 1, 2, and 3.Fig. 23 shows the results obtained with modules 1, 2, and 4.

Fig. 17 shows the voltage output and the inductor currentsof the two inverters with a 5-kW resistive load. The currentsare balanced, with around 14 Arms in each unit. The inductorcurrents have a low distortion, which expresses a low powerflow between the inverters. This power is low, does not damagethe system operation, and is minimized by the parallelismcontrol. The output voltage is 217.6 Vrms, which gives theproper static regulation provided by the voltage loop controller.The same variables for inductive load of 5 kVA and powerfactor of 0.86 are presented in Fig. 18. The currents are alsobalanced with modules 1 and 2 providing 11.8 Arms and 12.6Arms to the system, respectively. In this test, the output voltageis 215.6 Vrms.

Fig. 19. IL1, IL2, IL3 (20 A/div., 2 ms/div.) and V0 (100 V/div., 2 ms/div.)under nonlinear load.

Fig. 20. IL1, IL2, IL3 (10 A/div., 2 ms/div.) and V0 (100 V/div., 2 ms/div.)in nonload operation.

Fig. 19 presents the output voltage and the inductor currentsof the three inverters for a 10 kVA nonlinear load and a 2.5 crestfactor. The voltage has a total harmonic distortion (THD) ofapproximately 4.5%, confirming a good performance of thevoltage control strategy using instantaneous values. The cur-rents are balanced with inverters 1, 2, and 3 providing 16.3Arms, 16.5 Arms, and 17.5 Arms to the system, respectively.

Fig. 20 shows the system in nonload operation, which is theworst situation in terms of the parallelism control. The resultsshow that the arrangement is functioning properly, with no cur-rent circulation between VSIs. The fundamental components ofthe currents shown in Fig. 20 are in phase and are circulating inthe LC filters of the three inverters.

Fig. 21 presents the output voltage V0, and the currents IL1,IL2, and IL3 during the hotswap of inverter 1 in the systemunder a 10-kVA nonlinear load. The change in IL1 shows theinstant of the connection of inverter 1 to the system. Duringthe hotswap, the voltage has a smooth transient response,which is typical of damped systems. The currents have a fasttransient response and quickly find a new steady-state operation


Fig. 21. IL1, IL2, IL3 (50 A/div., 10 ms/div.) and V0 (200 V/div., 10 ms/div.)under nonlinear load, during the hot-swap connection of inverter 1.

Fig. 22. IL1, IL2, IL3, ILo (5 A/div., 10 ms/div.) and V0 (100 V/div., 10ms/div.) during a difference of 50 V between the voltages supplied to the VSIs.

point. Immediately, after the connection, the load current isadequately shared among the inverters.

The results obtained for two parallel-connected VSIs fed bybatteries can be seen in Fig. 22, which shows the inductorand load currents and the output voltage. At the instant ofacquisition, the voltage difference between the batteries was50 V. Even with a difference of 50 V (18%) in the voltagessupplied to the VSIs, the control strategy ensures an adequateload sharing between the VSIs. The graph of Fig. 23 showsthe division of the load current among the inverters across thewhole range of operation. This graph demonstrates that thecontrol strategy ensures the parallel operation of the VSIs ina wide range of operation points.

Fig. 24 reveals the parallel operation of different powerinverters. In this test, there are two 5-kVA and one 2.5-kVAinverter connected in parallel supplying a 7.5-kVA nonlinearload. On designing the KIL gain of the 2.5-kVA inverter equalto twice the KIL gain of the 5-kVA inverters, the proposedcontrol strategy ensures adequately load current sharing amongthe parallel inverters, even when these are of different power.

Fig. 23. Current distribution among three parallel-connected inverters undernonlinear load.

Fig. 24. IL1, IL2, IL4 (20 A/div., 2 ms/div.) and V0 (100 V/div., 2 ms/div.)under nonlinear load.

Fig. 24 shows that the 5-kVA inverter currents IL1 and IL2

are similar, with values of 14.4 Arms and 14.2 Arms each. Thecurrent IL4 of the 2.5-kVA inverter is approximately half thatof the others (6.9 Arms), as is desirable for this inverter.

VI. CONCLUSION

This paper proposes a technique for the parallel operationof single-phase VSIs. The principle of the control strategyreported herein consists of employing the feedback of theinductor current from the output filter of the VSI to modifythe input voltage of the same filter. Thus, the resulting controltopology utilizes only internal variables of the VSI to controlits operation in the parallelism. Therefore, each inverter hasits own parallelism control, which is responsible for ensuringthe proper sharing of the load current and avoiding currentcirculation among the parallel-connected inverters.

The proposed control strategy permits the parallelism ofVSIs to be obtained, in which the units operate independentlyfrom each other, at the same time obtaining a very robust sys-tem. These characteristics allow the application of the proposedcontrol strategy in the parallelism of UPS. With the proposedparallelism control, the inverters are paralleled without anyconnection impedance. They work at any load level, including


nonload operation. The control strategy allows the connectionand/or disconnection of one inverter from the common ac buswith a smooth transient response in load voltage. It also enablesthe parallel operation of different power inverters.

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Telles B. Lazzarin (S’09–M’12) was born inCriciúma, Santa Catarina, Brazil, in 1979. He re-ceived the B.S., M.S., and Ph.D. degrees in electricalengineering from the Federal University of SantaCatarina, Florianópolis, Brazil, in 2004, 2006, and2010, respectively.

He is currently working as a Postdoctoral Fellowat the Power Electronics Institute, Federal Univer-sity of Santa Catarina, Florianópolis. His interestsinclude dc-ac power converters, dc-dc power con-verters, ac-ac power converter, parallel operation of

inverters, and uninterruptible power supply.

Guilherme A. T. Bauer was born in Florianópolis,Santa Catarina, Brazil, in 1985. He received the B.S.degree in electrical engineering from the FederalUniversity of Santa Catarina, Florianópolis, Brazil,in 2008.

He is currently an Electrical Engineer at the Com-panhia Estadual de Distribuição de Energia ElétricaCEEE-D, Rio Grande do Sul, Brazil. His interestsinclude dc-ac power conversion, converters paral-lelism, uninterruptible power supply, and design ofhigh-voltage substations.

Ivo Barbi (M’78–SM’90–F’11) was born in Gaspar,Santa Catarina, Brazil, in 1949. He received the B.S.and M.S. degrees in electrical engineering from theFederal University of Santa Catarina, Florianopo-lis, Brazil, in 1973 and 1976, respectively, and theDr.Ing. degree from the Institut National Polytech-nique de Toulouse, France, in 1979.

He founded the Brazilian Power Electronics Soci-ety and the Power Electronics Institute of the Fed-eral University of Santa Catarina. He is currently aProfessor at the Power Electronics Institute, Federal

University of Santa Catarina.

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