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A COMPUTER-AIDED DESIGNAND SYNTHESIS

ENVIRONMENT FOR ANALOGINTEGRATED CIRCUITS

by

Geert Van der PlasKU Leuven

Georges GielenKU Leuven

and

Willy SansenKU Leuven

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

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Abstract

Due to the ever decreasing feature size of silicon technology the complexity that can be inte-grated on a single chip has reached the system level. Soon, as much as 100 million transistorswill be integrated on one ICs. We have truly entered the System-on-a-Chip (SoC) era. Theexisting design methodologies are insufficient for handling these designs, hence a growingdesign productivity gap develops: design productivity can not keep up with the design needscreated by SoCs. Although these SoCs are primarily digital, they interface to the real world,which is analog. Analog building blocks thus become increasingly more important in a worlddominated by digital techniques. In this work, research into design automation for analogcircuits has been carried out. Two complementary approaches have been investigated.

Firstly, an automatic analog synthesis system, AMGIE, has been built. The AMGIEsystem is targeted towards the automatic synthesis from specifications down to layout ofmoderate-complexity analog circuits (device count lower than 100) that have a high reusefactor. It uses a performance-driven, hierarchical top-down refinement, bottom-up assemblydesign methodology. Two libraries are required for its operation: (1) a cell (topology) librarycontaining a set of alternative implementation templates and (2) a technology library contain-ing technology parameters. Five design tools automate the different design tasks. Topologyselection selects among the topologies in the library the most likely candidate using a se-quence of three filters. The sizing and optimization tool determines the sizes and biasing ofthe selected schematic by using a (modified) equation-based optimization methodology. Thederivation of the sizing plan has been automated using a setup environment supported by de-sign tools. The layout tool LAYLA [Lam 99| uses a direct performance-driven macro-cellplace & route methodology to generate the layout of the sized schematic. Verification stepsafter sizing and layout extraction verify the design. Potential design problems are dispatchedto the redesign wizard. The redesign wizard provides corrective design procedures to help thedesigner resolve the detected problem.

A comparison experiment between different sizing approaches indicates that the imple-mented modified equation-based optimization approach is the most appropriate when a highreuse factor is to be expected. A second experiment, the design of an OTA circuit by EEMaster students, indicates that the AMGIE system creates a new breed of analog designers:system-level designers or less experienced analog designers that are capable of successfullydesigning moderate-complexity analog circuits in a few hours. The AMGIE system can how-ever also handle more complex circuits, as has been demonstrated by the design, fabricationand measurement of an analog signal processing building block: a charge-sensitive amplifier– pulse-shaping amplifier combination.

The design automation approach used in the AMGIE approach, however, relies on accu-

mulated design expertise under the form of a cell library which is reused by less experienceddesigners. Sometimes, the performance specifications of an analog block can not be obtainedusing existing analog design knowledge and techniques: these are high-challenge designs thatrequire design creativity. In this case full automation is not possible, but the designer can stillbe supported. The systematic design methodology that is presented in this work is targetedtowards the design of these high-performance analog blocks. It leaves room for analog designcreativity: coming up with new ideas to solve hard design problems. The methodology steersthis creativity to be productive, by linking every design choice that has to be made to the re-quested specifications. The design productivity is further increased by support through analogCAD tools.

The Mondriaan tool presented in this work is such a tool. It automates the layout gener-ation of the highly-regular analog blocks often found in high-speed converter architectures. Itautomates the back-end process of routing and technology mapping while giving the designera more abstract view of the layout problem: a floorplan which determines the final positionand connectivity of the cell array.

The presented systematic design methodology has then been applied to the design of high-speed current-steering D/A-converters. The first phase in the design flow is the specificationphase. Using behavioral modeling and simulation the specification of the D/A-converter func-tionblock have been derived. The second phase in the design flow is the synthesis of theconverter. A top-down refinement, bottom-up, mixed-signal design strategy has been adopted.In the bottom-up path, Mondriaan was used to generate the layout of the analog modules,while a standard cell place & route tool was used to create the digital layout. In the last phaseof the design a behavioral model is extracted that mimics the actual silicon part. This researchhas resulted in the first 14-bit accurate current-steering D/A-converter in CMOS technologythat does not require trimming or tuning. This performance was obtained by creating the novel

random walk switching scheme.Both presented approaches increase analog design productivity. This is demonstrated in

the text with design time reports for all the experiments that have been carried out.

Abstractii

List of Abbreviations

1P2M1P3M2P2MACA/D-converterADSLAHDLAMSA/MSASICASSPAWEBCBiCMOSCADCDCMOSCNNCPUCSACSA-PSACUDD/A-converterdBDCDIFFDLLDNLDRCDRIDSPDVDEDAEEERC

single poly, double metalsingle poly, triple metaldouble poly, double metalalternating currentanalog to digital converterasymmetric digital subscriber lineanalog hardware description languageanalog and mixed-signalanalog / mixed-signalapplication-specific integrated circuitapplication-specific standard partsasymptotic waveform evaluationboundary checkingbipolar complementary metal-oxide semiconductorcomputer-aided designcompact disccomplementary metal-oxide semiconductorcellular neural networkcentral processing unitcharge-sensitive amplifiercharge-sensitive amplifier – pulse-shaping amplifiercell under designdigital to analog converterdeciBeldirect current or design controllerdifferentiatordelay-locked loopdifferential non-linearitydesign rule checkdata representation interfacedigital signal process(ing/or)digital versatile discelectronic design automationelectrical engineeringelectrical rule check

iv List of Abbreviations

ETGaAsGCMGPGUIHDLICINLINTIPITRSLC-VCOLNAlow-IFLSBLSILTLVSMMPREMOSMSBNMOSOPAMPOTAOTA-CPCPCAPDFEPLLPMOSPSAPSRRPWLQ2

RCRFRGBROMS/HS&OSFDRSIASiGeSNDRSNR

extraction toolGallium-Arsenidegeometrical calculation modelgeometric program(ming)graphical user interfacehardware description languageintegrated circuitintegral non-linearityintegratorintellectual propertyinternational technology roadmap for semiconductorsinductor-capacitor tank VCOlow-noise amplifierlow intermediate-frequencyleast significant bitlarge-scale integrationlayout generation toollayout versus schematicmismatch preprocessormetal-oxide semiconductormost significant bitn-type MOS transistoroperational amplifieroperational transconductance amplifieroperational transconductance amplifier - capacitorpersonal computerprincipal components analysisparticle detector front-endphase-locked loopp-type MOS transistorpulse-shaping amplifierpower-supply rejection ratiopiecewise-linearquad quadrantresistor-capacitorradio-frequencyred green blueread-only memorysample-and-holdsizing and optimization toolspurious-free dynamic rangesemiconductor industry associationsilicon-germaniumsignal-to-noise-and-distortion ratiosignal-to-noise ratio

List of Symbols v

SoCSQPSVDSWITCAPTSVCOVFSRVGAVLSIVSIVTxDSLzero-IF

system-on-a-chipsequential quadratic programmingsingular value decompositionswitched-capacitortopology selectionvoltage-controlled oscillatorvery fast simulated re-annealingvariable-gain amplifiervery large-scale integrationvirtual socket interfaceverification toolany type of digital subscriber linezero intermediate-frequency

List of SymbolsNotation:

infinitythe empty setproportional to

= equal tonot equal toapproximately equal tocoefficients of polynomialinteger countersscalar functionsscalar variablesvector functionsvector variablesscalar subfunctions of vector functionscalar subvariables of vector variableexponentexpected value of xaverage value of x

List:

context dependent parameterset of design parameters, input specs and technology parametersthe amplitude of the glitch

i, j, . . .

f, g, . . .x, y, . . .

f, g, . . .x , y , . . .

E{x}

AA

vi List of Symbols

low-frequency gainMOS mismatch model parameters [Laksh 86, Pel 89]scaling parameter for scalar cost functionbeta functionbandwidthdetector capacitance(CSA) feedback capacitancegate source, gate drain, etc. capacitance of transistorload capacitanceoutput capacitancestatistical indices for design centeringparasitic capacitanceperformance specification margin or rangedifferential non-linearityith order error profileglitch energyequivalent noise chargetotal equivalent noise chargescalar cost functioninput signal frequencyfrequency of pole or zerorouting overhead factorsampling frequencyscaling parameter for scalar cost functiongainbandwidthtransconductance and output conductance of MOS transistornoise spectral densityintegral non-linearityinput rangeMOS DC current generating transconductanceLSB currenttotal DC currentfull-scale output currentBoltzmann’s constant (1.38e-23 J/K)transistor transconductance factor,loop counter or number of binary bits in a D/A-converterith eigenvalueeigenvalue matrixlength of transistor m1output value of code level in a D/A-converterlength related technology parametersprocess independent values of length and width of transistorsnumber of unary bits in a D/A-converterPSA order, number of bitsoutput range

BW

cgs, cgd, . . .

DNL

ENC

GBWgm, go, . . .

INLIR

kKPl

LMIN, LGRID, LMAXlogL, logWmnOR

List of Symbols vii

performance specificationphase margintopology performance region lower- or upperboundelementary electron charge (1.602e-19 C)reuse factor(CSA) feedback resistanceground line resistanceload resistanceoutput resistance of MOS transistoroutput resistance of a D/A-converterparasitic resistancetopology ranking valuesubblock specification set (estimators)standard deviation of a quantity xsingular value decomposition matrixsensitivity of a to variable bsignal to noise rateslew rateMOS mismatch model parameters [Laksh 86, Pel 89]Temperaturetime constanttechnology parameter setpeaking time constantpole zero time constantrise time constantglitch duration timestep functionpower supply voltagesdevice terminal voltage differencestransistor overdrive voltage,offset voltage due to random and systematic effectsfull-scale output voltagethreshold voltagenumber of wiresweight of constraint in cost functionwidth of transistor m1width related technology parameters

PPM

qr f

ro

rvS

SNRSR

T

u()

WMIN, WGRID, WMAX

Contents

Abstract

List of Abbreviations

List of Symbols

Contents

List of Figures

List of Tables

i

iii

v

ix

xiii

xvii

1 Introduction1.1 Goals of this Work1.2 Outline of this Work

19

11

I Automatic Synthesis of Analog Circuits 13

2 The AMGIE Analog Synthesis System2.1 Introduction2.2 Definitions2.3 Overview of Analog Synthesis Research

2.3.1 Early Work2.3.2 Second Generation2.3.3 Most Recent Work2.3.4 Conclusions

2.4 The AMGIE Synthesis System2.4.1 Functionality of the Analog Synthesis Environment2.4.2 Software Architecture of the AMGIE System

2.5 Summary

151515192021232526263438

3 Detailed Description of the AMGIE Analog Synthesis System 39394242

3.13.2

Specifications and HierarchyTopology Selection Tool3.2.1 Boundary Checking Filter

x Contents

3.2.23.2.3

Interval Analysis FilterRule-based Ranking Filter

3.3 Sizing and Optimization Tool3.3.13.3.23.3.3

Sizing Model GenerationCircuit Optimization SetupPractical Example

444545475557616465666970707071

737374747576777979798689909192

101102102106106107108

109

113

115Introduction

II Systematic Design of Analog Circuits

Conclusions

3.4 Layout Generation Tool3.4.1 Practical Example

3.5 Verification Tool3.5.13.5.23.5.3

Nominal Performance VerificationVerification with Mismatches and Technology SpreadVerification over Temperature and Power-supply Operating Ranges

3.6 Redesign Wizard3.6.1 Example Scenarios

3.7 Summary

4 AMGIE Experimental Results4.1 Comparison of Analog Sizing Synthesis: Equation-based vs. Simulation-based

4.1.14.1.24.1.34.1.44.1.5

Design SpecificationsManual SizingSimulation-based SizingEquation-based SizingComparison & Conclusions

4.2 Student Exercise: High-speed Operational Transconductance Amplifier4.2.1 Setup4.2.2 Session4.2.3 Analysis of Results4.2.4 Conclusions

4.3 Charge-Sensitive Amplifier – Pulse-Shaping Amplifier4.3.14.3.24.3.34.3.44.3.54.3.64.3.74.3.8

CSA-PSA SpecificationsCSA-PSA ArchitectureTopology SelectionSizing Synthesis: OPTlMAN

Layout GenerationVerificationMeasurement ResultsConclusions

4.4 Summary

Contents xi

5 Mondriaan: a Layout Synthesis Methodology for Array-type Analog Blocks5.15.25.3

Requirements of the New Layout Generation MethodologyDescription of the Layout ModelDescription of the Layout Generation Methodology5.3.15.3.25.3.35.3.4

FloorplanningSymbolic RoutingTechnology MappingBus and Tree Generators

117119120123124125126127130130133135136137137140143

145146148148149152152154154156156159161163163163164176177177178178179181181182184

5.4 Illustrative Example5.4.1 Current Source Array5.4.2 Switch/Latch Array5.4.3 Assembly5.4.4 Conclusions

5.5 Experimental Results5.5.15.5.2

Folding/Interpolating A/D-converter ModulesCurrent-Steering D/A-converter Modules

5.6 Conclusions

6 Systematic Design of Current-Steering D/A-converters6.16.2

Functionblock Design FlowCurrent-Steering D/A-converter Architecture6.2.1 Operating Principle and Specifications6.2.2 Proposed Architecture and its Design Parameters

6.3 Behavioral Modeling for the Specification Phase6.3.16.3.2

Dynamic BehaviorStatic Behavior

6.4 Synthesis Flow of the D/A-converter6.5 Sizing Synthesis

6.5.16.5.26.5.36.5.4

Architectural-level SynthesisCircuit-level SynthesisFull Decoder SynthesisClock Driver Synthesis

6.6 Layout Generation6.6.16.6.26.6.36.6.46.6.5

FloorplanningCurrent Source Array Layout GenerationSwatch Array Layout GenerationFull Decoder Standard Cell Place and RouteLayout Assembly

6.7 Extraction of a Behavioral Model for Verification6.7.16.7.2

Static Behavior: INLDynamic Behavior: Glitch Energy

6.8 Experimental ResultsMeasurement Setup6.8.1

6.8.26.8.3

Measurement ResultsBreakdown of Design Time

xii Contents

6.9 Conclusions

7 Conclusions

186

189

193

205

Bibliography

Index

List of Figures

1.11.21.3

1.41.5

1.6

2.12.22.32.42.52.62.7

2.82.92.10

2.11

3.13.2

3.33.4

3.53.6

3.73.83.93.103.11

Typical floorplan of a System-on-a-Chip (SoC)European Medea EDA roadmap [Medea 00] for mixed analog/digital and RF design.System-on-a-Chip functionblock hierarchy: the analog part has been refined down tothe device levelHigh-performance analog designView of design space: low-challenge and high-challenge designs and technology limitas a function of speed and accuracyOutline of this work.

Definitions.Different types of hierarchical decomposition for a flash type A/D-converterHierarchical view of the design process [Gie 00].Plan-based sizing tools (a) versus optimization-based sizing tools (b) [Gie 00]Snapshot of the AMGIE specification sheet editor.Hierarchical design flow implemented in the AMGIE synthesis system.Different hierarchical design strategies (the numbers indicate the sequence of the stepsexecuted).Graphical User Interface (GUI) of the AMGIE systemSoftware architecture of the AMGIE synthesis systemPetri net of the design controller (one hierarchical level — forward path only, redesignhas not been included in the figure).The Design Controller (DC) retrieves the input, runs the tool and stores the results.

Specification margins and ranges.Filter sequence implemented in the Topology Selection (TS) tool; the darker grey areaindicates the overlap between specifications and performance space or its bounding box.Boundary checking illustrated for (a) one and (b) two performance characteristicsFeasibility check with the relations between two parameters (a) and the result of thecombination of both filters (b).Sizing model generation procedure and application.The estimated area of a MOS transistor (including routing space) as a function of its Wand L compared to its active area (W * L)One-transistor amplifier circuitUndirected bipartite graph of the one-transistor amplifier circuit.Directed bipartite graph of the one-transistor amplifier circuit.Snapshot of the viewer of the sizing optimization processSchematic of the symmetrical OTA with class-AB output stage

26

78

912

171819222829

313335

3738

41

4244

4548

525253545859

xiv List of Figures

3.123.133.143.153.163.17

3.183.193.203.21

4.14.24.34.44.54.64.7

4.8

4.94.104.114.124.134.144.154.164.17

4.184.194.20

4.21

5.1

5.2

Trace of the VFSR optimization.Power–area tradeoff of the symmetrical OTA with class-AB buffer stageThe macro-cell place and route methodology used in LAYLA [Lam 99].Schematic of the Miller-compensated OTA.Performance-driven layout of the Miller-compensated OTA.The circuit under test, the encapsulated circuit with biasing and clocking templates(topology specific) and the verification template (functionblock and verification taskspecific) are applied to generate a test harness.The datasheet editor.The black box OPAMP in its test harness for slew rate analysisOutput signal and measurements.For mismatch simulations every MOS transistor is replaced by an equivalent statisticalmodel.

Schematic of the high-speed OTA used in the synthesis comparison project.Local feedback loop in the high-speed OTA.Decreasing cost as a function of design improvements.Verification after sizing and optimization of a synthesized OTA (results for group5).Performance-driven generated layout (group5 result).Verification after extraction of a synthesized OTA (results for group5).Layout results of the exercise session. Note that the smaller layouts have been scaledup slightly to increase visibility. The trend of the area change is however maintained.Breakdown of the OTA design time, in the case of an experienced tool user and de-signer. The reported time units are minutes.Block diagram of a typical particle detector front-end (PDFE).Architecture of the CSA-PSA circuit.Schematic of the active resistor.Schematic of the folded-cascode charge-sensitive amplifier (CSA).Charge-sensitive amplifier (CSA) open-loop Bode diagrams.Charge-sensitive amplifier (CSA) closed-loop Bode diagrams.Rise time of the charge-sensitive amplifier (CSA).Schematic of the pulse-shaping amplifier (PSA) with pole-zero cancellation.Results of topology selection: relative order of the 8 topologies (vertical axis — topol-ogy 8 is number 1 in the list) over varying performance specifications as function ofthe maximum power (horizontal axis).Schematic of the charge-sensitive amplifier – pulse-shaping amplifier circuit.Template floorplan for the CSA-PSA topology.Microphotograph of the charge-sensitive amplifier – pulse-shaping amplifier prototypechip.Peaking time measurement of the prototype chip: time response to an incident particlewith a charge of l00fC.

Three analog array types: signal generation (current-source array that generates nequal currents), signal processing (n amplification stages, found in flash-type A/D-converters) and signal multiplication and processing (current mirrors, used in interpo-lation circuits).Cell array model implemented in the Mondriaan tool.

6061626465

66676868

69

747778838485

87

899092939496969698

101104105

106

107

119120

List of Figures xv

5.3

5.4

5.55.65.75.85.9

5.10

5.11

5.12

5.13

5.14

5.155.16

5.17

5.18

5.195.205.215.22

6.16.26.36.4

6.5

Using spacer cells to extract array-wide connections; the spacer cell is required to real-ize the asymmetric contacts as shown in the sp2 cell on the left.Symbolic view of cells and routing channels: vertical routing across cells, horizon-tal routing in between cells. Vertical wires connect to the contact areas in the cell,horizontal wires connect to the vertical wires.Cell outline: cell extent, contact areas and routing channel.Layout generation flow.Bus device generators.Tree device generators.Schematic of current source array: 16 equal current sources (a), each current source issplit in four units (b), and the floorplan (c).Automatically generated 4-bit unary current-source array. For reasons of clarity theactual current-source cells have not been displayed except for the dummy cells sur-rounding the array. The pins are shown at the top of the figure.The switch/latch cell contains a digital latch driving a switch (a). The routing-drivenassignment result: the pins at the bottom of the figure have been input, the assignmentof the switch/latch cells and output pins (at the top) have been derived by propagatingthe connectivity (b).Layout of the 4-bit switch/latch array. For reasons of clarity the switch/latch cells’contents have not been displayed. The pins are shown at the bottom and at the top ofthe figure. At every odd column of the latch cell columns, spacers have been insertedto collect the output currents.Complete layout of the 4-bit analog core. The current source array and switch/latcharray have been placed and the array-wide and individual signals have been connectedusing trees and buses.Generating folding signals by cross-coupling the input stages in a high-speed A/D-converter.Full layout (a), and zoom in on one fold of a folding input stage (b).Generating interpolated signals by using weighted current mirrors in a high-speed in-terpolating A/D-converter.Floorplan of interpolating current mirrors. The numbers indicate the interpolation sig-nal being generated, the greyed out cells are dummies (surrounding the array and fillingup empty slots).Layout of interpolating current mirrors. This layout corresponds to the floorplan shownin figure 5.17.Block diagram and floorplan of the proposed D/A-converter architecture.Schematic of the current-source array of the 14-bit current-steering D/A-converter.Floorplan of the current source array of the 14-bit current-steering D/A-converter.Automatically generated layout of the 14-bit current-steering D/A-converter.

Converter functionblock design flow.Operating principle of a segmented current-steering D/A-converter.Block diagram and floorplan of the proposed D/A-converter architecture.Three different switching schemes: (a) unary current source implemented as 1 unit,(b) unary current source implemented as 4 units in parallel, (c) unary current sourceimplemented as 16 units in parallel.Calculation of the amplitude of the damped sine in terms of the glitch energy

121

121122123128129

131

132

134

135

136

137138

139

139

139141141142142

147148150

151

153

xvi List of Figures

6.6

6.76.8

6.96.106.116.126.136.146.15

6.166.176.18

6.196.206.216.226.23

6.246.256.266.276.28

Time response of the behavioral model: at one additional current source is switchedon; at several additional current sources are switched on.D/A-converter synthesis design flow.Yield as a function of unit current cell variance for a 14-bit D/A-converter (INL betterthan 0.5 LSB).Estimated area of the D/A-converter as a function of the number of unary bits (m).Schematic of the table look-up based thermometer encoder.Relative current errors.Floorplan of the current source array of the 14-bit D/A-converter test chip.Microphotograph of the 14-bit D/A-converter test chip.DNL measurement of the 14-bit D/A-converter test chip.The errors of the unary current sources in the matrix: (a) error surface, (b) oppositeangle error surface, (c) averaged horizontal error and (d) averaged vertical error.Hierarchical approach to optimize the switching sequence of 256 sources.Switching sequence of the Random Walk switching scheme.Simulation of INL for the same error profiles using: (a) Q2 classical sequential switch-ing scheme [Miki 86], (b) Q2 Random Walk switching scheme [Vdbus 99a, VdPlas 99b].Layout (cell outline) of the current source transistor.Layout of the swatch (switch/latch) cell.Microphotograph of the 14-bit D/A-converter [Vdbus 99a, VdPlas 99b].Comparison of numerically simulated INL with PCA extracted model of INL.Comparison of extracted glitch model with numerical simulation, the straight l ine isobtained using device-level simulation, the dash dotted line is obtained by using theextracted behavioral mode and simulation. At the bottom the clock and five bit linesare shown.Photograph of the measurement setup.Block diagram of the dynamic measurement setup.Microphotograph of the 12-bit D/A-converter [VdBosch 98].Measurement results of the 12-bit D/A-converter [VdBosch 98].Measurement results of the 14-bit D/A-converter [Vdbus 99a, VdPlas 99b].

153155

157158162166167168169

170172174

175176176177179

180181181182183185

List of Tables

3.13.23.33.4

3.5

4.1

4.2

4.34.44.54.64.74.84.94.10

4.114.12

4.13

5.1

6.16.26.36.4

6.56.66.7

Characteristics of analog circuit sizing approaches.Meta-model technology parameters and categories.Synthesis specifications of the symmetrical OTA with class-AB output stage.Sensitivity and performance degradation of the Miller-compensated OTA after place-ment and routing (internal nodes only); PM is 60.7°, GBW is 30MHz.Performance of the Miller-compensated OTA.

Required and obtained performance specifications, the results of the equations-basedresult are shown.Summary of times spent on the optimal design of the OTA circuit by the three presentedapproaches, the last row reports the total design time per design with inclusion of thesetup time assuming a reuse factor ( r f ) of 10.Common specifications for all groups.Specification values different for all groups.Sizing and biasing values of the student design runs.Sensitivity data.Obtained power consumption values.Obtained offset voltage values.Obtained phase margin values.Specifications common to all OTA designs, comparison with obtained performancesafter extraction and simulation (design from group 5).Specification set of the CSA-PSA functionblock.Specifications and performance achieved after sizing verification of the synthesizedCSA-PSA circuit.Measured performance of the synthesized CSA-PSA prototype chip and a previousmanual design.

Time spent on layout for a manual design and a design using the proposed methodology,showing the realized productivity gain.

Specification table of current-steering D/A-converters with typical values.Design parameters of the presented D/A-converter architecture.Truth table for the thermometer encoder (m = 4)Truth table for the different coders (m = 4): (a) coarse encoder, (b) fine encoder, (c)address decoder.Rules for optimum matching.Measured performance of the three systematically designed D/A-converters.Time spent on design, layout and verification of the three designs.

465059

6465

75

7880808283868888

8891

103

108

143

149151161

162171184186