A case study of test program generation

Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)

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A case study of test program generationJ. M. Martins Ferreira

FEUP / DEEC - Rua Dr. Roberto Frias

4200-537 Porto - PORTUGAL

Tel. 351 225 081 748 / Fax: 351 225 081 443

([email protected] / http://www.fe.up.pt/~jmf)


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Objectives

• To present practical BS test problems through a real case study

• To analyse the implementation of the test protocol using the test instruction set proposed earlier

• To enable the student to acquire the necessary experience to develop small test programs for specific test situations

• To enable hands-on sessions


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Outline

• The demonstration board

• The information required for test program generation

• The test vectors

• The test program


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The demonstration board

net 232Y3O7

O6

O5

O4

O3

O2

O1

O0

I7

I6

I5

I4

I3

I2

I1

I0

0

1

2

3

4

5

6

7

8

9

17

16

15

14

13

12

11

10

0

1

2

3

4

5

6

7

8

9

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

10

11

12

13

14

15

16

172Y2

2Y1

2Y0

/1Y3

/1Y2

/1Y1

/1Y0

A1

B1

A2

B2

A3

B3

A4

B4

Y1

Y2

Y3

Y4

net 22

net 21

net 20

net 19

net 18

net 17

net 16

net 7

net 6

net 5

net 4

net 3

net 2

net 1

net 0

net 11

net 10

net 9

net 8

net 14

net 15

Cluster 0BS Component 0 BS Component 1 Cluster 1

BS Component 2

TDI 0

TDO 0

TDO 1

TDI 1

net 13

net 12

A

B

/G1

/G2

S /G

(IC3) (IC1 and IC2) (IC4) (IC6)

(IC5)


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BS infrastructure

Parameter Component 0 Component 1 Component 2

Component belongs to BS chain 0 0 1

Location of the component in the chain 0 1 0

Length of the Instruction Register (IR) 8 8 8

Contents of the IR following capture XXXXXX01 XXXXXX01 XXXXXX01

Is an Identification Register present? No No No

Sample / Preload code 00000010 00000010 00000010


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Full-BS interconnects (1)

• Number and identification of the BS chains• Is the interconnect tied to GND or VCC?• For output pins:

– Number of output pins and location of the output cell, the control cell (if any) and the tristate control value

• For input pins:– Number of input pins and location of the input

cell


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Full-BS interconnects (2)

• For bidirectional pins:– Number of bidirectional pins and location of

the output cell, the input cell, the control cell and the tristate control value

• For primary input pins:– Number of primary inputs, identification and

tristate control value

• For primary output pins:– Number and identification of primary outputs


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The IC1+IC2 non-BS cluster

10

11

12

13

20

21

22

23

24

25

26

27

A

B

/G1

/G2

/1Y0

/1Y1

/1Y2

/1Y3

2Y0

2Y1

2Y2

2Y30

BS chain 0BS chain 0

IC1 and IC2


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Test of IC1+IC2 (1)

Parameter Value

Number of BS chains surrounding the cluster 1 (chain 0)

Information concerning BS chain 0

Number of BS cells 13

Identification of the BS cells 0,10,11,12,13,20,21,22,23,24,25,26,27

# of cluster inputs that are also primary inputs 0

# of cluster outputs that are also primary outputs 0

Guard values required? No


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Test of IC1+IC2 (2)

# vectors BS chain To shift in Expected values Mask data

5 0 0111011111111

0110111111111

0000011111111

0010011111111

0100011111111

1111111110001

1111111100000

1111101111000

1111111010010

1111110110100

0000011111111

0000011111111

0000011111111

0000011111111

0000011111111

• HILO generated 5 test vectors to provide 100% fault coverage of stuck-at pins in both components


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The IC6 non-BS cluster

2

3

4

5

Y1

Y2

Y3

Y4

A1

B1

A2

B2

A3

B3

A4

B4

28

29

30

31

32

33

34

35

14

15

S

/G

19

1

18

BS chain 1

BS chain 0

IC6


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Test of IC6 (1)Parameter Value

Number of BS chains surrounding the cluster 2 (chains 0 and 1)



Identification of the BS cells 1,14,15,18,19,28,29,30,31,32,33,34,35



Identification of the BS cells 2,3,4,5

# of cluster inputs that are also primary inputs 0

# of cluster outputs that are also primary outputs 0

Guard values required? No


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Test of IC6 (2)

• HILO generated 5 test vectors to provide 100% fault coverage of stuck-at pins in IC6

# vectors BS chain To shift in Expected values Mask data

0 0000011111010

0000000010001

0110000110111

0100011010101

0100000100010

1111111111111

1111111111111

1111111111111

1111111111111

1111111111111

0000000000000

0000000000000

0000000000000

0000000000000

0000000000000

5

1 1111

1111

1111

1111

1111

1111

0000

0000

1111

0000

1111

1111

1111

1111

1111


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The BS components

Parameter Component 0 Component 1 Component 2

Component belongs to BS chain 0 0 1

Location of the component in the chain 0 1 0

Length of the BS Register 18 18 18

The component supports BIST? No No No

Number of test vectors for internal test 2 2 2

INTEST code 00000000 00000000 00000000

Component To shift in Expected values Mask data

Each component 110101010111111111

111010101000000000

111111111101010101

000000000010101010

000000000011111111

000000000011111111


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The test vectors

• A modified version of the self-diagnosis algorithm generated 6 test vectors for complete short-circuit fault detection in the 24 full-BS interconnects:

ptv[0]: 010101010001000001010101

ptv[1]: 010101010010000010101010

ptv[2]: 011010100001000001011010

ptv[3]: 100110100001000010100101

ptv[4]: 101001100010000001100110

ptv[5]: 101010010010000010011001


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The serialised test vectorsTOTAL NUMBER OF INFRASTRUCTURE TEST PATTERNS: 4

*************************************************************************** Infrastructure test pattern number 0 (ID or BP register opcodes for IR's): *************************************************************************** Boundary scan chain number 0: Test pattern: TP[0][0]: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 Expected result (to be shifted out while this test pattern is shifted in): ER[0][0]: 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 Mask bits (for this expected result): MB[0][0]: 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 .. ..


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The test program0001 00000002 0000 ;***********************************************************0003 0000 ; Assembly source code for the demo circuit.0004 0000 ;***********************************************************0005 00000006 0000 start .org 0h0007 00000008 00000009 0000 ; Sequence to reset all BST logic.0010 00000011 0000 1A seltap0 ; (switch to) TAP 00012 0001 11 trst ; TRST0 output is pulsed low0013 0002 01 tms10014 0003 01 tms10015 0004 01 tms10016 0005 01 tms1

(…)

0026 000F0027 000F ; Sequence to test the BST infrastructure0028 000F0029 000F 00 tms0 ; BST chain 0, >> Run Test / Idle0030 0010 01 tms1 ; BST chain 0, >> Select DR scan0031 0011 01 tms1 ; BST chain 0, >> Select IR scan0032 0012 00 tms0 ; BST chain 0, >> Capture IR0033 0013 00 tms0 ; BST chain 0, >> Shift IR0034 0014 02 00 1A ld cnt,26 ; length of IR's + 10, BST chain 00035 0017 05 nshfcp ; shift in the ID or BP opcodes0036 0018 01FD03FCFD03 inf0 .db $01,$fd,$03,$fc,$fd,$03,$ff,$01,$ff,$03,$00,$030037 0024 06 04 01 jpe theend ; stop the test, if a BST infrastructure fault is found

(…)


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Detection of open circuit X1

• What are the conditions enabling the detection of open circuit X1?


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JTAGercode (X1)

start:seltap0;rst;state irshift;ld cnt,16d; ! two IRsnshf 0h; ! EXTEST instructionstate drshift;ld cnt,18d; ! length of the BSR (IC3)nshf 02000h; ! /1G=0,1Y1=0,1Y2=1,1Y4=0 (in IC3)state drshift;ld cnt,18d; ! length of the BSRs

! Notice that we will shift only 18 bits, but:! - the bitstream shifted in goes to the BSR of IC3! - the bitstream shifted out comes from the BSR of IC4

nshfcp 0h,00400h,00400h; ! check 2A3 when 1Y2=1; set 1Y2=0jerr faulty;state drshift;ld cnt,18d; ! length of the BSR (IC4)nshfcp 0h,0h,00400h; ! check 2A3 when 1Y2=0jerr faulty;state reset;halt; ! stop here if X1 not open

faulty:state reset;halt; ! stop here if X1 open


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Detection of open circuit X1


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Detection of short circuit X9

• What are the conditions enabling the detection of X9?


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JTAGercode (X9)

start:seltap0; ! the test vector is applied via TAP0rst;state irshift;ld cnt,8d; ! length of the IR (IC3)nshf 0h; ! EXTEST instructionstate drshift;ld cnt,18d; ! length of the BSR (IC3)nshf 40000h; ! /2G=0,2Y2=0,2Y3=1,2Y4=0 (in IC3)state drselect; ! test vector applied on passing UPD-DR

seltap1; ! response capturing is via TAP1rst;state irshift;ld cnt,8d; ! length of the IR (IC5)nshf 0h; ! EXTEST instructionstate drshift; ! test response captured on passing CAPT-DRld cnt,18d; ! length of the BSR (IC5)nshfcp 0h,00400h,00400h; ! check if 2A2,2A3,2A4 are 0,1,0jerr faulty;state reset;halt; ! stop here if X9 is not shorted

faulty:state reset;halt; ! stop here if X9 is shorted


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24



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• What are the conditions enabling the detection of X16?


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JTAGercode (X16)

start:seltap0;rst;state irshift;ld cnt,16d; ! length of the IRs (IC3,IC4)nshfcp 0h,8080h,8080h;jerr faulty;state reset;halt; ! stop here if X16 is not shorted

faulty:state reset;halt; ! stop here if X16 is shorted


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• What would happen if only the first 8 bits were shifted out? (instead of 16)

ld cnt,8d; ! length of the IR (IC4)nshfcp 0h,80h,80h;

A case study of test program generation

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