A 35-mW 30-dB Gain Control Range Current ModeLinear-in-Decibel Programmable Gain Amplifier

With Bandwidth EnhancementThangarasu Bharatha Kumar, Student Member, IEEE, Kaixue Ma, Senior Member, IEEE,

Kiat Seng Yeo, Senior Member, IEEE, and Wanlan Yang

Abstract—This paper presents the design of a programmablegain amplifier (PGA) that serves as an interface between thereceiver front-end and the baseband processor. The proposedPGA design is fabricated in a commercial 0.18- m SiGe BiCMOSprocess with a topology consisting of two digitally variable gainamplifiers cascaded by a post amplifier and interconnectedby differential wideband matching networks that presents anoverall enhanced gain bandwidth product. By using the currentmode exponential gain control technique, the proposed designachieves a broad 30-dB linear-in-decibel gain range, a gain-inde-pendent output 1-dB compression point better than 10 dBm,input/output return loss better than 13 dB, a 0.75-dB gainflatness over a multi-decade frequency range from 2.5 MHz to1.17 GHz, a measured in-band group-delay variation of 30 ps, a35-mW power consumption, and a 0.25-mm core die area.

Index Terms—Bandwidth enhancement technique, common-mode feedback (CMFB), current mode design, dB linearity, dcoffset cancellation (DCOC), digital gain control, digital variablegain amplifier (DVGA), exponential current converter, intercon-nect network, linear-in-decibel gain control, linearizer, low powerdesign, programmable gain amplifier (PGA), SiGe BiCMOS,variable gain amplifier (VGA).

I. INTRODUCTION

A PROGRAMMABLE gain amplifier (PGA) is a key RFfrontend block in order to support mobile communication

capability of the wireless transceivers [1]–[14]. The PGA gaincontrol range determines the receiver input dynamic range thatcan provide a regulated stable power level to the baseband sec-tion, as shown in Fig. 1(a). The drive for recent RF research isfocusing on high data-rate communication in the gigabit/secondrange. Hence, the requirement of the PGA interfacing the base-band section is to provide a regulated stable power level and

Fig. 1. (a) RF frontend to baseband interface. (b) Block diagram of the pro-posed dB-linear PGA with DCOC.

also to support large bandwidth. As the state-of-the-art, the sup-ported applications as well as the density of system integra-tion of the microwave and the millimeter-wave transceivers aregradually increasing towards system-on-chip (SoC) solutions[2]. Additionally to support low power applications, the supplyvoltage is also gradually down scaled. This limits the gain andlinearity performance of a single amplifier stage compelling tomove towards the cascaded multiple stage amplifier topology.The conventional cascaded identical amplifier stages [15] pro-vide the desired high gain, as shown in (1); however, the band-width also shrinks as the number of cascaded stages increasesgiven by (2) as follows:

(1)

(2)

where and are the gain and bandwidth of the overallcascaded amplifier consisting of identical stages with andas the gain and bandwidth, respectively.

By sandwiching an all-pass-filter interconnect stage witha gain peaking network, the bandwidth enhancement canbe achieved, and it was also shown that the bandwidthenhancement can be achieved by implementing the resistor–in-ductor–capacitor (RLC) interstage network as a bandpassnetwork [16]. Initially, the interstage that enhanced the overallbandwidth of the cascaded stages was implemented by usingpeaking inductors in the interstage of wideband transimpedanceamplifiers [17] and also in wideband distributed amplifiers[18]. This technique was also extended from inductors totransformers [19], [20]. However, this elegant implementationconsumes more die area and the number of inductors increasedproportional to the number of cascaded stages. The inductivepeaking also affected the gain flatness by introducing rip-ples, which may also result in system instability. One of thepossibilities with smaller die area is to replace the inductorswith resistor–capacitor (RC) bandpass networks, which wasproposed in [21]. An active interconnect design by usingstagger-tuned amplifier stages based on this technique wasproposed in [22].In this paper, a thorough design consideration of a PGA

used in a commercially feasible high data-rate RF transceiversystem based on the low-cost, long battery-life, good linearity,and straightforward baseband interface is studied, proposed,and developed. The topology and the design aspects of theproposed PGA sub-blocks, namely the digitally variable gainamplifier (DVGA) designed by the same authors [23], thefixed gain post amplifier, along with the differential widebandinterconnect networks are theoretically analyzed and experi-mentally verified by on-wafer probing. By incorporating thewideband interconnect network, an overall improved PGA’sgain-bandwidth product (GBW) is achieved. With two DVGAstages and a fixed high gain post amplifier, the proposed PGAbecomes a suitable choice for the RF receiver frontend tointerface with the baseband section by providing a nearlygain-independent output gain compression point over a largedynamic range. Additionally, the current mode gain controlimproves the accuracy of proposed PGA’s dB-linear gain stepsand the current mode biasing limits the rail-to-rail dc current;hence reducing the overall dc power consumption as comparedto the existing state-of-the-art.In addition to the work described in [24], the main contri-

butions of this paper include the illustration of its GBW en-hancement that is realized by using the RC inter-stage network,the detailed analysis of the nearly gain-independent output gaincompression point over a large dynamic range, and the detailedinvestigation about the switching time, group delay, and highdata rate supported.This paper is organized as follows. Section II describes the

proposed PGA topology. Section III provides a detailed circuitanalysis of the proposed PGA’s sub-blocks. Section IV providesexperimental results obtained by using on-wafer measurementto verify the design capabilities. Finally, a conclusion is givenin Section V.

II. DESIGN TOPOLOGY

The proposed dB-linear PGA has a fully differentialthree-stage cascaded topology with two identical DVGA cores,

a post fixed gain amplifier stage, and RC parallel interconnectnetworks with a symmetric RF signal path, as shown in theblock diagram of Fig. 1(b). The DVGA core is a 6-bit dB-linearlow power digitally controlled 11 to 8-dB variable gainamplifier (VGA) with on-chip dc offset cancellation (DCOC)[23]. The corresponding gain control bits of both theDVGA cores are shorted in pairs to provide an overall 6-bitprogrammable gain control. The post amplifier based on thesimilar topology as a DVGA core provides a 16-dB fixedgain with DCOC.The sequence of the PGA sub-blocks are carefully chosen

taking into account the RF receiver frontend to basebandinterface requirement of providing a linear regulated powerlevel over a large receiver dynamic range. This applicationrequirement in terms of PGA linearity specification translatesinto a gain-independent output 1-dB gain compression point( ) over the entire gain control range and the gaindifference has to be reflected in the input 1-dB compressionpoint ( ). For simplifying the analysis, we assume thatthe nonlinearity contribution from the interconnect stages arenegligible and are later verified by the measurement results inSection IV. The determination of the overall is not astraightforward process since the characteristic curve dependson the amplifying devices moving from linear operation intosaturation. The overall is dependent on the cascadedstage with amplifying devices that transits earlier from linearoperation into saturation, and hence, we can estimate the overall

by converting back and forth between the input powerand values with one stage at a time over the entirecascaded chain.The linearity analysis of the proposed PGA topology can be

illustrated from Fig. 2 by neglecting the interstage network.The DVGA core design has a nearly gain-independent mea-sured ( 12.5 to 11 dBm) for the entire DVGA gainrange denoted as in Fig. 2(a) and the DVGA core gain dif-ference is mainly reflected in its as and [shownin Fig. 2(a)]. We consider the and points of thepost amplifier as and , respectively, for illustration pur-poses. For the proposed PGA to be used in the RF receiver fron-tend, the post amplifier design has to ensure that sothat the overall PGA’s becomes gain-independent andwill be approximated to of the post amplifier ( ), asshown in Fig. 2(d). This will transform and limit the cascadedDVGA characteristics from Fig. 2(a) to (b).We perform the linearity analysis of the PGA for both the

maximum and minimum gain conditions as follows.

A. PGA Maximum Gain (B5~B0: 111111’b)

From the post amplifier transfer characteristics shown inFig. 2(c), the of the overall PGA is determined by the

of the fixed gain post amplifier, with itsvalue, determining the maximum output power level thatthe cascaded DVGA core can reach before the post amplifiergoes into saturation. By traversing back in the PGA chain, thecharacteristics of the cascaded DVGA core shown in Fig. 2(b)is limited by with the overall PGA’s set toshown in Fig. 2(d).

Fig. 2. Linearity analysis of the proposed PGA suitable for receiver frontend to baseband interface.

B. PGA Minimum Gain (B5~B0: 000000’b)

From the cascaded DVGA core’s transfer characteristicsshown in Fig. 2(a) and (b), by ensuring that , eventu-ally the overall PGA is determined by of thefixed gain post amplifier ( ) as in the previous condition andthe overall PGA’s set to , as shown in Fig. 2(d).Hence, by ensuring , the overall PGA’s nonlin-

earity, within the PGA gain control range, is reached due tothe early saturation of the post amplifier while the DVGA corestages are still operating linearly.In Section III, a detailed circuit analysis and design consider-

ations for each of the PGA sub-blocks are discussed.

III. CIRCUIT DESIGN DESCRIPTION

The circuit schematics of the DVGA core and the postamplifier that are used in the proposed PGA design havedifferent current biasing circuit ( ), as shown in Fig. 3.The schematic of either the DVGA core or the post amplifierconsists of three fully differential stages that are biased usingcurrent mirrors ( ) from a bandgap reference to obtain alow power design. The intermediate stage is the core commonemitter (CE) amplifier stage ( ) with a feed-forward DCOCand its gain is determined by the current source. Theinput stage ( ) with the transimpedance load ( ) andthe output stage ( ) are responsible for providing a dif-ferential wideband 100- impedance matching with fixedcommon-mode dc voltages that are independent of the PGAgain control [24].

A. DVGA Core and Digital Gain Control

For the DVGA core, the current source consists of ann-channel metal–oxide semiconductor (nMOS) transistor baseddigital-to-analog current converter ( ( to ) to ),and a bipolar junction transistor (BJT) based exponential currentconverter ( to ) that is designed to provide a preciselinear-in-decibel gain control, as shown in the Fig. 3, from 11to 8 dB.

The dB-linear gain of the DVGA core based on the digitalgain control ( to ) is given as

dB

(3)where is the resistance used in the exponential current con-verter, is the thermal voltage of the amplifying bipolar tran-sistor pair , ( to ) are the constant coefficientsof the binary weighted estimation of the linear gain function,

( to ) is the 6-bit digital gain control received fromthe digital baseband, and is the dc current corresponding tominimum gain when all digital control bits are reset (“0”).

B. Fixed High Gain Post AmplifierThe post fixed gain amplifier has a fixed current source

( ) providing a measured gain of 16 dB. The post ampli-fier presents a high over the entire PGA gain tunablerange to meet the 150-mVpp signal level requirement fromthe baseband. To verify the bandwidth enhancement by thegain peaking technique, the post amplifier circuit along withthe parallel RC interstage network at the input is separatelymeasured by on-wafer probing. The measurement results arediscussed in Section IV to highlight the benefits of the proposedinterstage network such as the gain peaking response for thebandwidth enhancement without affecting the wideband dif-ferential matching to 100- impedance and the linearityperformance.

C. Interconnect Network Stage and Bandwidth Enhancement

The matching network is a crucial circuit that provides a goodimpedance matching with low loss for cascading any two ad-jacent stages. In this proposed PGA design, the interstage RCparallel network in Fig. 4(a) is used to interface between theDVGA core stages as well as with the post amplifier stage. Thecircuit operation of the interconnect network can be understoodby following the sequence indicated in Fig. 4(b).1) At very low frequencies close to dc ( 0 Hz), the capacitor

acts as an open-circuit or a high-impedance shunt path,

Fig. 3. Circuit schematic of the dB-linear DVGA core and post amplifier.

Fig. 4. (a) Interconnect stage and (b) circuit frequency response.

and hence the interstage network operates as a voltage di-vider leading to an RF signal loss shown in the Fig. 4(b).

2) As the frequency of operation increases, the impedanceoffered by the capacitor decreases and a shunt RC networkintroduces a zero at frequency.

3) With further increase in frequency, the impedance of ca-pacitor drops below the resistance , and depending on

Fig. 5. Frequency response of cascaded stages: (a) without and (b) with band-width enhancement interstage.

the capacitor value, the network acts as a short circuit withlow signal loss beyond frequency.

4) From frequency onwards, the high-frequency parasiticresistance due to the skin effect of the metal tracesappears and results in a high-frequency pole.

This resulting frequency response shown in Fig. 4(b) is sim-ilar to a gain peaking response characteristics and the networktransfer function is given as

(4)

TABLE ISUMMARY OF MEASURED PERFORMANCE OF THE PROPOSED PGA AGAINST SUB BLOCKS (DVGA CORE AND POST AMPLIFIER)

As discussed in Section I, from (1) and (2), a GBW improve-ment is key for the proposed PGA design operating with a largegain control range in order to support the receiver’s dynamicrange, as well as a wide bandwidth to support high data rate.To provide the improvement in the GBW, the cascaded am-plifier stages of the proposed PGA provides the gain enhance-ment while the interconnect RC parallel network provides thebandwidth enhancement. The bandwidth enhancement is ob-tained by the introduced zero at frequency due to the in-terconnect stage (gain peaking) at high frequency cancels thedominant pole of the amplifier stage that limits the upper cutofffrequency of overall PGA bandwidth [22]. This is indicated byFig. 5(a) and (b). This technique is similar to the amplifier gainpredistortion technique in which the bandwidth is first enhancedby using the gain peaking parallel RC interstage network beforecascading with the next amplifier stage. Thus, the overall PGAbandwidth closer to the bandwidth of the DVGA core (whichis the bandwidth limiting stage) is achieved. This technique en-sures that the gain is not affected much and also the overall cas-caded bandwidth does not shrink, unlike the scenario shown inFig. 5(a) based on (2). This improves the overall PGA’s GBWproduct, which is desirable in the receiver frontend.This bandwidth enhancement technique provides an easy in-

terface option for cascading several such DVGA core and postamplifier stages with very low effect on the gain, matching, lin-earity, and interface dc performance. This technique is also val-idated by the measurement results shown in Table I.Additionally the parallel RC interconnect stage provides a dc

coupling with an additional voltage drop that depends on thebiasing conditions of the output of the previous and input ofthe next stage unlike the interconnect peaking inductors withsmall voltage drop (determined by the inductor -factor) acrossit. Thus, overcoming the loading effect that may also reducethe bandwidth [17] and each stage can be optimized to havedifferent dc voltages.To evaluate this analysis, a plot of simulated PGA’s output

power against the input power at 1-GHz frequency is shown inFig. 6. From the plot we find that the overall PGA’s isalmost gain-independent ( 7.1 dBm) for the proposed de-sign. For the curves closer to the minimum gain condition, thedegradation of the PGA’s is due to saturation of theDVGA core in addition to the already saturated post amplifier.This can be accounted for the condition that(see Fig. 2) and is verified by observing the performancein Table I that summarize the performance of the proposed PGA

Fig. 6. Simulated linearity plot of the proposed PGA design for the 64gain steps at 1-GHz frequency.

against the sub-blocks, namely, the DVGA core and the post am-plifier.The proposed interstage RC network, consisting of a par-

allel resistor and a frequency-sensitive capacitor, is a cascadednetwork which is external to the PGA’s sub-block amplifiers(DVGA core and post amplifier). Hence, the RC interstage net-work does not form a part of the sub-block amplifiers’ feedbackloop and do not affect the stability criteria of the overall cas-caded amplifier chain.The component values of the interstage network ( and )

are to be carefully selected and a design guideline is providedbased on design tradeoffs among the performance parameters ofthe overall proposed PGA design.Factors Affected by the Resistor :• The gain peaking and the resulting GBW enhancement isachieved by choosing a smaller (zero frequency) andpositioning it within the PGA’s passband

(5)

• Meanwhile, the group-delay variation increases as the gainpeaking is increased. In the proposed design, group-delayvariation is compromised by the GBW enhancement and adetailed analysis is provided in Section IV.

• The resistor is along the RF signal path and consequentlya large value of increases the signal loss

Loss (6)

• The interconnect RC network has very small influence onthe overall PGA’s input/output reflection coefficient. Thisis mainly due to the input fixed gain stage of the first stageDVGA core and output buffer stage of the post amplifier.

Hence, a small value of is preferred and the designed valueis chosen as 45 , which along with the shunt capacitor pro-vides the GBW enhancement as well as mitigates the discussedoverall PGA’s performance degradations.Factors Affected by the Capacitor :• As a product with a small resistor , the capacitormainly determines the GBW enhancement based on (5).

• The , which is frequency-dependent resistive loss dueto the skin effect, is determined by the quality factor ofand can be reduced by proper layout techniques such asusing short low-loss thick metal interconnect traces.

• The overall PGA’s upper cutoff pole frequency in-creases as is decreased,

(7)

• A smaller results in a reduced physical layout sizebased on the capacitance of the parallel plate metal–insu-lator–metal (MIM) capacitor, which is given as

(8)

Hence, a small value of is also preferred. However, to meetthe desired gain peaking requirement based on (5) with reducedeffect on the overall PGA’s performance by a small resistor ,the designed value is chosen as 5 pF.

D. Current Mode Gain Control With Improved Accuracy

The proposed variable gain control circuit shown in Fig. 3provides a large PGA gain range with improved accuracy. Thisaccuracy is achieved by using long-channel nMOS transistorsin the cascode current mirrors with the digital nMOS switches( ) stacked above the binary weighted nMOS currentmirrors, as shown in the DVGA core’s block of Fig. 3.By using the current mode gain control, the width and lengthof the layout traces from the gain control block to the DVGAstages as well as from the bandgap reference do not affect thecurrent flow. Hence, a fully differential topology with a sym-metric layout and reduced dc offsets in the RF portion can bedrawn with the digital gain control portion placed at a distancefrom the RF traces.

IV. EXPERIMENTAL RESULTS

The proposed post amplifier design with input interstage net-work and the overall proposed dB-linear PGA with DCOC de-sign are realized by using a 0.18- m SiGe BiCMOS processfrom Tower Jazz Semiconductors Inc., Newport Beach, CA,USA. The microphotograph of the post amplifier with an inputinterstage network and a standard bandgap reference is shown

Fig. 7. Die microphotograph of post amplifier with interstage network at inputand bandgap reference for on-wafer measurement.

Fig. 8. Die microphotograph of proposed PGA with bandgap reference.

in Fig. 7 and the microphotograph of the proposed PGA alongwith the bandgap reference is shown in Fig. 8, which occupies acore die area of 810 m 310 m excluding the measurementprobing pads. The PGA and the post amplifier performance areexperimentally verified by on-wafer probing by using the Agi-lent E8364B PNA network analyzer, RoHS SMBV 100A signalgenerator, LeCroy Waverunner 6000A series high-speed oscil-loscope, and Agilent E4407B ESA-E series spectrum analyzer.

A. Post Amplifier Design With Input RC Parallel Interstage

To verify the performance of the post fixed gain amplifierused in the proposed PGA and also to validate the bandwidth

Fig. 9. Measured -parameters plot of the post amplifier with input interstageused in the proposed PGA design.

Fig. 10. Measured linearity plot of the post amplifier with input inter-stage used in the proposed PGA design at 1-GHz frequency.

enhancement achieved by using the interstage network, a stand-alone testable device-under-test (DUT), as shown in Fig. 7,is measured by on-wafer probing. The measured -parametershown in Fig. 9 suggest that the interstage network does notaffect the input matching significantly and the return loss betterthan 13 dB is achieved over the entire frequency range. Thegain plot in Fig. 9 suggests that there is gain peaking of lessthan 1 dB observed at about 1-GHz frequency that increasesthe bandwidth of the overall cascaded interstage and the postamplifier to 2.45 GHz, as discussed in Fig. 5(b). Based on the

plot at 1 GHz frequency (Fig. 10), the post amplifiercan achieve of 7.1 dBm and of 22 dBmconsuming 9.8-mW dc power from a 1.8-V supply voltage.

B. Proposed PGA Design With Bandgap Reference

The overall PGA design shown in Fig. 8 consumes a dc cur-rent from 18 to 19.6 mA corresponding to gain variation from

Fig. 11. Measured PGA -parameters over the 64 gain steps.

minimum to maximum PGA gain, and during the power-downmode it dissipates a dc current of 915 A from a single supplyvoltage of 1.8 V.Themeasured differential -parameters of the proposed PGA

against frequency for all 64 gain steps is shown in Fig. 11. Theplot suggests that the proposed design has almost gain-indepen-dent input/output matching, reverse isolation, gain flatness, and3-dB bandwidth. The plot shows a uniform step size for thegain emphasizing the dB-linear accuracy achieved in the pro-posed PGA design.The linearity measurement was performed under

maximum, mid, and minimum PGA gain conditions shownin Fig. 12 and the results agrees well with the simulationresults shown in Fig. 6. The degradation from 7.5 to10 dBm is also observed for the minimum gain condition.For low-power transceiver designs operating in the time divi-

sion multiplexing scheme, the proposed PGA can be switchedto a low power mode (consuming leakage current of 910 A)using the power down digital pin shown in the microphotograph(Fig. 8). The turn ON and turn OFF time of the proposed PGAhas a significant contribution in determining the frequency ofswitching the transceiver between transmitter and receiver. Byusing a high-speed oscilloscope, a low-frequency square-waveinput to the power down pin and a single-ended sinewave inputof 1-GHz frequency, the turn ON and OFF times of the proposedPGA are measured and the results are shown in Fig. 13. Theproposed PGA has 1.5- s turn ON ( V) time and116 ns turn OFF ( V) time.The measured low-frequency gain plot (Fig. 14) using a

signal generator and a spectrum analyzer shows a lower PGAcutoff frequency of 3 MHz for both maximum and minimumgain conditions and is mainly due to the DCOC HPF incorpo-rated in each DVGA core and the post amplifier stages.The measured group delay, as shown in Fig. 15 of the

proposed PGA, over the 64 gain steps, has a variation lessthan 30 ps. While pulse-pattern [pseudorandom bit sequence

Fig. 12. Measured linearity plots for maximum, mid, and minimumPGA gain at 1 GHz.

Fig. 13. Measured PGA switching time based on the single-ended outputagainst the power down (PwrDwn/PD) digital input. (a) Turn ON ( 1.52 s)and (b) Turn OFF ( 116 ns).

(PRBS)] generator equipment is currently unavailable in ourmeasurement laboratory facility, an eye diagram is extracted

Fig. 14. Measured low-frequency gain plot for maximum and minimum PGAgain condition.

Fig. 15. Measured group delay of proposed PGA over the 64 gain steps.

from the measured amplifier -parameter data file using Ag-ilent’s Advanced Design Systems 2009 (ADS 2009) EDAsoftware [22] for 1 and 2 Gb/s, as shown in Fig. 16.From Fig. 15, the measured maximum variation of the group

delay for each gain step is more than 100 ps and it is due tothe group-delay peaking observed closer to the amplifier’s pass-band corner frequency. This group-delay variation can be mit-igated by choosing suitable component values of the interstagenetwork at the expense of sacrificing the enhanced bandwidthdue to gain peaking. This can be shown by the simulation plot(Fig. 17) of the proposed PGA’s gain and the group delay in fre-quency domain against the variation of the resistance ( ) usedin the interstage matching network from 20 to 50 (designedvalue is 45 ). Hence, from Fig. 17, we can choose a suitablevalue that compromises between the two conflicting design

tradeoffs, namely, the bandwidth and the group-delay variation[19], [22].The measured PGA gain characteristics against the digital

gain control code suggests an improved dB-linearity and alsothe variation of noise figure, as shown in Fig. 18. The noise-figure performance is not very critical for the proposed PGA and

Fig. 16. Extracted output differential eye diagrams from measured -param-eter data of the proposed PGA for: (a) 1-Gb/s 2 1 PRBS input and (b) 2-Gb/s

PRBS input.

Fig. 17. Simulated gain and group-delay plots for maximum PGA gain againstthe variation of the interstage matching networks’ resistance.

more design emphasis is on gain control range, output powerlevel, and linearity performance.

C. Performance Summary of the Proposed PGA Against ItsSub-Blocks—DVGA Core and Post Amplifier

The proposed PGA is comprised of two cascadedDVGA corestages and a post fixed gain amplifier that are interconnected byusing a parallel RC interstage network. Table I summarizes the

Fig. 18. Measured dB-linear gain and noise-figure characteristics at 1-GHz fre-quency of the proposed PGA.

measured performance of the DVGA core, the post amplifierwith the input interstage, the actual measured performance ofthe proposed PGA, and the estimated results based on the mea-sured performance of the PGA’s sub-blocks. Based on this con-solidated information, we can clearly observe the following.1) A bandwidth enhancement is observed for the post ampli-fier as compared to the DVGA core due to the gain peakingof the cascaded input interstage network included in theDUT (Fig. 7).

2) A bandwidth enhancement in the actual proposed PGAper-formance when compared to the estimated performancebased on (2). Also the degradation of the actual gain basedon the gain estimation of the cascaded DVGA core stagesand the post amplifier measured gain based on (1) is about1.4 dB, which can be accounted for the interconnect losses.Hence, an overall GBW product improvement is observedin the proposed PGA design along with a bandwidth of1.7 GHz, which is closer to the 1.9-GHz bandwidth of theDVGA core sub-block.

3) The of the proposed PGA ( 7.5 dBm) is closer tothe post amplifier’s measured result ( 7.1 dBm)with the PGA’s gain difference reflected in its(from 9 to 36 dBm), which is also the dynamic range.

Hence, the proposed PGA with the two cascaded DVGAcores, post amplifier, and the interstage network has a smallgain and degradation with a bandwidth enhancementresulting in the overall GBW product improvement as com-pared to the conventional cascaded amplifier stages.

D. Performance Comparison With Existing State-of-the-Art

The overall performance of the proposed PGA is comparedwith the existing state-of-the-art designs with comparable gaincontrol range in Table II. The works in [7], [11], [25], and [26]operate in the voltage mode for biasing and gain control as com-pared to the proposed PGA design that uses current mode expo-nential gain control to enhance the accuracy of the dB-linearperformance and current mode biasing that reduces the overall

TABLE IISUMMARY OF STATE-OF-THE-ART VGA WITH WIDE GAIN TUNABLE RANGE

dc power consumption by limiting the maximum rail-to-rail cur-rent to 19.4 mA from a 1.8-V supply. The work in [25], imple-mented in an advanced process technology with reduced powersupply voltage handling capability, has comparable gain rangeand die area. However, the high output linearity in [25] comeswith an overhead of higher power consumption as compared tothe proposed work. Though the work in [23] has improved gaincontrol linearity (which is the same DVGA core sub-block de-sign used in the proposed PGA) as compared to works in [7],[11], and [26], the proposed PGA achieves better lin-earity performance over a larger gain control range, which canbe observed from the small variation in the output voltage swingover the complete gain control range. The dc power consump-tion and the die area in [11] and [26] and are less than the pro-posed design. However, for the purpose of measurement, an ad-ditional output buffer is necessary in the designs [11], [26]. Un-like the analog VGA [7], [11], the proposed PGA can be directlyinterfaced with the digital baseband without the need for an ad-ditional digital-to-analog converter (DAC).

V. CONCLUSION

This paper has presented the design of a 6-bit PGA with alarge gain control range and a post fixed gain amplifier, whichis used as a sub-block in the proposed PGA. Both the designs arefabricated in a 0.18- m SiGe BiCMOS process and measuredby using on-wafer probing. The proposed PGA design, withoutsignificantly increasing the circuit complexity, simultaneouslyachieves an enhanced GBW product and a better lin-earity performance with a large dynamic range, which are desir-able characteristics for the integration in the receiver RF fron-tend of low-cost low-power consumer applications requiringgood gain control precision.

ACKNOWLEDGMENT

The authors would like to take this opportunity to thankTower Jazz Semiconductors Inc., Newport Beach, CA, USA,for providing the fabrication service of the design. The authorswould also like to thank L. W. Meng, Nanyang TechnologicalUniversity, Singapore, for assisting in the on-wafer measure-ment of the design.

REFERENCES[1] M. Tanomura, Y. Hamada, S. Kishimoto, M. Ito, N. Orihashi, K.

Maruhashi, and H. Shimawaki, “TX and RX front-ends for 60 GHzband in 90 nm standard bulk CMOS,” in IEEE Int. Solid-State CircuitsConf. Tech. Dig., San Francisco, CA, USA, Feb. 2008, pp. 558–635.

[2] B. Gaucher, S. Reynolds, B. Floyd, U. Pfeiffer, T. Beukema, A. Joseph,E. Mina, B. Orner, R. Wachnik, and K. Walter, “Progress in SiGe tech-nology toward fully integrated mmWave ICs,” in 3rd Int. SiGe Technol.Device Meeting, Princeton, NJ, USA, Oct. 2006, pp. 1–2.

[3] S. K. Reynolds, B. A. Floyd, U. R. Pfeiffer, T. Beukema, J. Grzyb,C. Haymes, B. Gaucher, and M. Soyuer, “A silicon 60-GHz receiverand transmitter chipset for broadband communications,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2820–2831, Dec. 2006.

[4] J. D. Cressler, “SiGe HBT technology: A new contender for Si-basedRF and microwave circuit applications,” IEEE Trans. Microw. TheoryTechn., vol. 46, no. 5, pp. 572–589, May 1998.

[5] W. R. Davis and J. E. Solomon, “A high-performance monolithic IFamplifier incorporating electronic gain control,” IEEE J. Solid-StateCircuits, vol. SSC-3, no. 4, pp. 408–416, Dec. 1968.

[6] W. M. C. Sansen and R. G. Meyer, “An integrated wideband variable-gain amplifier with maximum dynamic range,” IEEE J. Solid-State Cir-cuits, vol. SSC-9, no. 4, pp. 159–166, Aug. 1974.

[7] C. Liu, Y. P. Yan, W. L. Goh, Y. Z. Xiong, L. J. Zhang, and M.Madihian, “A 5-Gb/s automatic gain control amplifier with tempera-ture compensation,” IEEE J. Solid-State Circuits, vol. 47, no. 6, pp.1323–1333, Jun. 2012.

[8] H. D. Lee, K. A. Lee, and S. Hong, “A wideband CMOS variablegain amplifier with an exponential gain control,” IEEE Trans. Microw.Theory Techn., vol. 55, no. 6, pp. 1363–1373, Jun. 2007.

[9] F. Carrara and G. Palmisano, “High-dynamic-range VGAwith temper-ature compensation and linear-in-dB gain control,” IEEE J. Solid-StateCircuits, vol. 40, no. 10, pp. 2019–2024, Oct. 2005.

[10] S. Otaka, G. Takemura, and H. Tanimoto, “A low-power low-noise ac-curate linear-in-dB variable-gain amplifier with 500-MHz bandwidth,”IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1942–1948, Dec. 2000.

[11] Y.Wang, B. Afshar, Y. Lu, V. C. Gaudet, and A. M. Niknejad, “Designof a low power, inductorless wideband variable-gain amplifier for high-speed receiver systems,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.59, no. 4, pp. 696–707, Apr. 2012.

[12] D.-D. Pham, J. Brinkhoff, K. Kang, C.-W. Ang, F. Lin, and C.-H. Heng,“Feedforward technique for offset cancellation in broadband differen-tial amplifiers,” in Proc.12th Int. Integr. Circuits Symp., Singapore,Dec. 2009, pp. 429–432.

[13] M. Zargari, D. K. Su, C. P. Yue, S. Rabii, D. Weber, B. J. Kaczynski, S.S. Mehta, K. Singh, S. Mendis, and B. A. Wooley, “A 5-GHz CMOStransceiver for IEEE 802.11a wireless LAN systems,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1688–1694, Dec. 2002.

[14] T. B. Kumar, K. Ma, and K. S. Yeo, “A 7.9-mW, 5.6-GHz digitallycontrolled variable gain amplifier with linearization,” IEEE Trans. Mi-crow. Theory Techn., vol. 60, no. 11, pp. 3482–3490, Nov. 2012.

[15] T. H. Lee, The Design of CMOS Radio Frequency Integrated Cir-cuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.

[16] G.Matthaei, “Synthesis of tchebycheff impedance-matching networks,filters, and interstages,” IRE Trans. Circuit Theory, vol. CT-3, no. 3, pp.163–172, Sep. 1956.

[17] B. Analui and A. Hajimiri, “Bandwidth enhancement for tran-simpedance amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 8,pp. 1263–1270, Aug. 2004.

[18] J.-C. Chien and L.-H. Lu, “40-Gb/s high-gain distributed amplifierswith cascaded gain stages in 0.18- m CMOS,” IEEE J. Solid-StateCircuits, vol. 42, no. 12, pp. 2715–2725, Dec. 2007.

[19] J. S. Walling, S. Shekhar, and D. J. Allstot, “Wideband CMOS ampli-fier design: Time-domain considerations,” IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 55, no. 7, pp. 1781–1793, Aug. 2008.

[20] C. Li and S. Palermo, “A low-power 26-GHz transformer-basedregulated cascode SiGe BiCMOS transimpedance amplifier,” IEEE J.Solid-State Circuits, vol. 48, no. 5, pp. 1264–1275, May 2013.

[21] A. Woroncow and J. Croney, “Inductorless bandpass I.F. amplifiers,”Radio Electron. Eng., vol. 33, no. 3, pp. 184–186, 1967.

[22] J. Kim, L. Jolla, and J. F. Buckwalter, “Staggered gain for 100 GHzbroadband amplifiers,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp.1123–1136, May 2011.

[23] T. B. Kumar, K. Ma, and K. S. Yeo, “Temperature-compensateddB-linear digitally controlled variable gain amplifier with DC offsetcancellation,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 7, pp.2648–2661, Jul. 2013.

[24] T. B. Kumar, K. Ma, K. S. Yeo, and Y. Wanlan, “A 35 mW 30 dBgain control range current mode programmable gain amplifier with DCoffset cancellation,” in IEEE MTT-S Int. Microw. Symp. Dig., TampaBay, FL, USA, Jun. 2014, pp. 1–4.

[25] Y. Wang, C. Hull, G. Murata, and S. Ravid, “A linear-in-dB analogbaseband circuit for low power 60 GHz receiver in standard 65 nmCMOS,” in IEEE Radio Freq. Integr. Circuits Symp., Seattle, WA,USA, 2013, pp. 225–228.

[26] R. Kitamura, T. Tsukizawa, and N. Saito, “An 84 dB-gain-range and 1GHz-bandwidth variable gain amplifier using gain flattening capacitorsfor multi-gigabit radio,” in IEEE Radio Wireless Symp., Austin, TX,USA, 2013, pp. 220–222.

Thangarasu Bharatha Kumar (S’12) receivedthe Bachelor of Engineering degree in electronicsand communication from the Ratreeya VidyalayaCollege of Engineering (RVCE) [affiliated withVisvesvaraya Technological University (VTU)],Bangalore, India, in 2002, the M.Sc. degree inintegrated circuit design from the German Instituteof Science and Technology, Singapore (a jointdegree program offered by Nanyang TechnologicalUniversity (NTU), Singapore and Technische Uni-versitaet Munchen (TUM), Germany), in 2010, and

is currently working toward the Ph.D. degree at NTU.Since 2010, he has been a Research Associate with VIRTUS, Integrated

Circuit (IC) Design Centre for Excellence, Nanyang Technological University(NTU). His research interests include RF and millimeter-wave integrated-cir-cuit design and reconfigurable high-frequency amplifier design.

Kaixue Ma (M’05–SM’09) received the B.E. andM.E. degrees from Northwestern PolytechnologicalUniversity (NWPU), Xi’an, China, and the Ph.D.degree from Nanyang Technological University(NTU), Singapore.From August 1997 to December 2002, he was

with the China Academy of Space Technology,Xi’an, China, where he became Group Leaderof the Millimeter-Wave Group for Space-BorneMicrowave and Millimeter-Wave Components AndSubsystem in Satellite Payload and VSAT Ground

Station. From September 2005 to September 2007, he was with MEDs Tech-

nologies, as a Research and Development Manager. From September 2007to March 2010, he was with ST Electronics (Satcom & Sensor Systems) asa Research and Development Manager, Project Leader, and a member of theTechnique Management Committee of ST Electronics. Since March 2010,he has been with NTU, as a Senior Research Fellow and Millimeter-WaveRFIC Team Leader for the 60-GHz Flagship Chipset Project. As a PrincipalInvestigator (PI)/Technique Leader, he has been involved with projects withfunds in excess of S$12 Million (excluding projects done in China). He hasauthored/coauthored over 100 referable international journal and conferencepapers. He is reviewer of several international journals. He has filed ten patents.His research interests include satellite communication, software-defined radio,and microwave/millimeter-wave circuits and systems using CMOS, micro-electromechanical systems (MEMS), monolithic microwave integrated circuits(MMICs), and low-temperature co-fired ceramic (LTCC).Dr. Ma was the recipient of Best Paper Awards of IEEE SOCC2011, the IEEK

SOCDesign Group Award, the Excellent Paper Award of the International Con-ference on HSCD2010, and the Chip Design Competition Bronze Award ofISIC2011.

Kiat Seng Yeo (M’00–SM’09) received theB.Eng. and Ph.D. degrees in electrical engineeringfrom Nanyang Technological University (NTU),Nanyang, Singapore, in 1993 and 1996, respectively.He is currently the Associate Provost (Interna-

tional Relations and Graduate Studies) with theSingapore University of Technology and Design(SUTD), Singpore. He is a widely known authorityin low-power RF/millimeter-wave integrated circuit(IC) design and a recognized expert in CMOStechnology. He has secured over S$30M of research

funding from various funding agencies and industry over the last three years.Before his new appointment with SUTD, he was Associate Chair (Research),Head of Division of Circuits and Systems, and Founding Director of VIRTUS,School of Electrical and Electronic Engineering, NTU. He has authored orcoauthored 6 books, 5 book chapters, and approximately 500 internationaltop-tier refereed journal and conference papers. He holds 35 patents.Dr. Yeo is a member of the Board of Advisors of the Singapore Semicon-

ductor Industry Association. He has served on the Editorial Board of the IEEETRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He holds or hasheld key positions in many international conferences as advisor, general chair,co-general chair, and technical chair. He was the recipient of the Public Admin-istration Medal (Bronze) on National Day 2009 by the President of the Republicof Singapore and the Distinguished Nanyang Alumni Award in 2009 for his out-standing contributions to the university and society.

Wanlan Yang was born in Anhui Province, China,in 1969. She received the B.Eng. degree from theHarbin Institute of Technology, Harbin, China, in1990, and the M.Sc. degree in integrated circuitdesign from the German Institute of Science andTechnology-TUM Asia, Singapore, in 2011.Since 2011, she has been a Research Associate

with VIRTUS, Integrated Circuit (IC) Design Centrefor Excellence, Nanyang Technological University(NTU), Singapore. Her research interests includeSPICE compact model, SPICE modeling, on-wafer

measurements, millimeter-wave antenna design, and RF integrated-circuitdesign.