A 1.62GS/s Time-Interleaved SAR ADC with Digital ...€¦ · Nicolas Le Dortz. 1,2, Jean-Pierre...
Transcript of A 1.62GS/s Time-Interleaved SAR ADC with Digital ...€¦ · Nicolas Le Dortz. 1,2, Jean-Pierre...
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A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving
Interleaving Spurs Below 70dBFS
Nicolas Le Dortz1,2, Jean-Pierre Blanc1, Thierry Simon1, Sarah Verhaeren1, Emmanuel Rouat1, Pascal Urard1,
Stéphane Le Tual1, Dimitri Goguet1, Caroline Lelandais-Perrault2, Philippe Benabes2
1STMicroelectronics, Crolles, France, 2Supélec, Gif-sur-Yvette, France
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Challenges in high-speed ADCs NEED: High speed ADCs for high data rate communication SOLUTION: Time-interleaved SAR ADCs
– High sampling frequency (multi-GS/s) – Moderate resolution (up to 10 bits) – Energy efficient
ISSUE: Mismatch calibration required OUR WORK: Low development time analog/digital co-design
– Analog TIADC core – Digital background mismatch calibration 2
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Outline
• Analog/digital co-design • Classical analog architecture • Digital mismatch calibration • Measurement results
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Analog/digital co-design
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• 12 interleaved SAR ADC – Fs = 1.62GS/s • Background digital mismatch calibration No feedback to analog
x12
Vin+
Vin-
12:4
9 12
SPI Bus
SAR ADC 9 bits
SAR logic
Background mismatch calibration
Digital
Vref clk
Analog
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Outline
• Analog/digital co-design • Classical analog architecture • Digital mismatch calibration • Measurement results
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Classical SAR ADC structure
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Vin+
Vp Vn Vm
Vp Vn Vm
Vcm
Vin-
+ -
128C0
64C0 32C0 16C0 C0
• Radix-2 capacitive DAC • 1Vpp input signal delivered through 1.7V buffer • Latch comparator with 2-stage preamplifier
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Sampling switch
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Vin
Vcm = 0.7V
Good linearity achieved through ‒ Bottom plate sampling ‒ HPA low-Vt NMOS/PMOS transmission gate
Ron
Vin
RVT transistor
HPA transistor
ϕ1
ϕ2 ϕ2
ϕ2
ϕ1
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Custom capacitor array
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16C0 8C0
2C0 4C0
Bottom plate switch & comparator
L L/2
L/4
Top plate switches C0=400aF
• Compact 2-metal-layers lateral structure • DAC linearity ensured by good capacitor ratio
matching
100fF total capacitance
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Time-interleaving
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T R 2 1 5 3 4 6 7 8 9 - T 3 1 2 4 5 6
2 T 1 5 3 4 6 7 8 R 9 - T 3 1 2 4 5 R
5 3 4 8 6 7 9 - R 2 T 1 3 6 4 5 7 2 1
Tracking Conversion Reset
Sampling ADC 0
ADC 1
ADC 11
Conversion & sampling managed by SAR logic • 520ps tracking time • 12 steps per conversion - 1 comparison per cycle
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Mismatch-limited analog output
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Outline
• Analog/digital co-design • Classical analog architecture • Digital mismatch calibration • Measurement results
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Background digital mismatch calibration
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9 12 ADC
Offset calibration
Gain calibration
Skew calibration
• Background mismatch calibration Tracking of temperature and aging variations
• Use of High Level Synthesis (HLS) ‒ Reusable ‒ Parametric ‒ Scalable
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Offset mismatch calibration principle
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ADC 0
ADC to calibrate
Ideal signal
Objective: estimate the relative offset of each ADC
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Offset mismatch calibration principle
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ADC 0
ADC to calibrate
1N� ∑ samples of ADC to calibrate
– 1
N� ∑ samples of ADC 0 =
Relative offset of ADC to calibrate
Ideal signal
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Offset mismatch calibration implementation
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ADC 0
ADC to calibrate
Modified moving average
Modified moving average
Reduction of rounding errors • 12-bit quantized output • Digital dithering to spread residual spurs
12 8 1 7 3 6 11
to 12 bits
to 12 bits
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Gain mismatch calibration principle
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ADC 0
ADC to calibrate
Ideal signal
Objective: estimate the relative gain of each ADC
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Gain mismatch calibration principle
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ADC 0
ADC to calibrate
Ideal signal
∑ samples of ADC to calibrate ÷
∑ samples of ADC 0 =
Relative gain G of ADC to calibrate
ABS
ABS
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Gain mismatch correction
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ADC 0
ADC to calibrate
Modified moving average
Modified moving average
Absolute value low implementation cost vs. squared value
ABS
ABS 1G�
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Skew mismatch estimation
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Objective: estimate the delay Δt for each ADC
ideal signal
Δt-delayed samples
ADC 0
ADC to calibrate
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Skew mismatch error model
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ADC to calibrate
Δt
ϵ
dxdt
Output ADC to calibrate Ideal signal
+ Error ϵ = Δt × dxdt
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Signal/derivative orthogonality
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ADC to calibrate
Ideal signal
+ Error ϵ = Δt × dxdt
dxdt
average
0
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Δt ×dxdt
2
…×dxdt
Parameter to estimate is isolated
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Skew mismatch calibration implementation
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ADC to calibrate
average
dxdt
dxdt
2−1
dxdt
Eliminate signal Recover Δt Subtract error
Δt ϵ
Estimation and subtraction of the skew error term
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Digital derivative calculation
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ADC
• Digital FIR filter of 33 taps • Calculated from the output of all ADCs • Accurate frequency response up to 750MHz
Offset calibration
Gain calibration
Derivative filter
D(ω)
π
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Outline
• Analog/digital co-design • Classical analog architecture • Digital mismatch calibration • Measurement results
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FFT Spectrum – Single tone
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Sine wave -1dBFS Fin = 600 Mhz
Offset spurs ↓23dB Skew spurs ↓23dB
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After calibration
Before calibration
Sine input -1dBFS Peak SNDR 50.7 dB Up to 5dB increase
SNDR vs. frequency
5dB
Derivative filter limitation
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SFDR vs. frequency
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After calibration (only mismatches)
After calibration
Before calibration
Sine input -1dBFS Input buffer linearity limitation Mismatch-only SFDR 80dB Derivative filter limitation
21dB
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FFT Spectrum – Multitone
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6 tones -17dBFS Fin = 334 513 Mhz
Offset spurs ↓29dB Skew spurs ↓15dB
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FFT Spectrum – Modulated signal
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QAM16 modulation Fcarrier = 607 Mhz
Offset spurs ↓29dB Gain/skew in noise floor
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Chip fabrication
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2 x digital mismatch
compensation
MUX 3:1
Demux 1:6
2 x ADC cores
REF BU
FFER
BUFF
ER LDO
DC
AP
DCAP
Isolation
2.03
mm
0.82 mm
Testing
2 x TIADC on chip Mature ST CMOS 40nm technology Area 1.66 mm2
• Digital 0.70 mm2 (42%) • Analog 0.96 mm2 (58%)
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Power consumption
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Total consumption 93mW • Analog: 43.5 mW • Digital: 49.5 mW
FOM 283 fJ/conv
References 6mW (7%)
Offset calibration 2.9mW (3%)
Gain calibration 11.3mW (12%)
Skew calibration 35.3mW (38%)
Analog core 21.5mW (23%)
Input buffers 16mW (17%)
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Performance vs. previous work
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[1] [2] [3] This work Technology 65nm 65nm 65nm 40nm Sampling rate [GS/s] 3.6 2.6 2.8 1.6 Mismatch tones [dBFS] 50 55 60 70 SFDR [dBFS] 50 55 55 62 THD [dB] -55 -58 -55 -58 SNDR [dB] 47 49 48 48 Power [mW] 795 480 44.6 (*) 93 FOM [fJ/conv] 1207 801 76 (*) 283 Area [mm²] 7.4 5.1 0.63 (*) 0.83 [1] Doris, ISSCC 2013 [3] Stepanovic, VLSI 2011 [2] Janssen, ISSCC 2011
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Conclusion
• Successful analog/digital co-design to reduce development time
• Background digital calibration – Reusable – Parametric – Scalable
• Power/area overhead expected to decrease with technology scaling
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Questions?
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A 1.62GS/s Time-Interleaved SAR ADC with Digital�Background Mismatch Calibration Achieving�Interleaving Spurs Below 70dBFSChallenges in high-speed ADCsOutlineAnalog/digital co-designOutlineClassical SAR ADC structureSampling switchCustom capacitor arrayTime-interleavingMismatch-limited analog outputOutlineBackground digital mismatch calibrationOffset mismatch calibration principleOffset mismatch calibration principleOffset mismatch calibration implementationGain mismatch calibration principleGain mismatch calibration principleGain mismatch correctionSkew mismatch estimationSkew mismatch error modelSignal/derivative orthogonalitySkew mismatch calibration implementationDigital derivative calculationOutlineFFT Spectrum – Single toneSNDR vs. frequencySFDR vs. frequencyFFT Spectrum – MultitoneFFT Spectrum – Modulated signalChip fabricationPower consumptionPerformance vs. previous workConclusionSlide Number 34