A 1-Bit Analog-To-Digital Converter Using Delta Sigma Modulation for Sensing in CMOS Imagers

8/2/2019 A 1-Bit Analog-To-Digital Converter Using Delta Sigma Modulation for Sensing in CMOS Imagers

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A IBIT ANALOG TO OIGITAL CONVERTERUSiNG DELTA SIGMA MODULATION FOR

SENSiNG iN CMOS IMAGERS

byBllavana Kol!imarill.

A projectsubmitted in partial fulfillment

of the requirements for the degree ofMaster ofScienee in Electrical Engineering

Boise State University

November,2004


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1lle project presented by Bbavana Kol!imarla entitled A I-BIT ANALOG TODIGITAL CONVERTER USING DELTA SIGMA MODULATION FOR SENSING INCMOS [MAGERS is hereby approved:

R;lCfr-LAdvisor

IZ-5--ayDate

r DateCommittee ber

Sin I DateComminee Member

J R. Pelton DateGradllllte College

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ACKNOWLEDGEMENTS

It is my privilege to do Master o f Science in Electrical Engineering Departmentat Boise State University. I would like to take this opportunity to thank all my Professorswho have provided me with the technical education, guidance and motivation.

1 would like 10 express my deep gratitude to my advisor, Dr. Jacob Baker for hispatient advising and motivation during my graduate study here. I sincerely thank him forhis ellpert guidance, valuable suggestions and support. I also thank Dr. leff Jessing andDr. Sin Ming Loo for being on my committee and fo r their patient advising on thisproject.

would like to thank my parents, for their unconditional love. help andencmuagement and DJI my friends and well-wishers for their best wishes.

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ABSTRACfImage sensors consist of an army of pooto detector elements each of which

transforms a small portion of the image into e1ectcol\S. The pixel produees an electricalsignal (from the charges generated) that is indicati ...c of the image. This analog signal isthen con ...erted into a digital signal by the analog \0 digital converter (18]. Variations inprocess, temperature and noise affect the performllllCC of the sensing cin::uit causing afixed pattern noise on the image. The main goal of this project is to design a low powerlow noise lbit analog-to-digital converter (AOC) using delta sigma modulation (DSM),whieh is robust with process variations and power supply noise.

Project G(lal To design an AOC dn::uit that determines the intensi ty oflighl applied to the CMOS

image sensor using an a ...eraging technique. To design a circuit using simple signal processing that is robust with temperature,

noise and other process variations.I>rojett O ~ I l l U a l i ( l n

llJ..is project is divided into S chapters.Chapter One describes the basic principle of CMOS image sensors, pixel circuits and theimage sensor lImIy. Chapter Two gives an introduction to the DSM technique, some othersensing techniques using DSM and the need fo r this sensing technique. Chapter Threedescribes the individwd building blocks of the design; the NMOS source followers,


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cum:nt mirror, feedback circuit and comparator design alld also eovers tlte completedesign of the circuit. Chapter Four describes the simulations results obtained for thedesign. It also discusses tlte layout oflhe circuit. Chapler Five eontains the conclusions ofthe design.


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TABLE OF CONTENTS

ACKNOWLEDGMENTS ........................... ................................................................... .111ABSTRACT .................................................................................... ................................. IV

Overview of he Project ............................................................................................. IVProjcct (jaals ......................................................................................................... iV. 0 . . .~ r o J e c t rgam7.a tlon .................................................................................................... IV

LIST OF TABLES ............................................................................................................ ixLIST OF FIGURES ........................................................................................................... xLIST OF ABB REV IATIONS ............................................................................. .......... ... xvLIST OF SYMBOLS ...................................................................................................... xviCHAPTER I: BACKGROUND .. ......................................................................................1

CMOS Image SenSQrs .... .. 1CMOS Camera System ................................................................................................ 1CMOS Pixel Circui1.'l .................................................................................................. 23T Pixel ..... .................................. ............................... ................................. ........ .44T Pixel ................................................................................................................. 5I>inned I>hotodiode .................................................................................................... 7ADC lmplcmcnllltion............................................... . ..........................................8Column Parallel Architecture for AID Conversion ................................... . ....9

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CHAPTtR 2: INTRODUCTION ..................................................................................... 10to.I Modui lltorl .................................... ............................... .................. , ................. 10

CllAPTER 3: SENSE AMPLIFIER DESIGN ................................................................. ISSystcfn Block Diagram ......................... _ ..... ................................... _ ......................ISVoltage to Current Conversion ..._ ....... _ ................ _ ....._._ ......... _ ........ _...... IIUnearit'J orNMO S Source FoUoYm"S......._ ..._ . _ .........._ ........ ___ ......_ ....... .20Cwrent Mirror, ._ .. __ .__ .......___ _................................ _ .... _ ...._ .. _ .......... .23SlIIilChied Capacitof Cin:uil _ .__ _.__ ._._ ..._ .... _ .__ ..._____ _....25N o n 4 ~ t b p p t n g Clock Generator_____ .__ _ ._._ ._ ...___ ...__.... ..21

s.mpling Reference and Intensity Signab _______ ___ ._ . . ._ .....37Charge Injection aod Clock Feed llvougb___ ... _ .._ ......_ ._____ ..31St.7v.i",Chargc Injedion.t Clock Feed llvougb rom theTGs_ ._ 40Simple SIB Citcuit.___ _ ._._ .._ ..._.________ _.__ ...._ .__ ,4111len1l1l1 No ix, .__ .....___ _._._ ._.__ .._.. _ ...._ . 43eomp.r.tor DI:5Ign ...._ ._ ......__ ... _ ......... _ ..__ ___ .._._._.__ ._._.__ 4SSc1I$IU\';ly of the Com.,-atDr ..... _ .................... _ ... _ ..... _ ...M........... _ ........... _ M.SOSimulating the Clock Feed Through Noise & Kickback Noise: of he ComparalOf_S ISho wing the Schematic Used for the Dcsign........................................ _.................54D S ~ Sensing Circuit , ........................................................................................... 56

CHAPTER 4; SIM ULATION RES ULTS, LAYOUT OF THE ADC ..............................60Showing the: Output of the DSM xnsing circuit .................................. ...................60

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S e l 1 5 i t i ~ i t y 10 VOO and Ground Noise .. .... ...................................................................63Resolution Oflhc DSM ............................... .... .. .... ................ .... ... ..............................66ShoW1111 the Count gcnerotcd by the sensing cin::ui!... ................................................611Comparison of voltages hand cales and sims generated by the sensing dn::uit.. .........69Simut.ions oflhe Sensing Circuit for Different Sense .............__ ._ .... _ .......75Simulalions ofthc Sensing Cimlil II Higher Frequencies ...........................................75Tempcratun: S e n s i l i ~ i t y of the Sensing Cireuit.. _ .__ .._ ........__ ..... _ ............ _ ......nSimuJaions orlhe Senstng Circuit at Lo ...n VDD ........_ ......_ ....._._ ...__ ...7.la)'O'-C of the Delta Sigma ADC _ ..___ _....__ ......._ ..._ _ .._ ._ .__ ._ .79

CHAPTER 5: CONCLUSIONS _ ._ ._ ..__ _ .____ .._.__ ._._ ._. 81

~ 1 1 1


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LISTOFTABLES.Table 4.1. Cak:ulated and Simula1M $I.pls ror conswu rrlerax:e ~ I . and dirremd_pal mltagtes .___ ._ ._ ..______ ._ ..__ __ __ ._____ . ._67


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LIST OF FIGURESFigure 1.1. Typical CMOS c:amem system .._ ... ..... ......_ ............. ......................_ ....... _ . 2Figure 1.2. An:hilecture of an APS ....____ .... ..............._ .................. _._ .............__ .- - 3Figure 1.3. Schematicof. 3T APS.....___ .. _ ... _ .___ ..... _ ..... _ ..... _ ....... _ ......_ _ _ 4F i ~ 1.4 Schenwic of. 4T APS_ .._._ .... _ ......__ .................. .___ .......___ _ . . .6Fiaure 1.5. APS wilh. pinned pboIodiodc ....._ .. _ ..__ _ __ _._ __ __ _7Figure 1.6. CoIwnn Parallel ArclIiIel:Nft: (01" AID Con,-nsion in . CMOS imager._ ..._ 9Fiaurr 2.1 . F'1fSl Order b1: modulatoc-__ _.___ _ .__ _ .......__ ___ ...____ 1figUR 2.2. BIoc:Jt Diagram of 0\'eI" samplai AID coovmc:rs___ ... ____ 1figure U . Simulation nosuIu of ho .&.1: ADC .. _ .._.__ ..__ ....._._ ._._ .__ "Fiawe 3.1. Scnsilli Cin:lllt Blod: Diapm .__ __ _._____ _ _ _ _._ .. _ 15Figure 3.2. Vohage 10 CutTaU Conversion_____ __ ______ ____ 1Ifigure 3.3. Voltage 10 CUflmt coovcrta" ... th SCR ..... _ .......__ ._ ... _ .. _ .......__ .. _ .._19Fiautt 3.4: AC analysis oflbe SF...._._ ......._ ........._._ ........._ ...... _.... .......... . ........20Figure 3.5. OuiPUI Voltage oflhe NMOS SF with body effect for W " 20, SO. 100 ...... 21F1GIIIll 3.6. Gain orlbe NMOS SF with body effect for W W. SO, 100................... _ 21Figure 3.7 .Output Voltage ofthc: NMOS SF ... ihoul body effect for W .. 20 , SO. 100 .. 22Figure 38. Gain of the NMOS SF ... lhoUi body effeet for W " 20. 50. 100 .......... ...... _22FillUfC 3.9. PMOS cWTCnt mirror .......................................... ............. ...............................23FiGure 1 10. Varintion ofReference lII\d Signal currents in the cum:nt mirmr ......... .... 4


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Figure 3. 11 . Switched Capacitor Resistor.............. _ .. " ........ ....... ........... .... .................... ... .26Figure 3.1 2. Switched Capacitor Circuit ............ .. ....... ....... .... .................... ... ............... ......27Figure 3.1 3. SCR Operation ............ ..._............................................................................. 27Figure 3.14. NonOverlapping Clock Oenerator ...... ................................................... ...... 28Figure 3.15. Simulation showing the NonOverlapping Clocks generated from thegenerator .................... _._........__...... .... ........ .... .................. ... ....._...................................... 29Figure 3.16. Feedback Cireui t............................................................................................ 30Figure 3.17. CUrTCn1thrOUgh the bi t line voltage souro: ................................................. .30Figure 3.18. Showing a Single Current p u J ~ .................................... .... ...... .... ....... ... ..... 31Figure 3. 19 . Feedback Cireuit with the NMOS source follov.'CT ................... ................... 32Figure 3.20. Current through the bit line voltage source .._........_........ _. __....................... 32Figure 3.21. Incomplete Settling ............................ .......................................................... 33Figure 3.22. Lowering Clock Frequency to reduce Incomplete Sellling ..... .. ................... 34Figure 3.23. DSM Input Cireuit ........................_..........................._._._. _._ .. _ .................... 35Figure 3.24. Showing the shi fted reference and signal voltages .......................................36Figure 3_25. Showing charge injection ............................................................................. 38Figure 3.26. Sho"'1ng clock feed through ......................................................................... .39Figure 3.27.TO................................ ...................................... _ ...........................................40Figure 3.28. Clock Feed tluough ofTO ........ , ................................__...... .............. ......... .40Figure 3.29. Clock Feed through ofTO ........... , ...... ... ........ ... .......................................... 41Figure 3.30. Sample & Hold Operation .................................. , .. __ .............. , .......... 42Figure 3.31. Showing reference and signal vo ltages after sampling .................................42

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figure 1.12. Modeling noise in a RC low pass filter ........................................................ 43Figure 3.33. Comparator Circuit ........................................................................... ......... .45Figure 3.34. Showing the operation of the comparator in figure 3.33 ............................... 46

Figure 3.35. Showing the operation of the comparator io figure 3.33 ...............................47Figure 3.36. Comparator Circuit with SR Flip-flop ................ .................. ................... .... 48Figure 3.37. Showing the operation ofcircuit in figure 3.36 .............. ............................. .49Figure 3.38. Showing the clock,inputs and outputs of circuit in figure 3.36 ..................... 50Figure 3.39. Showing the Clock feed through Noise of the comparator .......................... 5 IFigure 3.40. Showing the Clock feed through Noise of the comparator .......................... 52Figure 3.41. Showing the Clock feed through Noise of the comparator with capaci tors ..53Figure 3.42. Showing the Clock feed through Noise of the comparator with capacitors ..53Figure 3.43. Schematic of the OSM .................. ................................................. ...............54Figure 3.44. OSM Sensing Cireui!. ......................................... . . ............................56Figure 3.45. Showing the signals Vren, Vsigl and output Q from the sensing circuit ....58Figure 4.1. Showing the Output of the DSM sensing circuit of figure 3.44 ...... . . ...61Figure 4.2. Output of the OSM sensing circuit offigurc 3.44 .............. .................... ........61Figure 4.3. Output of the OSM sensing circuit of figure 3.44 ...........................................62Figure 4.4: Output of the DSM sensing cireuit of figure 3.44 .......................... .................63Figure 4.5. Output of the DSM with VDD Wld ground noise for Vsig-J.1V ........ ..........64Figure 4.6. Output of the OSM with VDD and ground noise for Vsig=2.! 5V ..... ...........64Figurc 4.7. Output of the DSM with VDD and ground noise for V s i g ~ 1 . 6 V . . ....65Figure 4.8. Output of the DSM with VDD and ground noise for Vsig"'


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Figure 4.9. Showing the Count generated by the sensing cireuit of figure 3.44 ............ _.69Figure 4.10. Compar ison of voltages hand calcs and sims gcnernted by the sensing cireuitof figure 3.44._. _, ... , ...................................._.............................................................. " ..70

Figure 4.11. Compar ison of voltages hand cales and sims generated by !he sensing circuitoffigure 3.44 ......................................................................................... ...........................70Figure 4.12_ Showing the Count generated by !he DSM of figure 3.44 for differentreference voltages ...................................... _................... ................... ................... .......... ,70Figure 4.13. Showing !he Count generated by the DSM of figure 3.44 fOT differnntreference voltages ............................................................................................................71Figure 4.14. Comparison of voltages hand cales and sims generated by the sensing circuitof figure 3.44 ...................................................................................................................72Figure 4.15. Compar ison of voltages hand cales and sims genernted by !he sensing ci rcuitof figure 3.44 ................................ _.... _. .. _ .......................................................................72Figure 4.16. Comparison of voltages hand cales and sims generated by the sensing circuitof figure 3.44 ........................................................................... , __ -._................................ 73Figure 4_17. Comparison of voltages hand cales and sims generated by the sensiog circuitoffib'llre 3.44 ....................................... . . ......................................................................73Figure 4.1 8. Comparison of voltages hand cales and sims generated by the sensing circuitoffigure 3.44 .... __ ..... ............. _ .. . ............................. .................................................. 74Figure 4.19, Comparison ofvohages hand cales and sims generated by the sensing eireuitof figure 3.44 ............ .............................. ............................. ............... , ....._..................... 74

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Figure 4.20. Comparison of voltages hand cales and sims generated by the sensing circuitof figure 3.44 .............. ... ... , ........ ............................................ . .. .. 75Figure 4.21. Simulations of the sensing circuit of figure 3.44 for different sense times ... 76

Figure 4.22. Simulations of the DSM of figure 3.44 at higher clock frequcncies .............76Figure 4.21 Simulations oCthe sensing circuit for different tcmperatures ......................77Figure 4.24. Simulations of the sensing circuit for lowcr VDO ........................................78Figure 4.25. Chip Layout with the tcst structures ofthc Delta Sigma AOC ............. .......80

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LIST OF ABBREVlATIONS. S U ' .BSU .H H ....... ................... ....... ...... .... ....................... .........Boue late mVCfSlty.

MOS .. ...................................... .. ................. ........ . - ............... Metal Oxide ScmicondUCIOf.PMOS _ ........_ ... ... .._._ .............. ... ... ..... P-


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LIST OF SYMBOLSVDD .....__ _ ....... _ _ ._ __ ... _._ _ _ ._ ....... _ .. _ .._ ..Suppty VoltageI ' " " ........ "'"' """"'-V," DraiI1IO Souta:: Voltage..V ~ , 1lu!:shokl Voltgc .Vol Source 10 Drain Voltage.V., Gate 10 Source Voltage.Yeo! Column Voltage.

Ktfercnce CurrenlIsiS Signa! Currenlq Charge.

""Switched CapacilO r Resistance.

"'"'CI""-

A Am,.,.,.T T = - ~ V Voll.!.m Mi!lip p " ," Micro.,


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r F ~ m I O

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II

C I ~ T E R l : 3 A C K G R O U N D C MOS Image Senson

The science of converting an image to a signal that is indicative of the image islmagmg. Imaging systems have applications in the o o m m e ~ i a consumer, defense,medical, industrial, rmd scientific fields including mobile video communications andother hand beld devices. Size minimization, power consumption, and integrating multiplefunctions within the camera module are some of the huge challenges in such applications.Image sensors consist of an IIrray of photo detector elements each of whic h ltansforms asmall portion of the image into electrons. The pixel produces an electrical signal (fromthe charges genemled) that is indicative of the image. This analog signal is thenconverted into II digital signal by the analog to digital converter. The major reason for thegrowing interest in CMOS imagers is that they aHow a higher level of integration. Theycan also be operated at lower power supply voltages and consume less power wilencompared to charge coupled devices (CeD). The eel) devices have their ownadvantages in terms of performance and image quality {II [3] [19].

C MOS CII-mem Sy5trmA typical CMOS camem system [3] is shown in figure lot. Light from the image \0 berecorded is captured on to image sensing elements using optics (a lens is used to fOCllS theimage) . The light from the optical system is convened into an electrical signal by theimage sensor (by the pixel). The electrical signal is then processed by the signal-proces:sing module (like an ADC) into II fOlmat lhat is requi red by the display unit [3J.


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11II

2

S_

0. ' . 1""' '''o=mgl 0_ .1_1Figure 1.1. Typical CMOS nmCMI M)'stern

The image sensor and the analog to digital convener arc discussed here.A CMOS active-pixel image sensor contains a photo-detector clement (a

photodiodc or a photo gatc) and an active transistor (1Ul amplifier) for readout oflhe pixelsignal. A pixel converts the signal from the photodiodc inlO a fann thai can be read outby the addressing circuit. When ]ight is incident on a phOlodiodc it is converted intocharge and a phOlocurrcnt is produced. The various readout methods for the CMOSactive pixel sensors (AI'S) are the a) curren! mode readout (where the pholocurrenl isread out directly - difficuli approach due to the small phOlocurrents). b) charge

integration and volLage readout (the phO\ocum:nl is c o n v ~ r t e d in to a voltage byaccumulating it on to a capacitor-most common approach), c) charge integration andsensing readout (the photocurrenl is integrated on a capacitor and the charge is read outdirectly-difficult approach), and the d) resistive curren! to voluge conversion method (thepoolocurrenl is converted in to a voltage by a large resistive load - resistor matchingbetween the pixels can become difficult) [3 J. In this project a delta sigma AID converterfor use with a voltage mode pixel has been designed, fubrieated and tested.

CMOS Pixel C ircuit!CMOS pixels can be divided into two groups a) passive pixel b) active pixel (photodiodeIype & pooto gate type). l1te passive pixel or I -transistor (I'n contains no amplification.


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J[I is the sIm ples t of aU Plld lias II $lngJe lr.lnS is\or and II poolOd\ode but has noise andsensitivity problems. The active pi:


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III

,JT Pi n l

A NMOS 3T active pixel [41 is shown in figure 1.3 . When RST goes high Mlturns 011. The voltage across tbe diode i$ 5ClIO VOO and the photodiode is reverse: bLased .When the row .select RS goes high the voltage (VDO-Vp of MS) ruOOut on to thecolU/JUl line by the $OW'Ce follower MS . This is the dark or the n:ferrnce vol. of thepixel sina: the .:.cumulated charges OIl the photodiode l i te drained OIl!. Ailcf. suiubkintegration time (pbo1On lIt(:umu1atioo time) COIIIrOUcd by the RST ltaNisUlr MI photo

the dc:5Iml signallha! 10 the intmsity nflight applied to the pboIodiode. TheRS lind RST si&fl&ls sboukI be driva'l to voltages greaaa than von 10 fi.dly IUm Oft theN M O S ~

JDD YDD

When the RS Sig.naig0e5 high this \'()hage is sampled on 10 the column line. Theperformance of he sour r o l . l o " ~ u critica.lIO obtain a good gain and band..-idth of thep,xel's output. Increasing the width of the 'lIJurce follower (SF) incn:ues the gain butdecreases the bandwidth of the pixel. Increasing the width of the RS s,",'ilCh tuluces ils


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5'on' resistance and helps in increasing the gain and frequency bandwidth of the pixel'soutput. Increasing the width of the SF decreases the gate \0 source voltage and holds ilmore close to the threshold voltage thus giving a better conversion. Threshold voltagevariation of the source follo ... eT causes non-linearity in the pixel. Fixed pattern noise (a11Qise pattern observed on the captured images), arises due 10 variations in thresholdvoltage of source follower, dark current and IIf noise. This is a common problem with 3TAI'S. The correlated . double sampling (CDS) technique is employed 10 remove fixedpattern noise in the pixels. [n CDS technique the pixel's reset value is subtracted from thesignal value 10 remove the offset. non-unifonnitics and the threshold volUige of thesouree follower in the pixel [11!3J [" I [5) [6].

4T Pi,elA 4T pixel is shown in figure 1.4. By turning on the M I (rescl transistor) and MG(transfer gale) the photodiode is reset and the reference voltage is readout to the columnwhen RS goes high. l1le transfer gate is then shut ofT and the integrated eharge is storedon m., pholOdiodc. After the eharge is stored the trarufer gate is turned on and the desiredsignal that com:sponds 10 the inlensi ly of light is readout on 10 the column line. Thephoto-generated electrons are converted into a voltage by the source follower. Thenumber of volts per electron is the conversion gain. The conversion gain is increased andnoise is reduced here since the capaeiumce at the sense !lOde (gate ofMS) is reduced. Thereduction in the capaciumce is because of the isolation of the photodiode capacitance bythe trarufer gale [1)[3J [4/ [5) [61.


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6

roD

Figure 1.4. Sc:hematic or a 4T APS


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7

P i o o ~ Pholodiod"Figure I.S show, the schematic of the APS .. th II pinned pbotodiode

implerncnl3tion.. The photodiode is implemmld using. pinnal diode in order to reducethe dartt current (a ICmpenllure dependant c:unmt that is still prtxol ",ben thepbotod:odc i , n:Ver$e biased). n o i ~ and 10 ha,'e' high quantum c:fflCieney thus tIciIic:ving high pcrl'onnanc:e pixel It eomisls o f . pinnal. diode (p' -n-p) ..here the photons arecoI1ec:ted away from the s u r f ~ IhLl!l reducing noix due 10 dart c:wrmL 'The cbIrtcgenmated by the phocons is uam.ferred 011 10 the f\mting diffusion for The~ I t a n c : c : on the ~ l i " , diffusiOli node (pte ofMS) is eritieaJ sioce havins 100 !up.

signal ....iIen the full ctwx


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AOC hnpl emenlll.tionCMOS !milicI'S allow the integration of analog to digital conveners on I single die. ThevariOUSlpproaches for implanenling ADC's ... th active p i x e l 5 e l U Q 1 ' S ~ : (JI

8

I. Colwnn level analog 10 digital r o n v e ~ r : The APS lIIT1!.y consists of an ."..y ofADC's lIllie bouGm. One Of JI1(JI'e columns oflhe pixel amy $han; . 5inaJe AOCin this approach. Genetally aU the AOC's "'ill be operaung ID ..,aI1e1 thusallowmg low Of medium $peed AOC to be used. Mismatch of the eonvenns I 1M: columm and lining !be AOC in the pixel pitch an: !he tomro:xI problems....ilh this method III

2. Clup-kwl anaIo& 10 digital 0Dn\'fttef: Here single AOC is fOf !he m&iteAPS amy. This metbod mi.ni.rnia-s Iayotn area but requires a higb sp:ed pipelinedAOC ifthc APS.my me is bigfJ).

1. P l J C c I - ~ 1 - ' o g to digital c o n , ~ Eac:b pixel is cbignro ""1m il3 OYI'TIa;JIl\'Mer This method has various .t\"atlJageI O\"t"r the column and chiplevel AOC . II 0CIn$lln'IC:S loY. power ... Ofts ",ith low \'Ullage. has the ablhty 10obse,,"e the pixels outputs eontinuously and bas high Sl\'R. Abo very lowspeed ADC can be used \00lth these a n ; : h i ~ [J J.


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9

Column PlIfaIlel Arclutectute ror AID COIwersion [IIJ for CMOS imaae: SC'Tl5On issbo ...T1 in figure 1.6. At the in\aXCtion or every row and eoIumn I i ~ we haW'. piled

QODOeClCd to one enure column shares singk Aoc. A StngJe row is .ctivalCd III tmeand the eohnnns m: readout in panalici

_ AID Converte>" Anay

Figun 1.6. ColumQ PI,..llel Arc:bicHlure: for AID COD'"e:nion in a CMOS Imager


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CIIAPTER2: INTRODUcnONAt Moolllalon

to

Then! I IR ,evmtI approaches for designing RMIog to digital c o o v ~ (AOC)like siama-dclta, suecessi,'c approximafioo, and singk sIopdduai slope techniques. AIX:an:tuteelll/'eS like 5''CC''Ssh-e approximation e o n ~ r t e r 5 and dual-slope convcrtm pro\idetugh resolution at the cost of using high precision sample and bold circuits. hiah-spttdm j high lOCUraCy Inll:gratotS. Laser trimming of eomponenu is mjuiml for IheIeN)"quist Il\lc convmas (or KCWBC) .... tboul .... hid! tbcx arcluleCtlRS anncH IximpIemmed in the current Ie technology 110]. ( } \ ~ sampling siglN delta ADC', usesimple data COf\"ersion CIR:uiuy in pbcc of precise and wmpIu analog romponcnlS and

kip restitution.. S i ~ dcltl ADC's i lK pn"ferRd O\ 'c r the trldilionalardUlUIta h.,_ of their a''el''8&ine nalUI'e. v..iUch makes II IJI(II 'e robust 10 CMOSpnx:dIJ ,..nations, and the)' ""IlIlre las componcnlllCCUlXy (111.

The block of .. typical fint Ofder one-bit delta-sigma lA-II modulal(lf112J is shown In figure 2.1. II consists of lUI inkgralOr and .. quanliza. The integratOrlakcs the difference bet,,'el'I\ the input and the output signals. The quanti7.er isimplemen:ed with. 'bit comparator, which COR,eltS IU'I ana log signal to a high. or a lowsignal value. The input signal is firs t sampled, quantized and then digitized 12].


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I I

!nl.,gr&lOr- +(9)-----.1


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12

limited ap-amp bandwidth afTe;ct 10 p;'


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l3

OUL The capacitors on the input of Ih!: comparator average out the noise. The comparatorgain is nOl important here, as the error will be averaged out wi th lime. The sense can berun indefinitely ;0 this sensing technique: and increasing the sense lime i n c ~ theresolution. Errors due 10 thermal noise will be avemgcd oul by sensing for II. longer limethus iocreasing the signal 10 !lOise ratio.

A low power, low noise, I-bit analog-to.digi ta l convener (ADC) usmg deltasigma modulation (DSM) techniques to be used wilh II. voltage mode CMOS imagingpixel anay has been designed. NMOS source followers arc used fo r linear vo ltage \0current conversion. A switched capaci tor resistor topology is used instead of a resistor tominimize layout Mel!. and 10 overcome design challenges. The I:ornparator circuit used tocompare the reference and the intensity signals has II. good sensitivity of around SmV.The power consumed for each coiwlln is around 600uW.The design has good linearitycluuacteristics, low power consumption. low noise, flO buffers and a simpleimplementation. The eireuit is implemented in a O.Swn AM I CS process technology. '!beproposed DSM sensing circuit is applied to CMOS imaging sensors to measurc lightintensity applied to a pixel.

ADC's ~ e p t an analog inpul voltages or cum:nts and converts these inputs intoa digital value. The reference and the signal 10 be measured are the inputs to llie ADC andthe output of the AOC can be given to a counter which counts the nwnbcr of high's of theDSM circuil and gives a digital word representing the input. A sigma del ta ADC has ahigh resolution and il takes a number of inpul samples 10 converge on II result. Averagingfor II longer time gives an OU[PUllha[ is eloser [0 the inpul and also reduces the errOr.


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III

14

This sensing design is robust with variations in process shifts, threshold voltages,tempenlture, capaeitances. comparator offsets and has a good sensing accuracy. Theresolution increases with increasing sense times and sampling for a longer period.

This cireuit gives a good conversion for voltage ranges from 3.2V (Black) to O.7V(bright). The perfonnance of the ....}; ADC shown in figure 2.3. The reference voltage isheld at 3.2 V and the signal voltage corresponding to the desired intensity voltage fromthe pixel is varied from O.7V to 3.35V. We see that the hand calculations match thesimulation results giving a good sense for these voltage ranges.

Ou tput Voltage v . lnput Voltage Vref..J.2V, Vthn=O.13V, , - ----------------------------- ,

O.!' U l l.6U 2 U2.42.Sa 3 3.2U 6Input Voll.ogo

Figure 2.3. Simulat io n results of tbe d-E ADCIn NMOS source followers the lillcarity is alTected because the body effect cannot

be e1imillated. A comparator is used to determine which of the two voltages the referenceor the desired intensity signal paths is greater. The output of the DSM can be given to acounter, which can be thOUght oCas B digital filter.


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IS

CHAPTER J: SENSE AMPLIFIER DESIGNSYSTEM BLOCK DIAGRAM

The block. diagram of the DSM sensing circuit is shown in figure 3.1. A CMOSimager comisUi of u pixel anal' in which each individual pixel consists of a photodetector element 10 convert a ~ r t a i n intensity of light in 10 voltage. The photodiodc iJ.fil"$l =c t to . looltage (VOD) this is the refe=ICe voltage !hat is readout on 10 the imagermtumn. The pboto diad!: is Ibm oola!a;i for c:enai.n amount or aposure time durin&.... bich the junction capaciWlCa .re disdwgcd by tho:: light intmsily. 1be signal \'Ollare~ I l i to litis desired mttnSlty orlight is then sampled on 10 the column line..

DEllA SlGWAA.'W.OG to DlCilTALco.,,\U1a

""" ....., ..... ........... - _.. - f.''''1D c.r..h- "'" "'"'"'- s....it OSM o.p"s- ... ,.... "'" 1....

..."'" - _. -..0.......,. - "'" c-F i c u ~ 3.1. StOliDl Circuil Ulod Diall1lm

A common row line is connected 10 all the KCCS5 InInSiSlOrS in I row in order toread and all the: pueds in the same row simultanrously. ARer an aposwe time the


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stored charges on the photodiodes in the same row are read out simultaneously on 10 thebit line. Each bit line is then connected 10 an ADC 10 sense the bit lillC voltage [8]. Herewe are des igning a novel sensing circuit to determine the desired signal voltage on thecolumn line of the imager corresponding 10 the intensity of light. The DSM output is a 1-bit digital representatiOJl of the desired signal voltage indicative of the inteJlsity of light.Figure 3.1 shows the block diagram of the delta sigma analog to digital convener thatsenses the column voltage from the pixel. This column vollage indicates the amount oflight irn:idcnt on the photodiode when an image is captured by the camera.

The reference and the signal voltages from the column line are first sampled withthe sample and hold circuit shown in the block diagram. These voltages are then given 10the voltage to current convener block.

An NMOS common drain amplifier performs the voltage to current conversion.The reference aod the signal voltages Me convened into currents 10 isolate the sensingcircuit from the pixel voltages. The reference and signal currents arc then applied 10 thesigma block.

The difference in the reference and the desired signal currents is sununed in thesigma capacitor. The difference in currents is to be taken in ortlcr to subtJact OUI thevariations in threshold voltage of the souta: follower from pillel to pixel [2]. The voltagefrom the summing capacitor is then applied to the sensing circuit block.

The sensing circuit is a docked comparator with the SR latch that compares thevoltages from sigma capaci tor and the reference signal path. The comparator isimplemented with PMOS input transistors and the transistors with higher gate vollageSOllrCes lower current. The output of the latch is used to enable the feedback circuit.


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17

TIll: feedback circuil is implemented with a switched capacitor circuit, whichremoves a precise amount of charge. The feedback circuit tries to adjust the current in thereference and desired signal paths until they are equaL The desired signal correspondingto the intensity of the signal from the pixel can be determined by comparing the desiredsignal current \0 the reference signal current and by averaging the number of limes theswitch in the feedback path has been enabled \0 equalize the currents.


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18

V o l l a II) C urrt rll CODn!nionThe refe=\C'.C and d t s i ~ vo1tases from the column line: in the pixel are

convc:ncd in 10 wnmts by the NMOS JOW'CC follo,",w (SF). Figure].2 sho"'S the inpulcircuit [2] used (Of the design. 'o\itK:h performs the voltage 10 curmlt conversion. MI isan NMOS soura: folloWl:r .. . tich perfonns the ~ v l t a g e 10 current coavasion.

Ima&u CoIo.... V

..... V e ~ V r t l or VsilPh"" r;;-S_ ;:r

RowSded

v,,,

~ i g

, IChold :&

L ,Chaldt

',ofMI....llrer ..Vuf -Vlbl1Rlcf

VOD

Rsil

M2""'"

In this design resistor is replaced with. no.ildJtd capacilOr resistor (SC Resistor].

Figwt' 3.] mo.'S the input cin:uit (2] with the n-sistor implemented using aswilChcd capacitor- resistor. a PMOS device ",;!h ga le drain and bod)' shorted 10 VOD isused for the capacitor.


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, Vul ICboJd&

, VsigIa . o J d ~

VOD!l r ~ f = (Vref-Vthn)f Csc

POl8EPphi2.& CscVOD! sig = (Vsig-V tbn)f C5C

F i g u ~ 3.3. Voltage to currenl con,erter with SCR

19

A reference voltage has to be stored before the sense after which the signal fromthe pixel is sampled on to the inputs of the ADC and are then converted in to currents.MOSFET M 1 is added to convert the voltages coming from tbe pixel in to currents sothat tbe colwnn voltages are not changed with the sensing circuit. The difference in thereference and intensi ty voltages has to be taken to minimize pixel-Io-pixel variations [2] .


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Linn ri ly of NMOS Souree FollowfnlThe performance of the NMOS source fo llower (SF) is criliCliI for a linear

converSIOn. Non-linearites due to variations in threshold voltage and other processparameters could lead to blurring of images and non-uniform color pictures. Figure 3.4shows the Sl.:hematic for ac analysis of the SF with body effect. The output voltage(figures 3.5, 3.6) and the gain g u r e s 3.7,3.8) of the SF shown in the figures have beensimulated for different widths or20 (vout), 50 (voutll), and lOO(vout22). It can be seenthat illCreasing the width of the source follower increases the gain thus giving a goodconversion but the bandwidth of the SF decreases affecting the dynamic mnge. Also bodycffect limits linearity in NMOS switches. The linearity is limited by body effect in theNMOS switches sin.ce in an n-well process body-effect cannot be eliminated, as theNMOS device body is Ihe substrate. figures show the ac analysis of Ihe Sf without bodyeffect for different widths W " 20 (voul), SO(voutll), lOO(vout22). Without body effect itcan be seen that we get a higher gain and bettcr conversion and again the bandwidth isaffected . Increasing the width increases the parasitic capaciuUlcc (Coxn) of the MOSFET.which increases the time constant and hClICe decreases the bandwidth. [4 ] shows theanalysis of the effC(:1 of source follower on the pixel's output.

VDO

ImVV., 2_5V R 11 = VoutlR

Figure 3.4. AC analysis of the S F


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21

"' vou t l l900 .0,-_-;_- -_ . . . . . - ---- _. _-_ .... . . - - - _..... .Output

Voltage o fSF

1600, ~ - - ; -

700 . 0 - -_ . . . . . .

.... __ .... ... . . ... ----- ....-

_....... -

...

600 0 : -- : , - -_ ._ .. . . . . --- . .. ~ . - - . .. -. - ... .......... . -_ .100 10 ' 3 10 '4 10 -5 lO A6 10 ' ?f r eque noy Hz.1requency

Figure 3.5. Output Voltage of tbe NMOS SF with body effecl for W - 20 , SO, 100

Un. t s - - GUN5 0 -- GAI NI Oa-- GUN20 ,, - - --co- ' "F '' 3 :=! 0 ,"'F i c ' " N ~ ' lh";'fiII --f. :

~ ~ ~ ~ r - 2 "1---" :.+ -i,HI . --H.I '.- 1\ '. HI ' i-, " - , . ' I - - - - . ~ : ; -----' -H, :. '

-. _,""-"--- '--

, , .f requency Hz.1 requency

Figure 3.6. Gain crlhe Nl\10S SF with body effect for W " 20, SO, 100


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OutputVoltage orSF

22

- " " " " 11 - voul221000 G,- . . . ; . . . ; . . . . . . . . . . . . . . . . . . . . . . _-; . . . -- -_ . . .

'"'""""

. , . .0:-_ __ :;;_ '7 -," ........ -_ .. __.: ......0;

_ ...... _ . . .. . . . . . . . . . . --_ ... , . ,\

._ ...... -\o .._... : ._...! . __ ...;... __ ".!. . __ .. _ ; . ' ~ _ ]:::;:1.::;:j100 IDA] 10 4 10S 1 0 ' 1 0 ' 10"8 1 0 ' 10"10

I requency Ill:---01 requencyFigu re 3.7. Output Voltage of th e NMOS SF WilhOll1 body effect ror W - 20, SO, 100Onl t . . - - GUNSO -GU IUOG- GA11I20

Gainor -" ,SFdBI -L10"9

! : r" ' luency U".1 requency.' ll:urt 3.8. Gain of tbe NMOS SF wilhout body errtt"1 for W - 10, SO, 100


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2lCurnot Mirror

A simple-PMOS cllfrent mmor 121 is sbo\\-n in figure 3.9. M I i5 a PMOS diodeCOflnI:(:leo;I MOSFET wilh its M l ~ and gale tied Iogdbef and M2 minon!he aarmtt inMI If both MI and M2 ha,'e ihc same widths and lengths then ihcir gate sotJt'()e voltagesand dnin to source voltageS IR equal and !he CUJTalts flowing in bod! !he MOSFETS areMIeaIly the 5iLIDC. 11Ie cum:nts ~ i U be in the ratio orIbe ",idths as given by Equation 3.1,Doubling the v.idth of hU ",ill resull in doubling the currau lsig 12).

fi_W,f . . Wl

VDO

(3.1)

VDO

F l : u ~ 3.9. rMOS Cu rrent Mirror

figUl1l 1.10 shows the rd!idiiCe and signal ( :urrmlS in !he curmt [ milr'or of flgUfe 3.9with """;ab""" in von for. ~ r ~ o f and MI and M2 cIev>ce 5i>:es of

SOWU 10 dnUn \vhagcs of M I and M2 are !be same. As Ird is a eonstanl currenl 50UJU(it \/oill dnlw II constant cum:nl inespective of the sowu "oltagcs) will uy 10 bold thegales oCthc MOSFET"s al a conSWlI potentIal keeping the CIIlTCnts in both the branchesconstant ideally.


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.,

'" 0

__ --," 0Current

- Isig.... .........,,

, ~ , -,-_ .. __ ..... _,_ .... _.... -,,

24

, - --_ .......,,,,, -- ' - " ' - " - " ' - ~ - ? - ~ : : : - "

'" 0 I - - - - - c + ~ - c : : : : ~ - - - - - c ' ' - - -----'' 0 (/, .. + , i -- f -I '0 00 0 , 0 2 .0 '" ..,sweep ,-I Voltage VDD

Figure 3. 10. Variation (If Reference and Signal currents in the current mirror


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Switched Capacitor Ci rmitA switched capacitor resistor [2] sho\>''11 in figure 3. 11 a can be used for realizing

large resistors greater than 1Mega ohms. NMOS or PMOS devices can be used for theswitches. Phil and phi2 are two non-ovedapping docks that are not high at the same timefor NMOS devices and should not be low at the same lime for the PMOS switches.Figure 3.11 b shows a switched capacitor resistor implememed with NMOS switches.Figure 3.llc shows the non-overlapping clocks (not high at the S;lfne time) required forthe NMOS switches and their periods should be long enough to charge or discharge thecapacitor fully. Since phi I and phi2 are not high at the same timc only one of the NMOSswitches will be 'on' at a time. If vI and v2 are not equal and ifvl>v2 then when phi 1 ishigh the capacitor is charged to voltage vI after which phil goes low Ml turns of f andwhen phi2 is high (M2 turns on) the capacitor is discharged to voltage v2 this way acharge equal to qJ-q2 is transferred bet","Cen vJ and v2 each dock interval [2]. Theaverage currem transferred a\ any given time is

Equating (3.2) and (3.3) we get

We get

C.ll;{VI-V,) (VI-V,)T 1k

IR" " ' - f C ~

(3.4)

(3.5)


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26

->

figure 3.1 L M) Switched C apacitQr ResiJIGr bl SCR with NM OS i l " h ~ c) )'1,',)0o" eriapping docks

Hence a large resistor can be simulated with a switched-capacitor circuit (2J; thevalue of the resistance can be adjusted by adjusting the capacitance and the clockfrequency. 1Rc advantage of using switched capacitor circuits is less layout area when alarge resistor (an implanted or diffused resistor takes up large layoll\ area) has \0 berealized. And ",,;th varilll.ioru; in process charactrnstics and temperature the resistancewill vary: the resistance value can be adjusted by varying clock frequeocy wilh a

switched capacitor circuit. But the disadvantage of using SCR's is more powerconsumption and the need for non-overlapping clocks, which makes if more complicated.Charge can be added or removed using switched capaci tor circuits.

Figure 3.13 shows the simulation of the SCR of figure 3.12. The two oon-overlapping clocks and the voltage across the capacilOr have been sho",'Il. It can be seenthat when phil is high Ihe capacitor charges 10 4V and whcn phi2 is high thc capacitordischarges to 2V. Body effeet in NMOS switches is the reason why the voltage is notcharging al l the way 10 4V


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,., ,.,- '- - '-

'" 2VIQ1 10'1~ ' 0 0 f

. .....r--- , ' 0 Irlr-rrVolr.age ,.J " "I "i':,~ r o ~ capacitor1

- _ .

o ' " . ' 1 I ....'.1.." 1 ".re-;

'O J" 11 j" iI,1,I", ,],11,;" ":"" J J L.:\" L ',,---, , ' , - .GO 200 400 ua 100 1

'"

,_ oS- tl,ure 3.1J. SCR Optntiou

27


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"Non-Onr lapping Clock G c ~ r

A non-


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29

, - ph i2 - ph i l6 .0 -- ----_ .,_ ... . -_ .... --_ .........., -_ . . . . . . .. -,-_ .. ., , - --., " _.. ,,

,

1-, " - _..... ." " 10 .0

r i4 ,-1,-+,,- _ .,,

,r-1f 'I ,. ... :,

,

. ..... .. _.. __ ... . - _..... _ ... - -_. _...... .20 0 30 0 0 50 0.,----EJ

Figure 3. 15. Simulation showing th e Non-Overlapping Clocks generated from Ihel:encrPlor

Feed Back C ircuitThe SCR circuit in figure 3.16 shows the feedback cirellil [2] for the DSM. When

phi2 is high the capaci tor is discharged [0 ground. When philgoes high phi2 goes lowshutting ofT the bottom NMOS, charging the capacitor to the bit line vollage, wh en thecontrolling switch M I tuniS on indicating that the feedback path be enabled. The switchM! is controlled by the comparator, which determines whether the feedback path has tobe enabled or no!.


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30

F i g u ~ 3.17 dlo .... the stmuial iOil the feedback circuit o f figure 3.16 sbowil\jthe eurrenllhrough Ihe bil line voluge. The bit line vo llagc is varied 2V 10 5V. Here....-e:

Bi: ra "oIIagc: VbiIS ...ch !hol eoaIIoIs --.. . /1he fe.e.cback0.rVbi I -.sV


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Current throughthe bit lineI

31

"' - -Vbi t l b.......ch'DO D ~ . : - - - ; - - - - ; . . :--_ . . . . . . . . .. . . , .. . . .'00 ai .. --. ii . .:. . . . , . .. , . ., . . . .. . , ,400 0: _.- _ . _ . _. -: ...... - _. ,- -- : --- --.--- ---:- _. - ' --_.. -;. . . _._ . . ----:: ": : : : .... .'".. .00 0:: . . . . ."',._-: . . . . . . __ .... ........... :. . . . _ . . . ._-:, jj --i- ' ,o oj - i -----1

. . .-2e1a 0; _ . _ .. - -. : _ . --_. -- . . . _ . . . . _. -. . . . . . . .. -.. --_ ....'as 0 '0 ' 0 '07 0 '08 0 '0 ' 0 '10 0l1_ ..s----[3

flcarc l.l&. S"owmCI S i a g ~ Cureal palK

F ; ~ 1.18 dlows I lingle t\If1'eI\I puke oC Figure 1.17. Adding MOSFET MI ( f i ~ 3.20) the N\tOS $OIIfI:e rollowa mU:cs the charge 00 the SCR's independena oCthe bitiu-oe v o l ~ ";ow!he chargt: on the capacilOr esc givm by QcaP"' Cse (Vcol-V\hn) glveII' mluc:ed v o l ~ g e IWlng and reduced = 1 (companng figure 3.18 " " ~ t h o u l the NMOSSOUfU; bllo,,"'er and figun; 3.21 with !be NMOS soum: rolklwa-) and good hneanty. Theamounl or charge 00 !be bit hne is more eonstalll independent of he bit line voltage 12].


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12

I """'"VOD I ...'

CK I ...,Fla-"' J.19. Feedback Clrtuil WiD 1 . I I ~ N"MOS _rtt foUo ..er

., - _\'b,t l hr""""'" ,,---------'--"-----------,------------"---'-------',----- --------,

""""" _ . . 11SO 0!he bll hne ..".SO,

-SO , , ~ : - - - -- --- :--,::-- ------ ::--:: '" ---- --:--::------ -- , -, - - - -a 00 a 20 0 40 a '0 0 '0 ."t t l l l e uS---'8bll 2V IVb"!'V IJo' j!ure l.lO. Currell! Ihrouga the bit Ible ,ole.ge sour",


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33

- -Vb. b r < U l C h 200 D. . . . . . . . - - -- . . -- - - ----- . -- . .. . . . . , . . . , .. , . . . . .150 oi ......... ......... __ . j .......... ... __ ...... _, ..........., . . . . .r - : - - - , - - , - , ' , . , ,Currmt t h r o u . . . . ~ : : : : : :" , - - - ' ' ' ' : : ' ' : : " i ' : : : ' ~ = - - - ' 00 Of" ~ - . - - m 1 - - - - 1 - - ""'---f-----""'--f-- ~ " ' ' ' ' ' ' l

1,., , , ,, '' . . . . ." 't'" ., ...... [ ..... t'"\+!.\.:= , : ', :,:0 0 ' , --.'

. . . .-50 , 0 ; . ._ ...: , --_. --- --- .:, . . . . . . . . . . : - : .. --- . . . . . . .60S a '10 a ' I S 0 '20 0 '2 5 0 610 0

1'1&..... .1.21 . ' .,.,mp lde SdtlillC

LooklnSAI Indl\'.dual pulses of figure 3.20 in figure ).21 we can see thai there 1Imcomplete 5dlhnJ i.e, the currenl In the bit hoc: docs DOl go 10 zero ...hen phiZ goes high.This is we to clock fecdlhmugh. l.o ..mng!he cloek freqJ>ellCy o(the CI!CUII WIll rcdllCC.the incomplete ICt lhng of the Ci rcUit as seen In the simulation of figu!e 3.22. li ere thetime period iJ lOris.


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34

"' V b ~ t l b r a n c h tliD 0,-- -_ . . . . . ... . . . . -- - ' . . - . . . . . . . -. . .......,, ,, _____ _ 300.0, . . . . . -- --f - f - ---f _ ----_ . . t -__-_... -:

CUltt1li throughthe bit line- - = : : " : : : ; : : = - ~ 00 . 0 ..- --_ .. _- "

100 O ~ - - -

,..... ....... _ ........__ . -. __ ...... ., ' ', , ,, ' ', ' ', ' ,

\ f""""': """ "" ,:1 , ," ~ - - ~ ~ ~ ~ - - - - ~ ~ - - - + - - - - ~ - 1 0 0 0 ~ _ . . . . . . .

60506100 6lS 0-_........ . - -_.. ...... .

&20 0oS

6 25 0

- Figure 3.21. Lo ...ering Clock Frequency to reduce Incu mplttc Settling

- _ .6313 0


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"

Figure 3.23. DSM Input CircuitFigure 3.23 shoWl! the DSM input circui l (2\ consisting of NMOS source

followers and the: feedback circuit. The MOSFIT s M I and M2 1m' II1lKk: vt'ry wide sothai it 11M ViS very dose \0 Vthn. If the signal from the oompanuor 1l0C!! high theresistor (SCR) in the reference signal feedback path is enabled. If the r e T ~ signal isgreater than the desired signal we want to me35ure, Ihm the CIIITCTI\ in the reference pathwill be greater than the current in the desired signal path (sioce Vgs of Ml is greater thanVgs of M2). The MOSFET M4 (charge oontrolling switch) in !be desired signal path isal ....ays enabled. The eapacioor on the: node Vsig l is charged ....ith the d i f f e ~ in theCWTCnl.S ITdlsig.

The PMOS current mIrror can ideally source the same cUlTCnl through each sideand ..mn Vn:f >Vsig MI can sink more cum:nt due to it's higheT gale \'oltage than M4


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36

resulting in chasEing the capac:ilOr on the node Vsigl 10 II higher voltage the Q signalfrom the comparator goes low IhWl Hlcreasing the charge on node Vren .Wbto swi1ch M4 closes., the amounl of charge dumped on 10 !he capacitor in the desn'ed

When swilCb M3 closes. the amount of charge dumped on 10 the eapatu.or in the:

ngun: 3.24 shows the simulation showmg voltages on the nodes Vren and Vsigl. whichIdeally 1rnCir: each other due \0 the f


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J7

Simpling RdcuDce and Inlern;!), SignalsThe reference signal Of the black signal is sampled firsl followed by desirtd signal

on \0 Iho:: input sampling capaciton thrQugh switches. I f !he signal from the pixel \'lUiesduring conversion lime: then the ADC will produce a wrong ootpuL To handle theseclumging inputs this sample hold capacitor is added. The hold stilling times. linearity.clock jiner, hold-mode feed through of the S/H will alTt


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38

Charge Injection and l o ~ k Feed ThroughCharge inje


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J9When the MOSFET is operating in triode and elk goes high, elk will feed

through the parasitic C3pa1;itances (gate-source ilIld gatc-drain capacitances), \\'hichhas no elTect on the output voltage, as the hold (apacitor will charge through theNMOS resistance. But a voltage change occurs on the output when e lk is low as itfeed!; through due \0 Ihe volll1gc divider between the twld capacitor and the parasiticcapacitan>:e sOO"11 in figure 3.26.

Ck -" - ln TCgdCb.,d

Figure 3.26. Showing clock feed throughCloek reed through [15J and charge injection can be cancelled au! by uSing

various methods. By using a transmission gate for the switch the charges releasedfrom complementary MOSFET's Icod 10 cancel OU1 each other \0 a certain extent. Adummy transistor wilh drain sourcc and bulk shone

hold an:hi tectures for increasing the speed of\he sample and hold circuits have I)(."enproposed but they suffer from clock feed through and I:harge injcction problems too.A high speed sample and hold technique using MiJler hold capal:itance to improve the


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precision and reduce charge inj ection problem in open loop SIH circuits has beenproposed [17].

Showing C harge Injection & C lock Feed Through from the TG'sFigure 3.28 shows the c lock feed through on the output of the TG in figure 3.27 with

PMOS & NMOS widths 30/2 & 10/2 respectively for a 2.4V input, the voltage change isaround 12 mV. PM OS clock reed through is thrice the NMOS clock feed through.

,2 U li

2 410.-:---,,-----,Output Voltage2 405

Vo-(Vout

Fi gure 3.27. TG

........ .... ......... ............ .......... _........ -., ' ', ' ', ', ', "-- --'-- --, ' f ' '.., . .... . ; . . . . ! ..... ! .! ....... !......! . . . .. . . .., ' Voltage Chonge",12mV,, ' '. ........... ........... . ........ .. .......... .. ........ ., , . , . . .. . . . . .. . .. . .: : . ., , I2 400' '::-- - - - :"'-;--- --"'-;-- . . . . . . . .. . . . . . . ...o 0 2 0 4 0 .. 0 BOlO 0

"'-----6Figure 3.28. Clock Feed through ofTG


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41

H a ~ l I ~ "'Ilial widtli devi


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42

Figure 3.30. Sa mple & Hold O ~ r a l

f igure 3.31 shows the simulation of fie circui t ShOWll iJl fi guro: 3.30 wi th reference (dark)signal of2.4V and l ~ ' T I s i signa l of 2.2V.

,

I oltage II-YS ' !!

2 5 . . . . . . . . . . . . . . . . . . . . . . .. - . . . . --.- . . - . . --,--.--- .. -- - . . . . . . . . . . . . ,,2 0 . . f - . . -: . - - - - 1 1 - - 1 - - ~ :

1 5 . . . .

1 0

.. .. -....., ,..........., ,, ,, ,, ,, ,, ,os ... . ..... -.. --

"'

. . . ........................................... . . . . .. . . . .. . . . ." , ... . '. . .. .. .... .......... ,. - .........-.... ... -- .....-..... . . . . .. . . . ., . ,. . . .. . ." ,- i - t __ ,,} -.:,. ,. , , , ,hae .5Figure 3.31 . Sho.. ing rererence .od sil:nal voltages a Rer u mpUng


61/102

4J

Tbermal Noi.'ltThennal noise in a resistor is due to the random motion of electrons with variations intemperature. The sample and hold circuit [9J seen in figure 3.27 can be modeled as an RCcircuit seen in fig 3.32. The hold capaci tor charging through the MOSFET's parasiticresistances gh'es rise \0 a thennal noise introducing fluctuations in the reference andsignal voltages measured. R is the resistance thai comes from the MOSFET's parasiticresistances here Rn 1/ Rp and C is the hold capaci tor.

R R

cFigure 3.32. Modding noillt' in a RC low p filler [91

The noise in the resistor can be modeled by the voltage source VR seen in fig ",here VR 2.. 4kTR is the thermal noise "SO of the resistor [9]The U'lII1Sfcr function can now be ",Titten as

V_(s)= 1 [9JluRe

The toUlI noise power a1the output can be written as

The IOtal RMS noise vollage measured a\ the output can be given by

f9f


62/102

where k = Boltzmann's constanl - L18E2J JIKT - Temperature in KelvinC - Capacitance in Farads

The noise voltage is independent of Ihe MOSFET's resistances and is only dependant onthe s i ~ of the capacitor because for bigger values of R the noise per unit bandwidthincreases but the overall bandwidth of the circuit decreases due to higher time constant.Increasing the size of the capacitor will decrease the thermal noise sampled on to thecapacitor but the speed of the circuit degrades. [9] Using a lpF capacitance the value ofthe thermal noise at room temperature ca:n be calculated as follows:

\ i ( I } . ) ~ " ~ 2 J ~ I J 3 @ o o i i V _ ~ IpF 64.J.uV

Selling the hold capacitor to IpF gives an RJ\1S nOise voltage of 64.3J.1V at roomtemperature. So when the TG turns on both the input signal (reference or intensity) andthe kT/C noise voltage (64.3J.1V) are sampled on to the hold capacitors.


63/102

45

Companllor DesignFigure 3.33 sl>ows the comparator [2} "11h the PMOS imbalance MOSFET's used

for this design.VDD

PMOS 30/2NMOS 2012M8

Figure 3.33. Compa ra to r Circu itWhen dock is high MJ and M8 are off, the MOSFET's M4 and M7 tum on

pulling the nodes QUlp and Culm low, turning M2 and M9 '00 ' pulling the nodes 01-04'high'. In Ihis way all the nodes are actively driven ' high' or 'low'. This is important forerasing the comparator's memory, since a floating node might swing to a v()ltage value ofthe previous sense operation. Since M3 and M8 are offthcre is no direct path from von!O ground so 1he current pulled from von is also very less; it does not pull current exceptwhen the clock is switching stales. When clock is Iowan imbalance is created and thenodes vp and I'm arc compllfed. I f vp>vm the currenl in Ml is Jess than the current inM10 (since Vsg of Ml is less than Vsg ofMIQ). The node 04 will be pulled high andwIlen dock goes [ow Cutp will be pulled high tlll11ing M5 on lind pulling Outrn low(tuming M6 off). The companuor pulls an average current of around 4 S The


64/102

46

maxImum Input voltage that can be 5f:IlSed IS VO[).Vlhp and the comparator funcllonsfor negative input voltages also as the gate voltage still above the threshold voltage orthePMOS device. For vay tush Input voltage!l the input PMOS devices will be ofT and theImbalance cannot be c=\led. The nurumum vno fCqVlred isVsd.MI V J g . M 2 + V g s . M S - - O . 2 j + ( l . 6 6 t i ) . 9 2 = 1.83V for the 0.5 micron proceu.In the $1IllUJatlOll of Figt= 3.34 vp input is held III 2JV and vm input is held at 2.1 V.Since: \'JI>'-1tI the node Quip will be pullal high ",iIcu clock is low (Ouun will be pulledlow). Wbm clock is lugh both the OUtpulS are puUed kilO' III seen in the $imllauon.

Iv"-I)

" ,'"

- ~ ' P c:la::lr...1 - _ _ -_. "_ . -_ . -- --_. , - --- - - . - -_ . -y ---_._ ". - , _, , . . , . . . .

- . . .. . .. .. . .. . . .--.-.-- ..... ~ . - . - - .. --.-:.------ .. --.-:-.--- ....... .......-.-..- . . - .. .. . ...."Ir---j ,., - - ; .... -r .- - - - ,

. ." [ i- > - i- i- i, , , .- - . , .. . . .. . . .. . . ,-s 0 . . . . . . . . . . . . . . . . . . . -- . . ~ - - - - . . --.-- . ;- .-----.- . . . . . . -.- .. :" " . " . '" oS ." so,J.'gllre 3.34. S lIo.. inC tbe opcratioa of the comp"rator 10 ngUrf J.JJ

Figure J.JS show5 the inputs, elock s ip l s and outputs ofltic comparator with vpinpUI swept from 2.1V 10 2.3V and vm input is held at 2.2 V. When clock goes low boththe OUtPijlS are pulled 'high' mitiall y when the sensing operation suuu hence \he glitches


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"ate soet1 In the sImulation. ThiS can be a problem for sensiRII .incc the comparatOr couldtake the wrong declJion and enable or disable the feedback path ....hen il should I'IOt andtherecan be. chacgc Il"IlnSfer when there should not be any.

, o u h ~ ' - 1 l'00" ,V".... ~ o o . .. ...... ; .+ . . ....... .

1 ,"-"" ' " 10 0 0 15 0 0 200 0oS 25 0 0 laO D--8F1clln J.J5. Slto . ine lite 0pulicioa or.-c nampanlor iD n, ure ).JJFigure ) . )6 1hov.'S the COIl1pMalOr WIth SR F1Jp-00p .ddcd 011 its oulpU! when

do d aoes high both OUlpul5 go low and the latch docs not change stales which make theOU'P1" of the comparator change on the rising edge oflhe clock when the inputs change;Oulp flows 10 tho QI output and the: Dutro flows 10 the Q output. Adding the nip-napmakes II easier to COWl! the output pulses of the DSM .


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clk l

VDO

PMOS 3012NMOS 2012

M8

Figure 3.36. Comparator Cireuil " 'lib SR Ftip-nop

48

Figure 3.37 shows the simulation of figure 3.36. The input and output and the clocksignals !lave been shown. The vp input is s ....ept from 2.3 V and 2.7 V and vm is held at2.5 V. When vp>vm. QuIp goes high and the Qi output goes high (Q goes low). Outputsof the comparator Q and Qi nip when the input data changes only on the edge ofclock asseen in figure 3.37.


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"- .-..,r---t---i-----'-

111__" __+_ . _ ..-+- ._ . - -1--- ' - - ..-- ! -___--ii Q

I I I ---7- --- -- - t - - - - - - ; - - ~ " ' I - - ~ - - ~ -

I Voltage 11111---- --. -- - - -c j --- .------- - --'- Q

1 "",,,"

- --- -- - - - , ~ " - - ~ - - , ' ~ - -"',.

--

.

- -- - --,

- - 'nft- "'F4=l""' .. "".

-'--

I., .,

---._-.

f l I l - ~I I I iT ,p"".. .. "' '"

Figure J.J 7. Showill g the ollCra li (ln of cireuil in figure 3.36


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Se ositivity of Compara tor

The sensitivity of the comparalor is around 8mV. Figure 3.38 shows the transientresponse oflhe comparator in figure 3.36 with vp input swept from 2.52V to 2.536V andvm input at 2.528V. Figure 3.]8 shows the inputs. clock and the output signal of thecomparator. The minimum voltage t h ~ comparator can reso lve is SmV.

, -Oi+12 - ' 1+6 5- c:locl


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"Shnu lath'I& th e C \\K.K t' ted Through Noise & KIckback NoIse of the Comp"ratQr

Clock reed through noise is present whm clock feeds through the mp\ll orllle comparatorcin:uil and is not I problem hat: since the inpulS are isolated from the cJoc:k SIgnal by twoMOSFET'.. Ilowever ltickback noise (wllich is the noise feedmg in 10 \he mpuls whenthe eompantOr 15 switching staleS) is prcsmI and can bccomo: I problem for the 5eI1SlIlgCUCUIL

SunuLull lllhc lmparalOr ~ i l h DDIHdeaI !II()tIl'CeS can gin us !he amotIIIl of kick t.ck

III'OUnd ISOmV as scm III figwesJ.J9. 3.40.

,S I I . , -... "- -.....--_., ........ ",IIv'::c Is + ..000 . . . . . . . -:ron .m ..... _ -- .. -.. -

S DO: - ,_I n i ...

,t to:".

u ~ '

1.......!.-., .... _-_ ......... _ ...

10f 0 102 0 tu . 10 6 a

Figure J.J!I. Sbo . inl: the Clock feed througb Nooe of tbe comp .... to r


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inp"Voltage

)

... . .. ........................... .. . .. .r . ~ - - - - - + C - > - - - ~ I ,0:, ............. r ----- -- ---- - -_ . -- -------- --

............._................... ...... .... .100 0; -_ . . .. . . . .. .. .._ ISO Q! ----- , ---- -- -- f -- --. ._2 00 o::---.!- - - -.. -.........-........980 100 0 10201 0 < 0 106 0.,----aFigure 3.40. Showiog the Clock feed through Noise of the comparator

52

tlaving IpF capacitors on the inpul of the circuit reduces the kick hack ooise of thecomparator 10 6mV as shown in the simulation in Figures 3.41, 42. The huge: capacitorsavcr.age OU1 noise so Lhe kick back noise will not interfere with the sensing. The averagecurrent drawn from VOD fOT both me comparator and the nip-flop is around 771tA_A comparator with both NMOS and PMOS input transistors could be designed so that ithas a beuer sensitivity and wider inpul signal range beyond power supply rails.


71/102

", --s o 0 , : ~ .. ~ ... . . . . . . . . .

Iv ~ 1 1S 0020: +f ; .... . .. . .S 0000: .. .. : . .. i . . . ~ . . . . .. .. ...

........... -- . . . . . . . . . . .. .

j I - - - ~ . ... . .. . , ., 99(,0: . . . . . . . . . . . . . . .:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UO 100010201040106 0

- - ~ . s = -flt:.rr 3.41. Sbowillg tbr ClKk reed t b n H I l ~ Noise or tlrlr cornp ..... lor witbcapadlOI'!

--"1 a, .. ... , . .,................

I v ~ ~ e 10 o ~ - - - - - + - - t c - - - = = : : : j : : = = o = = = .. -..= - - - - - ~ 1 _2 a: .. .................... ............................ . .. .. . .

1 . . . . -....-, . : ......

.. .1 .............. , . ...................100 lIZ 0 104 0 106

folgurr 3.42. Sbo"'iDI: tIIr ClKk reed tbrough Noise or Ibr COlUparalor widr.


72/102-

Showing tbe Schematic U ~ e d ror (he Design

The schematic for the DSM AOC [21 is shown in ligu: 3.43.

VDD

i' - VIr! T I 4012 ~ - '

Vsig

Q

.on500110 5001 10

VOD l hil L...,+--CVD=D;------------.JY"1 "'" ""r fTFigure 3.4]. ~ h f m a t i c or the DSM

lb c current in the Tefcn:m:c signal path is

I. . " V",-v.. (3.6)...

The currenl in the desired signal path is

I _ V . -v ..- R.,. (3.7)

54


73/102

Due to the feedback path the currents in both the branches are equal, bence we can write

V'1 -v . '" V..,-V.. (3.9)"'" ...

where NMFCr-N - tOLaI number of clock pulses

M '" number of times Qi output goes high

Substituting for Rr., and R.,. in Equation ....e gel

-==V"3-e=: v..",., "' IICsc. N-M lese

N

N-MV.., ..... '" -_ V'1"'"N

().IO)

(3.11)

(3.12)

Using the Equation J.12 Ihe desired voltage signal from the pixel Clill be calculated.


74/102

DSM Sensing C ircuit

, A lll:l'1 lO!2 Yc.,. ttpF1t l c ~ -;1; ''''

Figure 3.44. I)SM Sen! ing CinuitThe voltages from the pixel i.e. the column voltages are sampled on to the holdcapacitors. NMOS 50urce followers are used to convert the voltages in 10 currents. 11lewidth of the NMOS devices is made large so that the gale to source voltage is dose to thethreshold voltage and will be robust with variations in VDD. The current in the refereru.:epath is mirrored using the PMOS current mirror. 11le switched capacitor circuit in thefeedback path behaves like a resistor. Since Vrd >Vsig the current that Ml C3JI sink inthe reference path is greater than the current in the desired signa.] path. The PMOS currentmirror mirrors the reference current to the other side; the difference in currents "illchargc the capacitor on node Vsigl. Since there is a lower gate voltage on M2, thecapacitor on nodc Vren will be at a lower voltage than the other path. Q will tum low


75/102

17disabhnl the fttdb&ck path in 110> n : r c ~ c signal path and decreasing the current in thispath resulting in increasing the node voltagc Vrcfl, untillhe CUl'ttf\15 in both the paths areequal. IlI(:rcuing the ~ i 5 W l C e in the feedback path will result in Iowmng the CuneR!nowing and "'ill UIke. longer sense time. Using small resiSlOfS (increase capacilanl:c ofSCR's) willa ive. faster $Itf\Se. The sense accurw::y depends on how ICCumldy charJctan be guided Into the c:apacilOB, if 1M dock high time i$ very low the NMOSSWItch of the SCR will be ofT the dwge from !be bi l Iioe caDDOI. be removN prttisdybee , . . . less charge goes 10 !be switched eapacitor.s inaeasing !he resi.slanoe Mdd ........8$.111 !he currenl$ flo ... This limits Ihc: axuracy of the sense beaoce gi\'lng nonhl1l3liues.TIle OUlJIUI Q! can be g i \ ' a l 10 an up COUlIta-, which counts !be Dumber of limes !be_lIeh in the feedb.dl: path.. bas been enabled. By . , ~ the number of times tho:capacitor in the feedback pub has disdwged by c:omparing i l to the refnaJCe ,'OIuge.we can gc1 an idea of the lbimi signal 00 thc coh.mll \'Oltage in the ptXt'I "'"t an: tryingto measure. Tbe: PO"''" by one of the DSM Sl"nX-amps 011 the chip is onlyaround 650)1W


76/102.

58

Figure 3.45 shows the signals VreO, Vsig l and the output Q from the DSM. It can bes teI\ from the simulation thai when Vref > Vsig. !ref > isig. the Q output goes lowmore decreasing the CUrTe1l1 in the reference signal path unti! the CUJTCllts ;m : equal.When Vrefl goes above Vsigl, Q goes bad: high and tries \0 discharge the node Vrcn., vref l

&.0 ... __ .. ....... -- . . . . . ..... ,--... , . . . . . . . . . . . . . . . . - - - - . " ' ,, . , .. , . . , . . . ' ,., . ', . ' ' " .. .r-,----' . . ..0 n.n . " __ n uOutput

Voltage fDSML ~ _ - " ' O . ~ ...... ' " .. ...... _, .......-.- .. -.... - . - ~

1-2 0 . . - . . . --. --. -- . . . . -. .....-

0 0 0 2 0 4 " , -...._--- .,. _--_ .. -_ ........". 10 12 1 4_c""=-_+.a, ,

Fig u re 3.45. Show ing the signals Vrefl , V$ igl and tb e ou tput Q froni tbe sensingci rcuil

Avernging roxluccs the amount of thermal noise sampled on \0 the capacitors by Iftimes as iodicated by Equation 1.11 [21

(l .U)

From the equation it can be seeo that increasing thc oumber of clock cycles decreases theamouOl ofthcrmalooise sampled 0010 the capaci lor and hence we get a better seose and


77/102

"an improvement In the signal to noise ralio by averaging for more n u m ~ r of clockcycles.


78/102

60

CHAPTER 4: SIMULATION RESULTS, LA YOUT OF THE ADe

Showing the Output of th e DSM s i n g circuit

Figures 4.1, 4.2, 4.3, 4,4 shows the simulation results for the DS M circuit asswning thatthe OOWller is enabled from O.5!J.S (to allow for start up and 81H operation) sense time is

For Vrof=3.2V, N- IOO, V",.-"i' =V.., - V..=3.2--O.67=2.S3V (Hand Calculations),

a) For Vsig"'J.! V, V.......=V .. - V .. =J.I-O.67=2.43V

From simulations, the output goes high J limes hence (Figure 4.1) and the value of

v...... .. N ~ M . v..,_ _ . 2.53 =2.45V (Calculated from simulations)

b) For Vsig- 2.15V, v..._ =2.1 S-O.67=L48V (Hand Calculations),From simulations Output goes high 44 limes hence M""44, (Figure 4.2) and the value of

1()()-44V....... z 2.S3 1.42V(CaJculated from simulations)100


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" ....... _, ............. . .. : r .... . . -...... .. ..: : - - - , ' Output

Vo ltageoroSM o .... " ~ ' - " " ' , - ' . .. . .. ... .-2 0 .. . . . . -...- . .

0 0 0 2 0 '

-0'-.. ~ . - - . - ....-.... -.,..-.. -- .. -...-.--, ..-.... . . . . .,,..........-. . ... ...... ._...-...... . ....... ... .

.-_.: .......

.... _--_ ..

...- ....

-_....-........ . ' ................._-- .......... .. 1012 1 4 1 '",-05_ 8

Figure 4.1. ShOIl-lnl,! Ibr ~ U ( P I I I of tbr DSM sensing circuit of figure 3.44

,' - : : - - - ' , ." ....Output .. I t

VoiligeorOOM ,

.

-0 '

.. .. .. ,.oS 1 2 l 'F 1 g u ~ 4.2. Output of tbe DSM leasiag circuit of l igu t 3.44

, ,

61


80/102

c) For V_r-1.6V. Y........ .6-0.67.O.9J1' (Hand Cakubltonl).

, -01 , ............... +..-.......-...... , ......., ......., ......,

au.... .VoltageorOOM

- ... ... . ... _--j . ,,,, ..c':: . :": ....:'

0 0 0 2 0 4 0' al II 1 2 1 4 I '- - -8FlgLlrr 4J. OUlPlit or Ib" DSM U D$ID& elK . 11 or "gun 3.44

61


81/102

d) For Vsig-O.8V, V .. . .,=O.8-O.67=O.13V (Hand Cal cu lations),

Ou tput goes high 96 times hence M--96. (Figure 4.4) and !he value of

OutputVoltageofDSM

,(Calculated from simulations)

- "'" .......-, -_ ...... .. ., ---.-....... -, -_._ .. , ......., .. ., ,, ', , - _..........., ,, '

..... ,0 . . . ......... . ..... . ... ,,

- .... ... -L .---" "1

, '_.,....... . ,........... - - _. ... . .... ,,,

"", '-2 0 --- - . . . . . . . . . . . -

0 0 0 1 0 4 "',_. . . . . . . . . . . . .o 8 1.0

,,

_ .............

" : Figure 4.4. Outpul of th e OSM sensing tireuil of figure 3.44

Sen sitivity 10 VOD ~ n d Grou nd Noise

,

, ,

Th e OSM ADC has been simulated with VOO noiseo f lOOmV and ground noise ofsOmV. Simulation results (Figure 4.5) show the count generated by the ADC for the

63

signal voltages shown above in figures 4.1 (a). 4.2 (b), 4.3 (cl. 4.4 (d) . It can be seen thatthe count does na t change (for Vref=3.2V. Vsig""3.1 V. Count=3. Vsig"'2. ISV, Count=44,Vsig"'1.6V. Count=67, Vsig=O.8V, Count=(6) with variations in von and ground. Thecircuit is robust with VOO and ground noise due to its symmetric nature.


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" "'--"-'---"--y'-' ..-at-' ~ " - .... -'" _... -_., ..._... "" _.....-, _..-----. . . . - .. . . . , . , - .. . . .. . , ., . . '- .. .._. ..

~ - - . , " .- ........... -.-. -........ " ... _--_ .... , - . . .. .. ' ... . .. - . - . ~ . - . .."",,"tVollagCorOOM

1"

. .. ............... . .. .. . . ..-........-................ -- ' ' ' - ' - - - ' ' ' - ~ .. . ' ... .... ..o o __ ~ - + ~ __ ~ ~ ~ __ ~ L -2 0 -_ . . . __ . . . . . . . . . !..

DO 1J2 0 4

"...............-......... -........--.-.-....." , 0 t ,, t t '" uS r : : : l- -

r-tC.n".s. OUlp.' o r t h ~ D5M , VOD u d croud ..obe for V ~ , -Qt 0 , . . - ...... - . . . . . . . . . . . . . . . . . . . - . . . . . .- , . . . . ---, . . _ . . . ., . . . ._ .

OutputVoltaglCofDSM

1,00

"lgun 4.6. Oulpul or ille DSM ",-1111 \'DO .. grouod o o i ~ for Vsir'2.ISV


83/102.

,,r-::---, ' ,[ ....au....Voltageo rOSM 2 .. ..

-Q '

_ , ~ l : .....: ' : ....:": .+.:': ..."': ...:,: ...:.,: ...:.':.0 0 0 2 0 4 0 ' DB 1 0 2 1 4 I '_""____figure" .7. O.lpl l l of I ~ " OS .\ l _ilb VDO u d ground aoiw for Vsig-oUiV

,"

0::-- . , ' 0OulpalVoltageofDSM , 0"

-Q'...... _', ........ ._.... ...... ........ , .... . "" ......., ....... . . . . . . . . . . . .. . .

. .... _ ........ ............. . .. . .. ... . ...... -.- .... -_ .. , - _.. ...... . . .... .. .. ... _..._..

. .. .. .- -..... . ........................ -- ..... .

. .-2 0 . . . . . . -- . -- . . . . :. . . . . - . . . . . . -- . . -: . . -.. . . . . -.--: .-- . . . . !0 0 0 2 0 4 '" 0 8 1 0 1 2 I t 1 6

--""""--'6f i t" re 4.8.. Oulpu' of Ibe DSM with VDO .od groulld !loiM for V ~ i g = O . 8 V

6S


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Resolution of tbe DSMThe resolution of the DSM can be calculated by using the following equation:

v '" V"".oItt .. 1.73V = 17.3mV... N 100As the input ~ o l t a g e s drop from 2.4 V to 2.3 V the count difference is 7 (for a lOOmVdifference in the reference and desired signals) from 2.3 V to 2.2 V the code is 6, for 2.2V to 2.1 V the code is 7, for 2.1 V to 2 V the count is 6. So the resolution can beestimated as

V.. = lOOmV 16.6mV6So calculating the shifted re ference ~ o l t a g e ~ a l u e with this resolution gives

v,., ...... N V,... =1.666VVtf >'oi'I =V""- V ..v....V""-V,,,,_ =2.4-1.666=O.7J4V instead of O.67V

Calculating the shifted reference and intensity voltages with V . = O.7J4V givesa) 2 . 3 V , V"" ..... _ 2.3_0.734_1.566V (Cafculau:J), V ......... 1 . 6 6 6 V

9JV ~ _ =1.666 - ..1.S49V (Sensed value)100b) V",=2.2V. V.....- =2.2-o.7J4=1.466V (Calculated), V""_ =1.666V,

87V".,..... =1.666 - ..1.449V (Sensed value)100c) V.... =2. lV, V ~ _ =2. H l.7J4=1.366V (Calculated), V"" ......1.666V,

V .......=1.666 . 80 =1.332V (Sensed value)100d) = 2 V.,. ..... =2-0.734=I.266V (Calculated), V", .. . =1.666V,

v, .......=].666 74- = ] .232V (Sensed "altle)100


85/102

67

Table 4.1 5hows the valucs for the Calculated and Simulated si8J1llls for a referencevoltage of Vrcp] V. The shifted reference volUlge V ~ . . . " . V..,.-V .. _J.-{l.67:2J3VTable 4.\. Calcul ated :Ind Simula ted signals for to nstant reference "o llage aDddifferent signal vo ltages

fiiifoE;' ~ 1 l ' ~ ~ i g " , 1 ~ S h i j k d ShijWReftrMU OI!5;red Counl HAND CALCS signal signal

llANOsignalS IMSond D6iud Signal SIMS

signals

11

V..=O.61

11111 ,-[i---

:%-


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68

S lt ijled~ t w U I I signal Dai , " ,RI 'Jucnu Desired Count l lAND signal signal signal

and Daind Signlll (cont'd) CALCS(conl 'd) S IMS HA.ND SIMSsignals (con/'d) (conl 'd) CALCS (cont 'd)(COllt'tf) V..=O.67 (cont'd)

Table 4.1. ("D ntinued)

Showing tb e Co unt gcne ...lcd by th e sens ing circuil

The DSM ADC (figure 3.44) lias been simulated (figures) for different referenceand signal voltages. The count generated by the seru;ing circuit has been shown in figures4.9,4.12, and 4.13. Here the desired intensity voltages have been varied for differentreference voltages and count generated by the DSM has been plotted. The desired sigoo. lvoltages (outpul) calculated from the COUlll generated by the DSM and Hand Cales hasbeen planed for different input voltages (figures 4-10, 4. 11 4.7,4 .14-.4 .20)

We can see from the figure 4.9 that as the voltage difference between thereference and the intensi ty signal increases the count also increases linearly.


87/102

69

Voltage va Count for Vr . f 3\('E'00 - - - - . -, - - --"-, __ 00.nI ' " N, M -u ~ t ; ; : . : : : : 0 0 0 ' ,

", "

'poll

Figure 4.9. Showing the Count g e D e r a t ~ by the sensing circuit or figure 3.44

Comparison or vo llagl'll hllnd cales and sims genenlled by tbe $cnsing circuitA graph showing a compar ison o f tile calculated and simulated va lues uflhe outputvallages ror both the threshold vollages (Vlhn:O.61V. 0.73V) arc shown in figure 4.10,4.11 . h can be seen that the voltages generated with the calculated threshold voltage ofO.73V ( figure 4. 11 ) are more close 10 the hand calculations.


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,.,,

OutputVobge Y$lnput Voltage: Vret-lV, VlhnsO.67V

"........."""

- """"..- .'. ' ---'. '- -. '. '' -... .u , . 1.1 1.1 2

InpuIV, , "_

....

uz., uu ,

70

Figure ".10. Comparison or \"o'tages band tala aad linu ' ~ D ~ n l l r d by I b ~ KlisioCcin:.it orf1cul"e 3.44

Output Voltage Yslnput Voltage Vr.t-3V, Vlhn=O .73V,.,,f "1a " ... ...

" , - - --I......- -...... I

a J'- . . . _ Q J c o- ~ . : . - = = ~ = ' = = f _ 1, .... - 1.21 1.11.82 2.2 2.4 2.D U ,.,

circuit or fi l"n 3.44


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"V o l t ~ I I ' vs Count for Vref 4.5, 4, 3.8, 3.6, 3.4, 3.2V

Figure 4.12. Showing the COLint generated by the DSM of figure 3.44 for differentreference voltages

Voltag" vs Count lor Vr"f . 3, 2.8, 2.6, VI , 2, 1.6, W

,,"nput VoltagO O l ~

,Figure 4.13. Showing the Count geocrated by the DSM of figure 3.44 for differentrefHeoce voltages


90/102

72

Figures 4.14-4.20 shows a comparison of the calculated and simulated values of heoutput desired signal voltages for different refCRllCC voltages.

Output Voltage v. Input Voltage Vref=4.5V. Vttln..o.73V

"- ' , -Figure 4.14. Compari.5011 ofvolllgcs bind el la Ind silllS geoeflted by the muiogcircuit of r"ure 3.44

Output Voltage . .. Input Voltage Vntrqv. Vttln-o.73V

,,.!l.a -,-

Fig ure 4.1 S. Compu'ison of voltages hind ulcs and sims geQerated by Ibe se nsingcircuit of figure 3.44

8/2/2019 A 1-Bit Analog-To-Digit

A 1-Bit Analog-To-Digital Converter Using Delta Sigma Modulation for Sensing in CMOS Imagers

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