A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC
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1 Masaya Miyahara, James Lin, Kei Yoshihara and Akira Matsuzawa Tokyo Institute of Technology, Japan A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC M atsuzaw a & O kada Lab M atsuzawa Lab. Tokyo Institute ofTechnology
description
A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC. Masaya Miyahara, James Lin, Kei Yoshihara and Akira Matsuzawa Tokyo Institute of Technology, Japan. Outline. Motivation Design Concept Calibration Technique Measurement Results Conclusions. Motivation. - PowerPoint PPT Presentation
Transcript of A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC
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Masaya Miyahara, James Lin, Kei Yoshihara and Akira Matsuzawa
Tokyo Institute of Technology, Japan
A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s5 bit Flash ADC
Matsuzawa& Okada Lab
Matsuzawa Lab.Tokyo Institute of Technology
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Outline
• Motivation
• Design Concept
• Calibration Technique
• Measurement Results
• Conclusions
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Motivation• An ultra-low power ADC is strongly required.
– Portable applications– Ubiquitous wireless sensor system– Green IT
• A low voltage operation is required for further technology scaling and low power operation.– Analog circuits design becomes more difficult.
• Increasing VT mismatch
• Degradation of gain and distortion of an amplifier– The FoM of an ADC should be reduced like digital circuits.
• Optimizing a speed, resolution and power.• Calibration technique for low voltage operation.
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Performance of flash ADCs
2
q
off2
)(121log
2
1
V
VENOB
ENOBNd
f
P
2
FoMc
FoM is deteriorated by the offset voltage of the comparator.Offset voltage should be low at low voltage operation.
-1.6
-1.4
-1.2
-0.8
-0.6
-0.4
-0.2
0.0
0 0.125 0.25 0.375 0.5 0.625 0.75
E
NO
B [
bit
] Estimation
Simulation
-1.0
Voff () [LSB]
Voff():Offset voltageVq : 1LSB voltage
5
FoM vs. VDD
0.2 0.4 0.6 0.8 10
1
2
3
4
0
100
200
300
VDD (V)
Ec (fJ)
N: 5bit
FoM (fJ)
mVVoff 6)( =
ENOB2
)(bitENOB
ENOBENOBN
N
Ef
Ef
22
2FoM c
c
cc
cfSV
IVVCE
TcDD
2DDcc
exp
Ec:Energy consumption for each comparator and followed logic circuits.
FoM can be significantly reduced by reducing power supply voltage VDD.
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FoM delay product
0.4 0.6 0.8 10
1
2
3
4
5
50
100
150
200
250
FD (fJ ns)
FoM(fJ)
V DD (V)
Del
ay (
nS
)
Delay (ns)
Fo
M(f
J),
FD
(fJ
ns)
TDD
DDd
VV
VkT
Delay time
The FD product suggests the balance between the number of interleaving and decrease of energy consumption.
VT = 0.4 V Excessive number ofInterleaving ADC
• Large area• Driving difficulty• Reduction of ENOB
DelayFoMFD
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Forward body biasingForward body biasing can decrease the delay time (1/2)and can be used easily at 0.5 V operation.
VDD
IN OUT
0
2
4
6
8
10
12
0.4 0.6 0.8 1 1.2 1.4Supply voltage (V)
Del
ay t
ime
(rel
ativ
e)
W/O FBB
W/ VFBB (0.5V)
BBW/O FBB
W/ FBB (0.5V) VTN = 100mV
VTP = 60mV
Increased leakage current in the proposed ADC is 0.32 mA by forward body biasing.
1/2
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Proposed Calibration Technique
CLK
Vinp Vinm
1stOutp 1stOutm
CLKp CLKm
LOWCALcode_B
CLKin CLKout
Proposed Calibration(Timing control base)
Timing controller
no CAL Cap CAL [5] Proposed
Voff() [mV] 10.1 5.79 1.49
Pd [W] 14.5 21.4 24.5
Delay [ps] 365 756 511
[5] V. Giannini, ISSCC2008
VDD=0.5V, fs=500MHz
CLKp
CLKm
1stOutp
1stOutm
Conventional Calibration (Capacitor DAC base[5])• MOS varactor sensitivity• Delay time and power
CLK1stOutp 1stOutm
Vinp Vinm
CALcode_B CALcode
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ADC Structure
Comparator Block(32 Comparators)
S/H
S/H
・ ・ ・
Reference ladder
Vin
Thermometer to Binary Encoder
5
Comparator ×4
Comparator ×4
Up Down Counter 6b ×4
Comparator ×4
Comparator ×4
S/H
S/H
Error Correction Cirtuit
Up Down Counter 6b ×4
Up Down Counter 6b ×4
Up Down Counter 6b ×4
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2b Interpolation
32 32
Clock Divider
5
Dout
5b Flip Flops
f f/4 f/8
90nm 1P9M CMOS process
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DNL and INL
DNL+/-2.2 LSB => +/- 0.5 LSB.
INL +/-1.5 LSB => +/- 0.3 LSB.
(Measurement results are updated because the measurement setup is improved.)
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
0 4 8 12 16 20 24 28 32
CODE
DN
L [
LS
B]
Before CAL
After CAL
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 4 8 12 16 20 24 28 32
CODE
INL
[L
SB
]
Before CAL
After CAL
11
15
20
25
30
35
40
45
50
0 200 400 600 800
Sampling Frequency [MSps]
SF
DR
, SN
DR
[d
B]
SFDR and SNDR vs. Fsample
SFDR, W/ CAL
SFDR, W/O CAL
SNDR, W/O CAL
SNDR, W/ CAL
5 d
B10
dB
Fin = 1 MHz
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SFDR and SNDR vs. Fin
15
20
25
30
35
40
45
0 100 200 300 400
Input Frequency [MHz]
SN
DR
, S
FD
R [
dB
]
SFDR
SNDR
Fsample = 360 MSps
FoMBest = 110 fJ/conv.
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Performance Summary
Reference # [7] [8] [9] [10] This workResolution (bit) 5 5 5 5 5fs (GS/s) 0.5 1.75 1.75 0.06 0.6SNDR (dB) 26 30 30 26 27Pd (mW) 5.9 2.2 7.6 1.3 1.2
Active area (mm2) 0.87 0.017 0.03 - 0.083Vdd (V) 1.2 1 1 0.6 0.5FoM(fJ) 750 50 150 1060 160CMOS Tech. (nm) 65 90 90 90 90Architecture SAR Fold+Flash Flash Flash Flash
[7] B. P. Ginsburg, J. Solid-State Circuits 2007.[8] B. Verbruggen, ISSCC 2008.[9] B. Verbruggen, VLSI Circuits 2008.[10] J. E. Proesel, CICC 2008.
FoMFmax = 160fJ @ 600MSpsFoMBest = 110 fJ @ 360MSps
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Conclusions• The strategy for low voltage operation is
proposed.– FoM delay product (FD) is considered for not only
low FoM but also high speed operation.
• Low voltage design techniques are proposed.– Forward body bias can be used easily at 0.5 V
operation. (Td => 1/2)– The timing control based offset calibration technique
is proposed. (DNL / INL 2 LSB => 0.5 LSB)
• Proposed ADC has good power efficiency and high speed operation.– 600MSps, ERBW = 200 MHz, ENOB = 4.6 bit,
FoMBest =110 fJ/ conv. at 0.5 V supply.
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