A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications

7/27/2019 A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications

1/13

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007 2021

A 0.2-mW 2-Mb/s Digital Transceiver Basedon Wideband Signaling for Human Body

CommunicationsSeong-Jun Song , Student Member, IEEE , Namjun Cho , Student Member, IEEE , and

Hoi-Jun Yoo , Senior Member, IEEE

Abstract This paper presents a low-power wideband signaling(WBS) digital transceiver for data transmission through a humanbody for body area network applications. Thelow-power and high-speed human body communication (HBC) utilizes a digital trans-ceiver chip based on WBS and adopts a direct-coupled interface(DCI) which uses an electrode of 50- impedance. The channel in-vestigation with the DCI identies an optimum channel bandwidthof 10 kHz to 100 MHz. The WBS digital transceiver exploits a di-

rect digital transmitter and an all-digital clock and data recovery(CDR) circuit. To further reduce power consumption, the proposedCDR circuit incorporates a low-voltage digitally-controlled oscil-lator and a quadratic sampling technique. The WBS digital trans-ceiver chip with a 0.25- m standard CMOS technology has 2-Mb/sdata rate at a bit error rate of 1.1 1 0 7 , dissipating only 0.2 mWfrom a 1-V supply generated by a 1.5-V battery.

Index Terms Body area network (BAN), clock and data re-covery (CDR), digital transceiver, digitally-controlled oscillator(DCO), human body communication (HBC), quadratic sampling,wideband signaling (WBS).

I. INTRODUCTION

R ECENT advances in semiconductor technologies andcomputing systems have enabled the proliferation of mobile and portable electronic devices in the ubiquitous mobilecomputing environment. A wearable computing technology isan example for the user to easily place such devices around thehuman body. The wearable electronic devices (e.g., wrist-typecomputers, earphones, video eyeglasses, and head-mounteddisplays) and sensors offer the potential for a wide range of applications from health management to personal entertainment[1], [2]. Since such devices are distributed on the human body,a body area network (BAN) can provide connectivity betweeneach wearable device within the communication range of thehuman body, corresponding to 12 m. Moreover, it shouldbe powered by a very small battery in order to minimize itsphysical size, and be connected through simple interfaces forconvenience of use. Since the wearer utilizes wearable elec-tronic devices and sensors continuously anytime and anywhere,the devices require a low-power data transceiver employing

Manuscript received November 6, 2006; revised April 16, 2007.The authors are with the Department of Electrical Engineering and Com-

puter Science, Korea Advanced Institute of Science and Technology, Daejeon305-701, Korea (e-mail: [email protected]; [email protected];[email protected]).

Digital Object Identier 10.1109/JSSC.2007.903080

energy-efcient communication schemes and also the high datarate operation needs for exchanging multimedia data such asaudio or video over BANs.

There are two approaches to implementing the BAN: one ex-ploiting the human body itself as a transmission medium andthe other using external mediums such as wire and air. Tradi-tional wireline technologies such as USB On-The-Go that pro-

vides a point-to-point link between portable devices canprovidehigh data rates but needs long copper wires which are generallycumbersome for human body applications [3]. The radio-fre-quency (RF) short-range personal area connection using Blue-tooth can provide more practical usability. However, it has po-tential problems such as low data rate, high power consump-tion, and vulnerability to interference at the 2.4-GHz frequencyband [4]. Even the Zero-G receiver [5] for achieving signif-icant power savings over the Bluetooth radios still consumestoo much power. On the other hand, the novel wireless com-munication method utilizing the body as a data communica-tion medium, the human body communication (HBC), can op-

erate with good signal-to-noise ratio (SNR) performance in thelow-frequency band. Thus, the HBC is an attractive wirelessconnection technology for achieving both the high data rate op-eration and the low power consumption.

Recently, several HBC schemes have been suggested forthe BAN and their data transferred through the skin of thehuman body. The near-eld electrostatic coupling schemeusing a narrowband low-frequency signal was rst introducedby Zimmerman [6] and expected to signicantly reduce powerconsumption. His coupling scheme is strongly dependent onthe conditions of the surrounding environment like the earthground for the return path and has limited data rate of 2.4 kb/sdue to the narrow bandwidth of 400 kHz. Another schemeemploying an electromagnetic wave of 10 MHz also suffersfrom the bandwidth limitation of conventional FM and FSK[7]. Recently, another group reported a transceiver adoptingelectroopic conversion method to achieve higher data rate of 10 Mb/s by using a special off-chip sensor [8]. However, itleads to high cost, high power consumption, and large physicalsize for human body applications. Moreover, it must have twoelectrodes, signal and ground, which make it inconvenientto use.

This paper presents a novel HBC scheme exploiting wide-band signaling (WBS) technique with a direct-coupled interface(DCI) over the optimized HBC channel. The HBC channel is

optimized for high-speed operation on the human body. The0018-9200/$25.00 2007 IEEE


2/13

2022 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

Fig. 1. Conceptual block diagram of the human body communication with adirect-coupled interface through a human body.

DCI is an interface method connecting the silicon chip withthe human body directly. It uses only a single electrode fordata transmission without any intentional ground electrode, incontrast to other methods which require an off-chip sensor todetect the feeble electric eld and the earth ground path. Inaddition, the 2-Mb/s WBS digital transceiver chip is imple-mented by a 0.25- m standard CMOS technology. The digitaltransceiver consumes 0.2 mW of power from a 1-V supply.Therefore, the proposed HBC scheme can achieve lower power

consumption with high data rate operation than other HBCschemes in [6] [8], which make it suitable for the applicationto energy-ef cient point-to-point data transmission around thehuman body using the BAN. The proposed HBC using the DCIon the human body is illustrated in Fig. 1. The HBC transceiverwith the DCI does not need an off-chip component or a sensorto detect electric eld. Thus, it can fully integrate all functionalblocks on a silicon chip excluding a signal electrode, therebyachieving low cost and small physical size. Also, the WBS withthe optimized HBC channel can provide energy-ef cient datatransmission to extend the lifetime of the battery.

The paper is organized as follows. The communicationchannel characteristics of the human body are investigated inSection II. Section III describes the WBS digital transceiverwith the detail explanation of its main building blocks suchas the direct digital transmitter and the all-digital quadraticsampling clock and data recovery (CDR) circuit, including theexternal receiver analog front-end (AFE) block. Chip fabri-cation and measurement results are explained in Section IV.Finally, the conclusion is given in Section V.

II. C HANNEL CHARACTERISTICS

The transmission characteristics of the HBC channel havebeen investigated by using RF signals from 1 MHz to 40 MHz[7] and from 1 MHz to 3 GHz [9]. However, the frequency

characteristics presented in [7] were obtained by using a pairof signal and ground electrodes and only the frequency domain

response was reported in [9]. In this paper, for the potential op-timization of the WBS transceiver with the DCI, the character-istics of the HBC channel are investigated in the time and fre-quency domains by using only a single signal electrode withoutany intentional ground electrode or path. Fig. 2 illustrates themeasurement setup for the time and frequency domains. The

distance between a transmitter and a receiver is xed at 15 cm.The I/O impedances for the transmitter and the receiver are50 . As shown in Fig. 2(a), a battery-powered crystal-basedtransmitter is connected to the forearm with a single Ag/AgClelectrode. An electrode as the receiver is connected to a digitaloscilloscope and its ground is oated to parasitically couple itwith the signal ground of the transmitter through air in consid-eration of its usage in the real situation. In this setup, the trans-mitter transfers the electrostatic pulse through the forearm to theoscilloscope with parasitic coupling of the earth ground by theelectric eld. Fig. 3(a) shows the measured output waveformfor the time-domain characteristics. For a square wave of 3 Vat 2 MHz, the channel outputs are measured to be the positiveand negative pulse signals with no DC offset. Each pulse signalexhibits a narrow small pulse signal with a width of about 8 nscorresponding to a bandwidth of 125 MHz and the amplitudeof 90 mV. In order to obtain the characteristics of the humanbody over the frequency sweep without any purposeful groundelectrode, a signal generator is exploited as a transmitter andits ground is connected to the common ground of the oscillo-scope as shown in Fig. 2(b). The signal generator generates thesinusoidal waves with 1-V peak-to-peak in the frequency rangefrom 100 Hz to 1 GHz. Fig. 3(b) indicates the measured fre-quency-domain characteristics. The human body behaves as abandpass lter with a bandwidth of about 100 MHz and shows

approximately 6-dB attenuation. This behavior is attributed tothe capacitive coupling through the parasitic ground path for thereturn signal and the small input impedance of 50 . Furtherstudy on the considerable characteristics of the HBC channelsuch as the characteristics versus the distance and the antennaeffect of the body is reported in [10]. According to this investiga-tion, the range of 10 kHz to 100 MHz is founded as the suitablefrequency for the WBS over the HBC channel. Therefore, thewide bandwidth HBC channel enables the WBS transceiver tooperate at the high data rate.

Based on the channel investigation, a HBC channel modelis developed to optimize the performance of the WBS trans-ceiver over the channel. An electrical circuit model of Fig. 4 forthe WBS HBC system with the DCI is obtained by extending aprevious simpli ed electrical circuit model ( , , and

) for the biological tissues [11] to the human body model.The capacitance value of , a parasitic capacitor associatedwith the parasitic air coupling as the return path between theground of the transmitter and the receiver, is very small (severalpF) due to the feeble coupling. and are added asthe transmission loss model associated with the coupling to thereceiver s ground path above about 1 MHz. (50 )and (50 ) are the output and input impedances of thetransmitter and the receiver, respectively. is the inputload capacitance of the receiver. Fig. 5 shows the HBC channel

characteristics simulated by using the circuit model in the timeand frequency domains.


3/13

SONG et al. : A 0.2-MW 2-MB/S DIGITAL TRANSCEIVER BASED ON WIDEBAND SIGNALING FOR HUMAN BODY COMMUNICATIONS 2023

Fig. 2. Measurement setup for the investigation of the HBC channel (a) in the time domain and (b) in the frequency domain.

Fig. 3. Measured characteristics of the HBC channel (a) in the time domain and (b) in the frequency domain.

According to the safety study of the human exposure to theRF signals, the minimum electric eld intensity is 28 V/m overthe frequency range up to 300 GHz for general public exposureto time-varying electric elds [12]. The maximum electric eldintensity is roughly estimated at 20 V/m and the induced dis-

placement current is much less than 45 mA, because the humanbody impedance exhibits the range of 300 to 500 over thefrequency range of 10 kHz to 100 MHz [12]. All measurementconditions meet the ICNIRP guidelines [12] as well as the IEEErecommendations to provide an electrical safety for the humanbody [13].

III. WBS D IGITAL TRANSCEIVER

The HBC transmission is based on the WBS scheme that di-rectly transmits binary digital signal through a transmitter intothe human body, transfers wideband pulse signals over the HBCchannel, and then recovers the binary data at the receiver. TheWBS has two features: simple interface and high data rate ca-pability. The WBS enables the use of only a single electrodefor the data transmission. A transceiver exploiting the WBS is

connected to the human body with a single Ag/AgCl or metalelectrode. The grounds of the transmitter and the receiver areparasitically coupled each other. The earth ground path for areturn signal is not implemented and only the parasitic groundcoupling exists. In addition, since the WBS is independent to

the conditions of surrounding environments such as the earthground, the data transmission using the WBS enables stable op-eration for the situation even if a part of the human body istouched to the ground, which is rather special compared with[6]. The WBS provides the maximum data rate of 125 Mb/s. Ac-cording to the time-domain characteristics as shown in Fig. 3(a),the data rate can go up to about 125 Mb/s because the pulse bitsignal has a width of about 8 ns.

According to the channel investigation, several design re-quirements can be de ned in realizing the data transmissionwith WBS technique. A WBS transceiver operating at the highdata rate of 2 Mb/s can transfer the real-time multimedia datastreams such as MP3 le without any encoding and decoding.For the longer lifetime of a very small battery, a power less than10 mW is required with a 1-V supply. The 1-V supply voltage


4/13


Fig. 4. Electrical circuit model for the WBS HBC system with the DCI.

Fig. 5. Simulated characteristics of the HBC channel using the electrical circuit model (a) in the time domain and (b) in the frequency domain.

is below the sum of the threshold voltage of nMOS and pMOS.This can eliminate short circuit currents for the digital circuits,thereby minimizing unnecessary power consumption [14]. Forthe transmission of the binary data, the nonreturn-to-zero (NRZ)is chosen to enable clock recovery from data transitions withno additional timing reference at the receiver. Accordingly, the

transmitter is designed to drive the NRZ data over the humanbody channel. The receiver requires small input impedance tomove the low-frequency pole away from the origin in the fre-quency spectrum. It can cut off the low-frequency interferencenoises including the baseline wandering below 0.5 Hz and pow-erline interference of 60 Hz. To facilitate the high-speed mea-surements, the 50- impedance was chosen to match with theimpedance of the equipments.

The 3-dB operational bandwidth of about 200 MHz at the re-ceiver is chosen to suf ciently sustain the channel bandwidthwithout inter-symbol interference (ISI) effects. To achieve thetransmission between the ngertip and the ear, corresponding to100-cm distance, the voltage gain should be larger than 30 V/V,and the minimum input sensitivity, the minimum received pulseswing, is to be 10 mV. Since the channel output signal is com-

prised of positive and negative pulses without DC offset, thesymmetric operation is demanded. A clock and data recoveryfunction requires a bit error rate (BER) less than 10 for theembedded clocking which includes the clock timing informa-tion into the data in NRZ data service.

Fig. 6 shows the block diagram of the WBS transceiver that

comprises a direct digital transmitter and a CDR-based WBSreceiver. The direct digital transmitter consists of a clock syn-thesizer, a pseudo-random binary sequence (PRBS) generator, a2-to-1 multiplexer (MUX), and a driver. The clock synthesizerhas a ring oscillator structure and generates the clock signalwith frequency scaling to activate the PRBS generator. ThePRBS generator generates 2 1 PRBS data and transmitsthem through the driver to the human body for on-chip link testing. Also, external binary data such as digitally convertedaudio data or baseband data can be directly transmitted to thehuman body by the 2-to-1 MUX. The driver is connected to theelectrode and induces the electric eld on the skin of the humanbody. The CDR-based WBS receiver consists of a receiverAFE, a CDR circuit, and a bit error detector. The receiver AFEampli es, triggers, inverts, and shifts the received wideband


5/13


Fig. 6. Proposed architecture of the wideband signaling transceiver.

pulse signal in order to recover the binary data. The next CDRcircuit extracts a clean clock signal from the recovered binarydata and latches the data. The bit error detector is integratedfor on-chip BER testing and detects error bits of the recovereddata from the extracted clock for 2 1 PRBS. The transceiveris powered by a supply regulator, which generates the supplyvoltage of 1 V from a 1.5-V battery.

Fig. 7 illustrates the timing diagrams of the WBS transceiver

operation. As investigated in Section II, when the binary datais directly inserted into the human body, the channel outputsa narrow small pulse signal that comprises positive and nega-tive pulses with no DC offset. The received pulse signal whichmay be corrupted by the channel is suf ciently ampli ed forwide bandwidth, and subsequently, the signal is triggered topositive and negative states by using two symmetric thresholds,

and , where the symmetric operation provides the dutycycle of 50%. Consequently, the binary data can be recoveredby inverting and shifting the triggered signal. For CDR at thereceiver, the full-rate clock signal is locked at the center point of the bit interval window. The binary data is recovered by latching

the level-shifted signal at the rising edge of the clock signal.The WBS transceiver should operate over the wide band-width of 200 MHz in order to recover binary data from thewideband pulse signals. However, it increases power dissipationinherently. Particularly, since the receiver AFE and the CDRcircuit are the crucial elements and power-hungry buildingblocks, the low-power techniques are necessary for theirdesigns. For these reasons, the WBS digital transceiver incor-porates four low-power techniques: direct digital transmission,all-digital CDR architecture, low-voltage digitally-controlledoscillator (DCO), and quadratic sampling technique. Thesetechniques allow the WBS digital transceiver to signi cantlyreduce power consumption along with high data rate operation,which results in more energy-ef cient data transmission thanother transceivers [6] [8] over the HBC channel.

Fig. 7. Timing diagrams for the operation of the WBS transceiver.

A. Direct Digital Transmitter

Fig. 8 shows the detailed block diagram of the direct digitaltransmitter. The digital signal can be directly transmitted to the

body by exploiting the WBS scheme. This voltage-mode trans-mission approach can considerably save power consumptionof the HBC transmitter because it needs only an inverter-typedriver without modulation blocks. The clock signal is gener-ated from the ring oscillator and scaled by the frequency divider.The ratio of the frequency dividing is chosen by the 7-bit ther-mometer decoder. The PRBS generator as a binary data sourceis based on the polynomial of . The voltage-modedriver as a single inverter makes it dif cult to maximize thetransmitting power over the body due to the variation of itsoutput impedance. To maximize the transmitting power alongwith the constant output impedance, the driver exploits a doubleinverter topology, combining a single inverter and an identicalinverter with drain resistors. Fig. 9 depicts the schematic dia-grams for three voltage-mode drivers: a single inverter, an iden-


6/13


Fig. 8. Detailed block diagram of the direct digital transmitter.

Fig. 9. Schematicdiagramsfor three voltage-modedrivers:(a) a singleinverter,(b) an identical inverter with drain resistors, and (c) a double inverter in thecombination with (a) and (b).

tical inverter with drain resistors, and a double inverter. Fig. 10illustrates the contour lines of the output impedance for threevoltage-mode drivers, plotting the amount of the current trans-ferred to the body as a function of the voltage at the driver soutput. Since the body impedance exhibits the range of 300to 500 over the frequency band with 100 MHz as mentioned inSection II, the transistor s size (35 m/10 m) is large enoughto drive the large human body capacitance (about 15 pF) andthe drain resistor (200 ) is chosen for matching to the bodyimpedance. The driver s output impedance is constant to almost

400 by controlling the output impedance of each inverter withthe input voltage as shown in Fig. 10(c). It indicates that thetransmitting power increases almost two times more than theconventional approaches. Accordingly, the proposed double in-verter topology allows the increase of the transmitting powerwhile maintaining its output impedance.

B. WBS Receiver AFE

According to the channel investigation, the output signal of the channel shows narrow small pulse signals with no DC offset,when the binary data is directly applied to the human body bya single electrode. These characteristics seem to be similar withthe AC-coupled chip-to-chip interconnect using 50- transmis-sion lines on a FR-4 PC board shown in [15]. The pulse re-ceiver used in the AC-coupled interconnect achieves high data

rate of several Gb/s. However, it had a differential structure

and poor receiver sensitivity more than 100 mV with a 1.8-Vsupply. The WBS transceiver requires that the input sensitivityof a receiver AFE should to be less than 10 mV for the 50-input impedance. Fig. 11 shows the block diagram of the ex-ternal WBS receiver AFE consisting of three blocks: a wide-band preampli er, a Schmitt trigger, and a level shifter. TheAFE accomplishes four tasks: amplifying, triggering, inverting,and shifting. Signal waveforms at each output are the same asthose in Fig. 7. The wideband preampli er is designed as anoninverting opamp with a wide bandwidth that provides suf-cient ampli cation to the received pulse although it is cor-rupted by the channel. The next Schmitt trigger stably triggers

the output of the preampli er to positive and negative states withtwo thresholds against the variation of the received pulse swing.The Schmitt trigger consists of three resistors ( - ) and thesame opamp as that of the preampli er. It produces positiveand negativetriggering threshold voltages ( and ). Eachthreshold voltage is chosen as the value of two times smallerthan the output swing of the preampli er, enough to trigger atthe half of the pulse signal. Thus, and are expressed as

(1)

(2)

respectively, where and are the receivedpositive andnegative pulse swings, respectively, is the voltage gain of the preampli er given as , 10 V/V in this design, and

is the supply voltage of the AFE, 1.5 V in this design. Ac-cording to the design requirements of the WBS transceiver, theminimum input pulse swing is 10 mV. Hence, the values of and are 50 mV and 50 mV, respectively. Subsequently,the output signal is inverted and shifted up to ground level bythe bias voltage of for the digital input atthe next CDR circuit. The level shifter can be implemented by


7/13


Fig. 10. Contour lines of the output impedance for three voltage-mode drivers: (a) a single inverter, (b) an identical inverter with drain resistors, and (c) a doubleinverter.

Fig. 11. Block diagram of the WBS receiver AFE.

Fig. 12. Quadratic sampling CDR architecture based on a low-voltage DCO.

using an inverting opamp with the reference voltage of .In order to verify the performance of the external receiver AFE,an on-chip AFE is implemented by using a 0.18- m standardCMOS process [16]. The AFE can operate at 10 Mb/s whileconsuming a power of only 4.8 mW with a 1-V supply.

C. Quadratic Sampling CDR Circuit

In human body communications, a stream of the binary datatransfers over a human body with no clock accompanied, buta receiver must process the data synchronously. Thus, to ex-tract a clean clock from the stream of the binary data and syn-chronize the data by the extracted clock, the WBS digital trans-

ceiver employs a CDR circuit that is exploited in areas suchas optical communications and high-speed serial links or inter-connects [17]. Since the transceiver operates at relatively lowdata rates for the recovered binary data, differently from gigabitserial links [17], bandwidth-limited effects such as ISI or am-plitude noise and clock frequency offset between a transmitterand a receiver are tolerable in the WBS transceiver. Hence, itis desirable for the CDR circuit to be focused on low powerconsumption rather than high-speed operation. However, underthe condition of V, an analog CDR circuitmay experience performance degradation. But the power dis-sipation of digital circuitry is proportional to the square of the


8/13


Fig. 13. Circuit diagram of a single delay stage of the low-voltage DCO.

Fig. 14. (a) Timing operation and (b) detailed block diagram of the QSPD.

supply voltage. Therefore, the transceiver adopts an all-digitalsampling CDR architecture based on a low-voltage DCO. Tofurther reduce power consumption and complexity, a quadraticsampling technique is incorporated. The proposed CDR circuittakes an all-digital PLL con guration as shown in Fig. 12. Itconsists of a quadratic sampling phase detector (QSPD), a lock-state controller, a 4-bit UP/DN counter, and a low-voltage DCOwith voltage reference. The QSPD samples the incoming dataat every rising edge of the clock and detects the transition of the data. The 4-bit FT signals can be generated by averagingand low-pass ltering the sampled values through the lock-stagecontroller and the 4-bit UP/DN counter. When the LC signal of Fig. 12 goes high, the loop will be locked. The DCO controlled

Fig. 15. Simulated QSPD characteristic.

by FT[3:0] is designed to generate 16 multi-phase clock sig-nals for quadratic sampling. In order to further reduce powerconsumption, the low-voltage DCO and the quadratic samplingtechnique are used.

Fig. 13 shows the circuit diagram of a single delay stage of the low-voltage DCO with eight delay stages. The pMOS dif-ferential input pair ( ) is used to achieve lower ickernoise and large input capacitance. The delay stage takes a fullydifferential structure based on the switched nMOS capacitor ar-rays ( and ) that are digitally controlled byFT[3:0] for ne tuning [18]. To secure stable oscillation againstthe variation of the resistor loads ( ), the cross-coupledpair ( ) is adopted in parallel with - . The incre-mentaltiming delay oftheunit capacitance ( ),25 fF inthisdesign, should be smaller than a sampling time interval forthe stability of the capture behavior. For coarse tuning of the os-cillation frequency of the DCO, the signal, generated bya voltage reference with off-chip trimming, controls the amountof the tail current ( ). The bias capacitor pair ( ) is


9/13


Fig. 16. (a) Quadratic sampling algorithm and (b) comparison of the PD characteristics in the conventional and proposed CDRs.

Fig. 17. Acquisition behavior for the quadratic sampling CDR circuit.

needed to improve the linearity of the DCO gain characteris-tics. According to the simulations, the tuning range of the DCOshows 1.1 MHz with the tuning gain of 60 kHz/bit. The powerconsumption of the single delay stage is only 14 W.

Fig. 14(a) illustrates the timing operation of the QSPD. Theincoming data (DIN) is sampled by the 16 sampling clocks(CK0 CK15) with a uniform interval between sampling clocks.A bit interval window of the DIN is split into seven regionswith respect to the position of the data transition. Each regionhas the quadratic interval, which is based on bilateral symmetrywith region 4 as the central region. When the data transition is

at regions 1, 2, or 3, the down signal (DN4, DN2, or DN1) goeshigh, respectively. The LC signal goes high for region 4. Threeup signals (UP1, UP2, and UP4) show the same operation asthe down signals at regions 5, 6, and 7, respectively. Fig. 14(b)shows the detailed block diagram of the QSPD for the timingoperation. Fig. 15 plots the simulated QSPD characteristic,indicating the difference of the UP[2:0] and DN[2:0] signals asa function of the delay between the sampling clock CK0 and theinput data DIN. The output of the QSPD shows the seven-levelphase detection (solid line). Thus, the OSPD accomplishes thequadratic phase detection (dash line) by averaging and low-passltering through the lock-state controller and the 4-bit UP/DNcounter.

Fig. 16 illustrates the proposed quadratic sampling algorithmin (a) and the comparison of the PD characteristics between the

Fig. 18. Microphotograph of the test chip.

proposed quadratic sampling (solid line) and the conventionallinear sampling (dash line) in (b). The QSPD generates the 3-bitUP, LC , and 3-bit DN signals that are produced by XOR ing twoconsecutive bits of the DIN signal with the quadratic intervalwindow. All of them are converted to 4-bit two s complementvalues before weighting and averaging functions. To avoid po-tential loop instability, the averaged values are low-pass lteredby a simple digital lter. Then, the low-pass ltered values areused to generate the UDN and CCK signals. Based on this al-

gorithm, the QSPD provides the quadratic gain over a bit in-terval window as depicted in Fig. 16(b). To acquire the samePD gain with the sampling time interval ( ), the conventionalCDR with a linear PD needs 32 sampling clocks in the FT[3:0]range of 0100 to 1100. It leads to the increase of the number of the VCO delay stages as well as the sampling block in the PD.Hence, the linear PD characteristic should be paid additionalpower consumption and area costs. In other words, with the helpof the quadratic gain characteristics, the number of samplingclock signals can be reduced by a factor of two against the linearapproach. Therefore, the quadratic sampling can further reduceboth the powerconsumption and the area overhead. Fig. 17 illus-trates the simulated acquisition behavior of the quadratic sam-pling CDR circuit, plotting the code value of the 4-bit FT signalsas a function of time. Its acquisition time is about 45 s.


10/13


Fig. 19. Photograph of the test board.

Fig. 20. Photograph of the test measurement setup.

IV. M EASUREMENT RESULTS

The proposed WBS digital transceiver is fabricated witha 0.25- m standard 1P4M CMOS technology, where thethreshold voltage for nMOS and pMOS at saturation regionare 0.6 V and 0.65 V, respectively. Fig. 18 shows the mi-crophotograph of the test chip, including the WBS digitaltransmitter and receiver. Its core area is about 0.85 mm . Atest board powered by a 1.5-V battery is shown in Fig. 19.The metal electrode on the test board is composed of a goldplate with the size of 5 mm 7 mm. The Ag/AgCl electrode,2 cm in diameter, is also connected to the board. The electrodefor the signal transmission is chosen between the metal andAg/AgCl electrodes by using a slide switch on the board. Thetransceiver chip was mounted on the FR-4 PC board by using

Fig. 21. Measured eye diagrams of the WBS digital transceiver for 2-Mb/s2 0 1 PRBS.

Fig. 22. Measured eye diagrams of the WBS receiver AFE for 2-Mb/s 2 0 1PRBS.

chip-on-board assembly. The board size is about 6 cm by10 cm. All measurements are conducted between the wrist andthe ngertip, which corresponds to the distance of about 25 cmas shown in Fig. 20. A WBS transmitter board is attached to thewrist using a single Ag/AgCl electrode on the backside. Whenthe ngertip touches the metal electrode on a WBS receiverboard, the stream of the binary data is transferred through thebody to the WBS receiver board.

Fig. 21 shows the measured eye diagrams of each outputof the direct digital transmitter, the HBC channel, the receiverAFE, and the recovered clock and data of the CDR circuit for2-Mb/s 2 1 PRBS data, respectively. The channel output of the binary data exhibits the narrow small pulse signals with the


11/13


Fig. 23. Measured jitter histograms of (a) the recovered clock output and (b) the recovered data output for 2-Mb/s 2 0 1 PRBS.

Fig. 24. Free-running characteristics of the DCO.

amplitude of about 50 mV and no DC offset. Fig. 22 shows themeasured eye diagrams of each output of the wideband pream-

plier, the Schmitt trigger, and the level shifter at the WBS re-ceiver AFE for 2-Mb/s 2 1 PRBS data, respectively. The re-covered clock and data jitter are measured to be 1.6 ns rms and1.7 ns rms, respectively, as shown in Fig. 23. Fig. 24 showsthe simulated and measured free-running characteristics of theDCO, plotting after slightly controlling the amount of the tailcurrent. This plot indicates that the measured DCO gain andtuning range are about 40 kHz/bit and 800 kHz, respectively.The frequency difference between the simulated and measuredcurves is attributed to the variation of the unit capacitance inthe switched nMOS capacitor array. Since the capacitor arrayis laid out in symmetry with copying of a unit capacitor to

minimize the mismatches between capacitors, the DCO char-acteristics keep positive linearity over the full tuning range asshown in Fig. 24. Thus, there is no malfunction on the fre-quency and phase tracking in accordance with the measurementresults. The measured receiver input pulse swing as a func-tion of the communication distance from the ngertip to theear for 2-Mb/s 2 1 PRBS data is shown in Fig. 25. The mea-surement for the receiver input pulse swing is conducted be-tween a ngertip and an ear, corresponding to the communica-tion distance of 100 cm to prove the feasibility of the data trans-mission over a human body for an audio application utilizingthe proposed HBC scheme. It indicates that the receiver inputpulse swing rapidly decreases to the minimum input sensitivityof 10 mV, where the BER is measured to be about 1.1with the on-chip bit error detector by counting error bits for

Fig. 25. Measured receiver input pulse swing as a function of the communica-tion distance.

TABLE IPERFORMANCE SUMMARY OF THE PROPOSED WBS D IGITAL TRANSCEIVER

2 1 PRBS data. The overall digital transceiver chip consumes0.2 mW from a 1-V supply.

Table I summarizes the performance of the proposed WBSdigital transceiver. The performance comparison with previousworks is summarized in Table II. The power consumption of anon-chip receiver AFE for the WBS transceiver is 4.8 mW [16].Thereby, the WBS transceiver including the receiver AFE dis-sipates a total power of 5 mW and achieves the transmission bit


12/13


TABLE IIPERFORMANCE COMPARISON W ITH OTHER HBC T RANSCEIVERS

energy of 2.5 nJ/bit, which is 26 times more ef cient than otherHBC transceivers introduced in [6] [8]. Hence, the proposedWBS digital transceiver achieves low power and high data rateoperation suitable for energy-ef cient data communications forBANs.

V. C ONCLUSION

A novel HBC scheme is proposed and implemented for en-ergy-ef cient data communications using the human body as a

data transmission medium. From the investigation of the HBCchannel using the DCI, the human body behaves as a bandpasslter with a bandwidth of 100 MHz and the channel output ex-hibits the narrow small pulse signals with a width of 8 ns. Theproposed HBC scheme exploits WBS technique with the DCIover the optimized HBC channel. For the convenience of usage,the DCI uses only a single electrode without an extra groundelectrode for data transmission. With the help of four low-powertechniques such as direct digital transmission, all-digital CDRarchitecture, low-voltage DCO, and quadratic sampling tech-nique, the WBS digital transceiver achieves 2-Mb/s operationwith power consumption of 0.2 mW from a 1-V supply. The

minimum input sensitivity of the receiver exhibits about 10 mVat a BER of 1.1 in the range of the communication dis-tance of 100 cm.

REFERENCES[1] S. Kim, J.-Y. Lee, S.-J. Song, N. Cho, and H.-J. Yoo, An

energy-ef cient analog front-end circuit for a sub-1-V digital hearingchip, IEEE J. Solid-State Circuits , vol. 41, no. 4, pp. 876 882,Apr. 2006.

[2] R. L. Ashok and D. P. Agrawal, Next-generation wearable networks, IEEE Computer Mag. , vol. 36, no. 11, pp. 31 39, Nov. 2003.

[3] T. B. Remple, USB on-the-go interface for portable devices, in Proc. IEEE In t. Conf. Consumer Electronics , 2003, pp. 8 9.

[4] H. Komurasaki, T. Sano, T. Heima, K. Yamamoto, H. Wakada,I. Yasui, M. Ono, T. Miwa, H. Sato, T. Miki, and N. Kato, A

1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSKapplications, IEEE J. Solid-State Circuits , vol. 38, no. 5 , pp.817 825, May 2003.

[5] S. Verma, J. Xu, M. Hamada, and T. H. Lee, A 17-mW 0.66-mmdirect-conversion receiver for 1-Mb/s cable replacement, IEEE J.Solid-State Circuits , vol. 40, no. 12, pp. 2547 2554, Dec. 2005.

[6] T. G. Zimmerman, Personal Area Networks (PAN): Near- eld intra-body communication, M.S. thesis, MIT, Cambridge, MA, 1995.

[7] K. Hachisuka, A. Nakata, T. Takeda, Y. Terauchi, K. Shiba, K. Sasaki,H. Hosaka, and K. Itao, Development and performance analysis of an intra-body communication device, in Proc. Transducers 03 , Jun.2003, pp. 1722 1725.

[8] M. Shinagawa, M. Fukumoto, K. Ochiai, and H. Kyuragi, A near-eld-sensing transceiver for intrabody communication based on theelectrooptic effect, IEEE Trans. Instrum. Meas. , vol. 53, no. 6, pp.

1533 1538, Dec. 2004.[9] J. A. Ruiz, J. Xu, and S. Shimamoto, Propagation characteristicsof intra-body communications for body area networks, in Proc. IEEE Consumer Communications and Networking Conf. , 2006, pp.509 513.

[10] N. Cho, J. Yoo, S.-J. Song, S. Kim, and H.-J. Yoo, The human bodycharacteristics as a signal transmission medium for intra body commu-nication, IEEE Trans. Microw. Theory Tech. , to be published.

[11] L.C. Ward, N.M. Byrne, K.Rutter, L.Hennoste, A.P. Hills,B. H. Cor-nish, and B. J. Thomas, Reliability of multiple frequency bioelectricalimpedance analysis: An intermachine comparison, Amer. J. Human Biol. , vol. 9, pp. 63 72, 1997.

[12] Int. Commission on Non-Ionizing Radiation Protection (ICNIRP),Guidelines for limiting exposure to time-varying electric, magnetic,and electromagnetic elds (up to 300 GHz), Health Phys. , vol. 74,pp. 494 522, 1998.

[13] IEEE Standard for Safety Levels with Respect to Human Exposureto Radio Frequency Electromagnetic Fields, 3 Hz to 300 GHz , IEEEC95.1-1991, 1999.

[14] H. Neuteboom, B. M. J. Kup, and M. Janssens, A DSP-based hearinginstrument IC, IEEE J. Solid-State Circuits , vol. 32, no. 11, pp.1790 1806, Nov. 1997.

[15] L. Luo,J. M.Wilson,S. E.Mick, J.Xu, L.Zhang, and P.D. Franzon, 3Gb/s AC coupled chip-to-chip communication using a low swing pulsereceiver, IEEE J. Solid-State Circuits , vol. 41, no. 1, pp. 287 296, Jan.2006.

[16] S.-J. Song, N. Cho, S. Kim, and H.-J. Yoo, A 4.8-mW 10-Mb/s wide-band signaling receiver analog front-end for human body communica-tions, in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC) , 2006, pp.488 491.

[17] S.-J. Song, S. M. Park, and H.-J. Yoo, A 4-Gb/s CMOS clock and datarecovery circuit using 1/8-rate clock technique, IEEE J. Solid-StateCircuits , vol. 38, no. 7, pp. 1213 1219, Jul. 2003.

[18] S. B. Anand and B. Razavi, A 2.75 Gb/s CMOS clock recovery cir-cuit with broad capture range, in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers , 2001, pp. 214 215.


13/13


Seong-Jun Song (S01) received the B.S. ( summacum laude ) andM.S. degrees in electrical engineeringand computer science from the Korea Advanced In-stitute of Science and Technology (KAIST), Daejeon,Korea, in 2001and 2004, respectively. He is currentlyworking toward the Ph.D. degree in electrical engi-neering and computer science from KAIST.

Since 2001, he has been a Research Assistant at

KAIST, where he worked on developing high-speedoptical interface integrated circuits using submicronCMOS technology, phase-lockedloops and clock and

data recovery circuits for high-speed data communications, and radio-frequencyCMOS integrated circuits for wireless communications. His currentresearch in-terests include ultra low-power wearable/implantable biomedical microsystemsand energy-ef cient communication systems for bodyarea andsensor networks.

Namjun Cho (S04) received the B.S. ( summa cumlaude ) and M.S. degrees from the Korea AdvancedInstitute of Science and Technology (KAIST),Korea, in 2004 and 2006, respectively. He is cur-rently working toward the Ph.D. degree at KAIST.

He has worked on developing UHF RFID tag chipintegrated with environmental monitoring sensorsand the low-power digital-to-analog converter forhearing aid system. His current research interestsinclude low-power biomedical microsystems and thewireless transceivers for body area networks.

Hoi-Jun Yoo (M 95SM 04) graduated from theElectronic Department of Seoul National Univer-sity, Seoul, Korea, in 1983 and received the M.S.and Ph.D degrees in electrical engineering from theKorea Advanced Institute of Science and Technology(KAIST), Daejeon, in 1985 and 1988, respectively.His Ph.D. work concerned the fabrication processfor GaAs vertical optoelectronic integrated circuits.

From 1988 to 1990, he was with Bell Communi-cations Research, Red Bank, NJ, where he inventedthe two-dimensional phase-locked VCSEL array, the

front-surface-emitting laser, and the high-speed lateral HBT. In 1991, he becameManager of a DRAM designgroup at Hyundai Electronics anddesigneda familyof fast-1 MDRAMs and synchronousDRAMs, including 256M SDRAM. From1995 to 1997, he was a faculty member with Kangwon National University.In 1998 he joined the faculty of the Department of Electrical Engineering atKAIST. In 2001, he founded a national research center, System Integration andIP Authoring Research Center (SIPAC), funded by Korean government to pro-mote worldwide IP authoring and its SOC application. From 2003 to 2005, hewas the Project Manager for SoC in Korea Ministry of Information and Com-munication. His current interests are SOC design, IP authoring, high-speed andlow-power memory circuits and architectures, design of embedded memorylogic, optoelectronic integrated circuits, and novel devices and circuits. He isthe author of the books DRAM Design (Seoul, Korea: Hongleung, 1996; in Ko-rean) and High Performance DRAM (Seoul, Korea: Sigma, 1999; in Korean).

Dr. Yoo received the Electronic Industrial Association of Korea Award forhis contribution to DRAM technology in 1994 and the Korea SemiconductorIndustry Association Award in 2002.

A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications

Documents

Transcript of A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications