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We used to implement our designs by

hand-writing Register ranser Level

(RL) code. While this approach produces

a relatively small chip area , it leads to long

development times, and any subsequent

changes to requirements can result in sig-

niicant rework o the implementation.

his approach also car ries some risk rom

a business perspective: We oten do notknow how diicult it will be to place and

route the design until t he very end o the

design process, when it is all but impos-

sible to make changes and still meet our

release date.

We have adopted a new approach, one

in which we design in MALAB and use

Filter Design HDL Coder to generate

synthesizable RL code. By connecting

system design to silicon, this approachenables us to rapidly evaluate ilter archi-

tectures and optimize or silicon area. It

has reduced our RL code development

cycle rom three months to less than two

weeks. System modiications that used to

take al most a month to complete can now

be made in as little as three days.

Engineering an audio codec flter chain requires a careful balance of

performance, power, and size. Our group must design solutions that not only

meet rigorous standards for signal-to-noise ratio (SNR) and total harmonic

distortion (THD), but also minimize power consumption and the total area of

silicon required on the chip.

Automatic Hardware Implementation ofDigital Filters for an Audio Codec

MATLAB Digest

Digital

Decoder

Digital

Encoder

Serial

Port

Interface

DigitalSignal

Processor

DAC

Left

DAC

Right

ADC

Left

ADC

Right

PGA

Left

PGA

Right

Preamp

Left

Preamp

Right

Headphone

Left

Headphone

Right

Microphone

Left

Microphone

Right

Audio Codec

FBB = 48 kHz FConv = 6.5 MHz Analog Circuits

Figure 1. High-level block diagram o the audio codec.

Architecting an Audio Codec

Audio codec consists o two separate process-

ing chains (Figure 1). Te audio encoder

provides the interace rom the microphone

to the digita l signal processor (DSP). Te

audio decoder works in the opposite direc-

tion, converting signals rom the DSP to data

that is sent to the speaker.

A key technical challenge in the systems

that we design is that both the analog-to-

digita l converter (ADC) that ollows the

microphone preamplier and the digital-to-

analog converter (DAC) that precedes the

loudspeaker power amplier must operate

at the relatively high requency o 6.5 MHz.

by MediaTek Inc.

Products Used MATLAB

Filter Design Toolbox

Filter Design HDL Coder

Signal Processing Toolbox

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On the other hand, the DSP processes data at

a common rate o 48 kHz. Te digital section

o the audio codec converts between these

two requencies by applying a series o digital

lters. Te stereo encoder channel, or exam-

ple, uses eight lters to decimate its input

signal, while the stereo decoder uses nine

lters to interpolate its input signal.

In the architecture phase o design, we use

MALAB to model the encoder and decoder

channels. Using parameters provided by our

analog designers, we model digital-to-analog

and analog-to-digital converters and con-

struct multirate digital ltering chains.

Next, we use MALAB, Signal Processing

oolbox, and Filter Design oolbox to post-

process the results produced by the model by

calculating ast Fourier transorms (FFs)

and estimating SNR and HD. In this way,

we can work out an optimized architecture

beore moving to implementation.

Implementation Using a FiniteState Machine Sequencer

In our previous design methodology, we useda single multiplier-accumulator (MAC) and

a nite state machine sequencer to imple-

ment the signal processing chain (Figure 2).

Te sequencer is responsible or addressing

the RAM and ROM and controlling their

operations. It also sets the input arguments

or the MAC. Te ROM stores lter coe-

cients, the RAM stores intermediate multiply-

accumulate results, and the MAC perorms

the calculations based on the coefcients and

data samples.

raditionally, the sequencer was designed

using a pencil-and-paper process that was

complex and time-consuming. Te hand-

written RL code was so inexible that

even small modications proved dicult.

On occasion, we also ound that the RL

code or the sequencer nite state machine

Sequencer

RAM

ROMROM

MAC

Addr Coefficient

Signal outputSignal input

Result

Addr CoefficientData Data

48 kHz(6.5 MHz)

6.5 MHz(48 kHz)

Figure 2. Block diagram o a traditional audio codec design.

Figure 3. The new design architecture, in which each flter is implemented independently using FilterDesign HDL Coder. R1, R2, and Rn represent the rate change (interpolation/decimation) o the frst,second, and nth flter in the chain.

was almost impossible to place and route.

Tere were about 2,000 states in the nite

state machine with more than 40 variables

assigned in these states. Tis resulted in a

very low area uti lization ratio o 10% dur-

ing placement and routing o the gate-level

netlist. In other words, the proposed silicon

area was 10 times greater than anticipated!It took a tremendous eort to synthesize the

sequencer logic into a custom ROM memory.

Yet stil l there was about 2x area penalty or

the sequencer over our initial projection or

the combinatorial logic (custom ROM usually

needs more silicon area).

Automating Implementation

In our new design methodology, we have

eliminated the complex sequencer. Instead,

we use a series o digital lters designed

with MALAB and Filter Design oolbox

and implemented with Filter Design HDL

Coder (Figure 3). Each digital lter block

operates independently so that it can beeasily modied, removed, or added to the

overall chain.

Te decoder chain includes our hal-band

FIR lters and a sample rate converter. Each

lter interpolates by two, taking the initial

48 kHz signal to 96 kHz, 192 kHz, 384 kHz,

and 768 kHz, respectively. A sample rate

converter then converts directly rom 768

kHz to the target requency, 6.5 MHz.

6.5 MHz(48 kHz)

ROMR1 DigitalFilter 1 ROMRnDigitalFilter nROMR2

DigitalFilter 2

48 kHz(6.5 MHz)

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Te encoder chain includes two cascaded

integrator-comb (CIC) decimators, as well as

two halfand FIR lters. Te rst CIC deci-

mator decimates by 25 rom a channel input

rate o 6.5 MHz down to 260 kHz. It is ol-

lowed by a simple, hand-written interpolate-

by-48 zero stuer. Interpolated data at a rate

o 12.48 MHz is then subjected to decimation

by 65 within the second CIC decimator. It is

later processed at a rate o 192 kHz within

rst halfand FIR decimation-by-2 lter.

Finally, the second halfand decimation

lter downsamples data rom 96 kHz to the

channel output rate o 48 kHz. In the case o

the encoder channel, Filter Design oolbox

simplied the CIC design by enabling us to

rapidly evaluate numerous design options,

such as the number o bits to use.

Generating RTL Code andOptimizing for Area

Aer designing the individual lters in the

encoder and decoder chains, we generated

Verilog code or each lter using Filter Design

HDL Coder (Figure 4). At this stage, we could

begin optimizing the implementation to min-

imize the silicon area o the design.

We tried several Filter Design HDL Coder

optimization and architecture options or

RL generation. For example, to optimize the

halfand FIR lters, we rst tried an option

that produces a ully parallel architecture in

which the lter clock rate is the same as the

data rate. We then used Synopsys Design

Compiler to synthesize the code and report

on the area allotted. Te distributed arith-

metic option in Filter Design HDL Coder,

which required a clock rate 16 to 20 times

higher than its data rate, produced a design

that used about 25% o the area o the ully

parallel design. Since we have a suciently

high requency clock already available on our

chip, this was the best choice.

Figure 4. Filter Design HDL Coder interace showing part o the flter architecture and a

segment o generated code.

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Verifying the Implementation

We used MALAB scripts, RL test benches,

and Verilog simulations to veriy the RL

implementation. In act, we reused many o

the MALAB scripts developed in the archi-tecture phase to generate stimulus signals and

post-process the results by plotting FFs and

calculating SNR and HD.

Aer this rst round o verication, we

passed the RL code to our colleagues or

synthesis. Te place-and-route step o the

synthesis produces timing data in an SDF

(standard delay ormat) le. We included this

timing data in another round o gate-level

simulations to ensure that there were no raceconditions in the logic. Te design was then

sent o or abrication.

ests o the initial chip run uncovered no

problems whatsoever with the digital por-

tion o the audio codec. Tis meant that our

team was ree to lend a hand with the analog

parts o the design and with the rest o the

testing eort.

The Effect of Newer FabricationTechnology

Changes in abrication technology are shi-

ing the balance o analog and digital com-

ponents on the chips that we design. While

analog transistors must maintain a certain

size to drive their required loads, digital

transistors shrink when a new abrication

process is introduced. When migrating rom

a 0.25um to a 45nm abrication process, or

example, the overall area o a mixed-signal

audio codec went rom 50% digital and 50%analog to 25% digital and 75% analog.

While our new design methodology

requires more silicon area than our

traditional methodology, reductions in the

size o digital components in the new abri-

cation processes osets this increase while

allowing us to retain substantial development

time savings.

In the uture, it might be possible to ur-

ther optimize our design process by using

other low-area architectures oered by

Filter Design HDL Coder, such as part ly serial

architectures, or by implementing the single

sequencer architecture with automatically

generated code.

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