8.my recent doc

7/26/2019 8.my recent doc

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CHAPTER 1

OVERVIEW OF THESIS

1.1 INTRODUCTION

WIRELESS LAN (WLAN) in the multigigahertz bands, such as Hiper LAN II

and IEEE 8!"##a$b$g, are rec%gnized as leading standards &%r high'rate data

transmissi%ns, and standards lie IEEE 8!"#"* are rec%gnized &%r l%+'rate data

transmissi%ns" he demand &%r l%+er c%st, l%+er p%+er, and multiband R- circuits

increased in c%n.uncti%n +ith need %& higher le/el %& integrati%n" he &re0uenc1

s1nthesizer, usuall1 implemented b1 a 2hase'L%ced L%%p (2LL), is %ne %& the p%+er'

hungr1 bl%cs in the R- &r%nt'end and the &irst'stage &re0uenc1 di/ider c%nsumes a large

p%rti%n %& p%+er in a &re0uenc1 s1nthesizer" 31namic latches are &aster and c%nsume less

p%+er c%mpared t% static di/iders" he &re0uenc1 s1nthesizer rep%rted in uses a prescaler

as the &irst'stage di/ider, but the di/ider c%nsumes 2%+er" 4%st IEEE 8!"##a$b$g

&re0uenc1 s1nthesizers empl%1 S5L di/iders as their &irst stage, +hile d1namic latches

are n%t 1et ad%pted &%r multiband s1nthesizers" In this paper, a d1namic l%gic multiband

&le6ible integer'N di/ider based %n pulse's+all%+ t%p%l%g1 is pr%p%sed +hich uses a

l%+'p%+er +ideband *$ prescaler and a +ideband multi m%dulus 7*$7$9$8 prescaler"

he di/ider als% uses an impr%/ed l%+'p%+er l%adable bit'cell &%r the S+all%+ S c%unter"

he &re0uenc1 s1nthesizer is %ne %& the basic building bl%cs in m%dern

c%mmunicati%n s1stems" he %perating &re0uenc1 %& the &re0uenc1 s1nthesizer is limited

b1 the &re0uenc1 di/ider and the :%ltage'5%ntr%lled ;scillat%r" he &uncti%n %& channel

selecti%n in the &re0uenc1 s1nthesizer demands pr%grammable di/isi%n rati%s &%r the

&re0uenc1 di/ider" he integer'N &re0uenc1 s1nthesizer is m%re practical, less c%stl1 and

%& l%+ spuri%us sideband per&%rmance as c%mpared +ith the &racti%nal'N &re0uenc1

s1nthesizer" It is usuall1 &%rmed b1 a prescaler, a 2r%gram 5%unter (2 c%unter) and a

S+all%+ 5%unter(S c%unter)" Such a t%p%l%g1 can pr%/ide a pr%grammable di/isi%n rati%

%& N2 < S, +here N, 2 and S are the di/isi%n rati%s %& three bl%cs respecti/el1" he

prescaler pr%/ides a dual'm%dulus %& N=N


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he 2 c%unter pr%/ides a &i6ed di/isi%n rati% acc%rding t% the re0uirement %& the

%/erall di/isi%n rati%, +hile the c%ntinu%us di/isi%n rati%s &r%m t% *8 is achie/ed

thr%ugh the S c%unter b1 peri%dicall1 rel%ading the di/ide'b1'! stages, +here n is the

number %& stages %& the S c%unter" he c%ntinu%us di/isi%n rati% is used t% select the

desired channels" 4uch research has been &%cused %n the prescaler design &%r its highest

%perating &re0uenc1" H%+e/er, in the m%dern c%mmunicati%n s1stem, there is an

increasing demand &%r multi'standards applicati%ns" he re0uirement &%r +ide band and

high res%luti%n %perati%ns c%ntinue t% be the pr%blems" % satis&1 these re0uirements,

di&&erent re&erence &re0uencies, and di&&erent arrangement &%r N, 2 and S c%unters are

selected &%r di&&erent applicati%ns" In this pr%.ect, a ne+ +ide'band high res%luti%n

pr%grammable &re0uenc1 di/ider is pr%p%sed" he +ide band and high res%luti%n are

%btained b1 using the all'stage pr%grammable t%p%l%g1 in b%th c%unters"

he high'speed &re0uenc1 di/ider is a e1 bl%c in &re0uenc1 s1nthesis" he

prescaler is the m%st challenging part in the high'speed &re0uenc1'di/ider design because

it %perates at the highest input &re0uenc1" A dual'm%dulus prescaler usuall1 c%nsists %& a

di/ide'b1'!$> (%r *$) unit &%ll%+ed b1 se/eral as1nchr%n%us di/ide'b1'! units" he

%perati%n %& the di/ide'b1'!$> unit at the highest input &re0uenc1 maes it the b%ttlenec

%& the prescaler design" % achie/e the t+% di&&erent di/isi%n rati%s, 3 -lip'-l%ps (3--s)

and additi%nal l%gic gates, +hich reduce the %perating &re0uenc1 b1 intr%ducing an

additi%nal pr%pagati%n dela1, are used in the unit" he p%+er c%nsumpti%n %& this di/ide'

b1'!$> unit, +hich is the greatest p%rti%n %& the t%tal p%+er c%nsumpti%n in the prescaler,

signi&icantl1 increases due t% the p%+er c%nsumpti%n %& the additi%nal c%mp%nents"

!


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CHAPTER 2

LITERATURE SURVEY

2.1 A 13.5-mW 5-GHz fre!e"#$ %$"&'e%(zer )(&' *$"+m(#-,(# fre!e"#$ *(/(*er-

Le/+"&("0 S. S+mr(0 C. L+#+(&+0 A.L.-Fe. 24.

DESCRIPTIONhe ad%pti%n %& d1namic di/iders in 54;S 2hase'L%ced L%%ps &%r

multigigahertz applicati%ns all%+s t% reduce the p%+er c%nsumpti%n substantiall1 +ith%ut

impairing the phase n%ise and the p%+er suppl1 sensiti/it1 %& the 2hase'L%ced L%%p

(2LL)" A '?Hz &re0uenc1 s1nthesizer integrated in a "!'@m 54;S techn%l%g1

dem%nstrates a t%tal p%+er c%nsumpti%n %& #>" mW" he &re0uenc1 di/ider c%mbines

the c%n/enti%nal and the e6tended true'single'phase'cl%c l%gics" he %scillat%r empl%1s

a rail't%'rail t%p%l%g1 in %rder t% ensure a pr%per di/ider &uncti%n" his 2LL intended &%r

+ireless LAN applicati%ns can s1nthesize &re0uencies bet+een "#* and " ?Hz in

steps %& ! 4Hz A l%+'p%+er '?Hz 54;S &re0uenc1 s1nthesizer &%r +ireless LAN

transcei/ers has been presented" he 2LL integrated in a "!' m 54;S techn%l%g1

c%nsumes %nl1 #>" mW, thans t% a d1namic S25 di/ider" his class %& di/iders is

dem%nstrated t% be suitable &%r multigigahertz s1nthesizers, since it d%es n%t impair the

p%+er suppl1 re.ecti%n %r the phase n%ise per&%rmance" WIRELESS LAN s1stems in the

7'?Hz band, such as HiperLAN II and IEEE 8!"##a, are rec%gnized as the leading

standards &%r high'rate data transmissi%ns" Being intended &%r m%bile %perati%ns, the

radi% transcei/er has a limited p%+er budget" he &re0uenc1 s1nthesizer, usuall1

implemented b1 a 2hase'L%ced L%%p (2LL), is %ne %& the m%st critical bl%cs in terms

%& a/erage current dissipati%n since it %perates e6tensi/el1 &%r b%th recei/ing and

transmitting" he best published integrated s1nthesizers ar%und ?Hz suitable &%r

+ireless LAN recei/ers c%nsume up t% !mWin b%th 54;S and bip%lar realizati%ns"

;ther s1nthesizers embedded in 8!"##a'c%mpliant transcei/ers can c%nsume up t% !mW"

>


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3ISA3:ANA?ES ;- ECISIN? 4EH;3D

his high p%+er c%nsumpti%n is mainl1 due t% the &irst stages %& the &re0uenc1

di/ider that %&ten dissipates hal& %& the t%tal p%+er" 3ue t% the high input

&re0uenc1, the &irst stage %& the di/ider cann%t be implemented in c%n/enti%nal

static 54;S l%gic"

Instead, it is c%mm%nl1 realized in S%urce'5%upled L%gic (S5L), +hich all%+s

higher %perating &re0uenc1, but burns m%re p%+er"

A3:ANA?ES ;- 2R;2;SE3 4EH;3D

31namic latches are n%+n t% be &aster and m%re c%mpact than static %nes" he

rue'Single'2hase'5l%c (S25) design all%+s t% dri/e the d1namic latch +ith

a single cl%c phase, thus a/%iding the se+ pr%blem"

he use %& d1namic l%gic is n%t %nl1 p%ssible up t% 7 ?Hz, but als% e6tremel1

e&&ecti/e in reducing the s1nthesizer p%+er dissipati%n"

2.2 De%(" +"* O6&(m(z+&(" f &'e E7&e"*e* Tr!e S(",e-P'+%e C,#8-9+%e*

Pre%#+,er -:(+ Pe" Y! ;+"' A"' D We( ;e" L(m

DESCRIPTION he p%+er c%nsumpti%n and %perating &re0uenc1 %& the E6tended

rue Single'2hase 5l%c (E'S25)'based &re0uenc1 di/ider is in/estigated" he sh%rt'

circuit p%+er and the s+itching p%+er in the E'S25'based di/ider are calculated and

simulated" A l%+'p%+er di/ide'b1'!$> unit %& a prescaler is pr%p%sed and implemented

using a 54;S techn%l%g1" 5%mpared +ith the e6isting design, a ! reducti%n %& p%+er

c%nsumpti%n is achie/ed" A di/ide'b1'8$9 dual'm%dulus prescaler implemented +ith this

di/ide'b1'!$> unit using a "#8'mum 54;S pr%cess is capable %& %perating up t% * ?Hz

+ith l%+'p%+er c%nsumpti%n" he prescaler is implemented in l%+'p%+er high'

res%luti%n &re0uenc1 di/iders &%r +ireless l%cal area net+%r applicati%ns" he design and

%ptimizati%n %& a high'speed E'S25'based prescaler has been carried %ut b1

in/estigati%n %& the %perating &re0uenc1 and p%+er c%nsumpti%n %& the E'S25 circuit" A

ne+ di/ide'b1'!$> unit +ith l%+ p%+er c%nsumpti%n has been pr%p%sed" It is suitable &%r

*


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the high'speed 54;S prescaler design" A di/ide'b1'8$9 dual'm%dulus prescaler

implemented +ith the pr%p%sed unit has been implemented t% achie/e the ultra'l%+'

p%+er c%nsumpti%n" he dual'm%dulus %perati%n ab%/e * ?Hz in the S25'based

prescaler has &irst been achie/ed" he prescaler has been implemented in high'res%luti%n

&re0uenc1 di/iders" It is suitable &%r the +ireless c%mmunicati%n s1stem bel%+ * ?Hz"

he %perati%n %& this pr%p%sed prescaler and &re0uenc1 di/ider ha/e als% been silic%n

/eri&ied" he high'speed &re0uenc1 di/ider is a e1 bl%c in &re0uenc1 s1nthesis" he

prescaler is the m%st challenging part in the high'speed &re0uenc1'di/ider design because

it %perates at the highest input &re0uenc1" A dual'm%dulus prescaler usuall1 c%nsists %& a

di/ide'b1'!$> (%r *$) unit &%ll%+ed b1 se/eral as1nchr%n%us di/ide'b1'! units" he

%perati%n %& the di/ide'b1'!$> unit at the highest input &re0uenc1 maes it the b%ttlenec

%& the prescaler design"


he E6tended rue Single'2hase 5l%c (E'S25) l%gic is pr%p%sed t% increase

the %perating &re0uenc1" H%+e/er, this causes additi%nal p%+er c%nsumpti%n"

In m%dern +ireless c%mmunicati%n s1stems, the p%+er c%nsumpti%n is a e1

c%nsiderati%n &%r the l%nger batter1 li&e" he 4;S 5urrent 4%de L%gic

(454L) circuit, +hich is %& high p%+er c%nsumpti%n, is c%mm%nl1 used t%

achie/e the high %perating &re0uenc1, +hile a rue Single'2hase 5l%c (S25)

d1namic circuit, +hich %nl1 c%nsumes p%+er during s+itching, has a l%+er

%perating &re0uenc1"


In this paper, the p%+er c%nsumpti%n and %perating &re0uenc1 in the E'S25

l%gic st1le is e/aluated" he t+% ma.%r s%urces %& p%+er c%nsumpti%n, namel1,

the sh%rt'circuit p%+er and the s+itching p%+er, in the E'S25 di/ide' b1'! unit

is calculated and simulated"

Based %n the anal1sis, a ne+ di/ide'b1'!$> unit is pr%p%sed t% achie/e the l%+

p%+er c%nsumpti%n b1 reducing the s+itching acti/ities and the sh%rt'circuit

current in the 3--s %& the unit, and a dual'm%dulus prescaler implemented +ith

the unit is pr%p%sed"


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2.3 A D$"+m(#-L(# Fre!e"#$ D(/(*er fr 5-GHz WLAN Fre!e"#$ S$"&'e%(zer-

Y!e-F+"

Re6!,(# f C'("+.

DESCRIPTION A d1namic'l%gic &re0uenc1 di/ider &%r &ull1 integrated 54;S

&re0uenc1 s1nthesizer is presented in this paper" he di/ider based %n the dual'm%dulus

prescaler and d1namic l%gic circuit is designed t% reduce the p%+er c%nsumpti%n,

transist%r'c%unts, and chip area" he simulati%n results sh%+ the pr%p%sed circuit

achie/ed the %perating &re0uenc1 band &r%m "#?Hz t% "8!?Hz &%r +ireless l%cal

area net+%r applicati%ns" A simple architecture %& the d1namic'l%gic &re0uenc1 di/ider

has been dem%nstrated in a standard "#8@m 54;S techn%l%g1" he &re0uenc1 di/ider is

designed +ith%ut c%unters and the simulati%n results sh%+ the ad/antages in l%+ p%+er

c%nsumpti%n and less chip area" he pr%p%sed &re0uenc1 di/ider achie/es the %perating

&re0uenc1 bands &%rm "#?Hz and "8!?Hz in steps %& !4Hz, +hich c%/ers #

channels in WLAN applicati%ns" IEEE 8!"##a and HiperLAN are standards %& +ireless

data net+%rs +ith &re0uenc1 band %perated &r%m t% 7?Hz +hich c%/ers &i&teen

channels +ith a channel spacing %& !4Hz" he &re0uenc1 s1nthesizers are +idel1 used

t% generate L%cal ;scillati%n (L;) signals in m%dern c%mmunicati%n s1stems" In %rder t%

c%/er the re0uired carries and %perate &r%m input &re0uenc1 %& ?Hz, the di/isi%n %& the

di/ider has t% be pr%grammed &r%m ! t% !9*" he %perating &re0uenc1 %& a &re0uenc1

s1nthesizer is limited b1 the &re0uenc1 di/ider as +ell as the :%ltage 5%ntr%lled

;scillat%r (:5;)"

3ISA3:ANA?ES IN ECISIN? 4EH;3D

-%r WLAN standard, m%st c%mm%n high'speed &re0uenc1 are based %n pulse'

s+all%+ architecture" he architectures re0uire t+% additi%nal c%unters &%r

generati%n %& a desired di/isi%n rati%" It %ccupies man1 gate'c%unts, large chip

area, and c%nsumes e6tra p%+er" he high p%+er c%nsumpti%n is mainl1 due t% the &irst stages %& the &re0uenc1

di/ider that %&ten c%nsumes hal& %& the t%tal p%+er" he &irst stage %& the di/ider

cann%t be implemented in d1namic S25 circuit

7


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his paper pr%p%ses a ne+ &re0uenc1 di/ider eeping the same &uncti%n as a

c%n/enti%nal %ne +ith%ut empl%1ing a sall%+er c%unter t% c%nsume taes e6tra

p%+er and unnecessar1 chip area"

he pr%p%sed t%p%l%g1 is based %n the c%unter'less and dual'm%dulus c%unter

detect%r"

2.4 De%(" f + ,) 6)er )(*e+"* '(' re%,!&(" 6rr+mm+,e fre!e"#$

*(/(*er- :. P. Y! e& +,. - Se6. -25

DESCRIPTIONhe design %& a high'speed +ide'band high res%luti%n pr%grammable

&re0uenc1 di/ider is in/estigated" A ne+ rel%adable 3 &lip'&l%p &%r the high speed

pr%grammable &re0uenc1 di/ider is pr%p%sed" It is %ptimized in terms %& pr%pagati%ndela1 and p%+er c%nsumpti%n as c%mpared +ith the e6isting designs" 4easurement

results sh%+ that an all'stage pr%grammable c%unter implemented +ith this 3 &lip'&l%p

using the 5hartered "#8 m 54;S pr%cess is capable %& %perating up t% #"8 ?Hz &%r a

#"8 : suppl1 /%ltage and "8'mW p%+er c%nsumpti%n" B1 using this c%unter, an ultra'

+ide range high res%luti%n &re0uenc1 di/ider is achie/ed +ith l%+ p%+er c%nsumpti%n

&%r 7'?Hz +ireless LAN applicati%ns" he design di&&iculties %& the +ide'band high

res%luti%n pr%grammable &re0uenc1 di/ider &%r multi'standard applicati%n are

in/estigated" A high speed l%+ p%+er c%unter is success&ull1 implemented &%r multi'

standard %perati%ns" 4easurements results sh%+ the &irst ?Hz all'stage pr%grammable

di/ider +ith l%+ p%+er c%nsumpti%n is achie/able +ith the pr%p%sed bit cell"

3RAWBA5FS ;- ECISIN? 4EH;3D

he &re0uenc1 s1nthesizer is %ne %& the basic building bl%cs in m%dern

c%mmunicati%n s1stems" he %perating &re0uenc1 %& the &re0uenc1 s1nthesizer is

limited b1 the &re0uenc1 di/ider and the /%ltage'c%ntr%lled %scillat%r" he&uncti%n %& channel selecti%n in the &re0uenc1 s1nthesizer demands pr%grammable

di/isi%n rati%s &%r the &re0uenc1 di/ider"

4uch research has been &%cused %n the prescaler design &%r its highest %perating

&re0uenc1" H%+e/er, in the m%dern c%mmunicati%n s1stem, there is an increasing

demand &%r multi'standards applicati%ns"


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A ne+ +ide'band high res%luti%n pr%grammable &re0uenc1 di/ider is pr%p%sed"

he +ide band and high res%luti%n are %btained b1 using the all'stage

pr%grammable t%p%l%g1 in b%th c%unters"

2.5 4.2 mW fre!e"#$ %$"&'e%(zer fr 2.4 GHz ?(ee +66,(#+&(" )(&' f+%& %e&&,("

T(me 6erfrm+"#e- S. S'(" e& +,.0- =!". 2> .

3ES5RI2I;ND A ne+ &re0uenc1 s1nthesizer +ith l%+'p%+er and sh%rt settling time is

intr%duced" With t+%'p%int channel c%ntr%ls &%r an integer'N 2LL, +e ha/e achie/ed a

near zer% settling time &%r an1 &re0uenc1 change in !"*?Hz Gigbee band" B1 utilizing a

/ertical'N2N parasitic transist%r &%r the :5; biasing, the cl%se'in phase n%ise has been

impr%/ed b1 dB &r%m the case %& 4;S biasing" A m%di&ied'S25 t%p%l%g1 is pr%p%sed

&%r l%+'/%ltage &re0uenc1 di/ider circuits" sing the #"!: suppl1 /%ltage &%r "#8mum

54;S, the p%+er c%nsumpti%n is %nl1 *"!4+" Ne+ &re0uenc1 s1nthesizer architecture

+ith /er1 l%+ p%+er and sh%rt &re0uenc1 settling time +as intr%duced" A t+%'p%int

channel c%ntr%l scheme +as used &%r %ur pr%p%sed &re0uenc1 s1nthesizer in +hich a

3A5 +ith tunable gain and a linearized :5; are used t% e&&ecti/el1 c%mpensate the gain

mismatch bet+een the t+% c%ntr%l paths" 3espite the use %& an integer'N architecture

+ith narr%+ !Hz band+idth, +e ha/e achie/ed near zer% &re0uenc1 settling time+ithin the accurac1 %& the measurement e0uipment &%r the 4Hz &re0uenc1 .umping

&r%m !"*?Hz"he batter1 li&e &%r m%bile applicati%ns is in/ersel1 pr%p%rti%nal t% the

energ1 c%nsumpti%n %& m%bile de/ices" hus it is imp%rtant t% minimize the energ1

c%nsumpti%n b1 minimizing b%th the acti/e dut1'c1cle and the acti/e p%+er c%nsumpti%n

%& a +ireless terminal c%ncurrentl1"


he &re0uenc1 settling time %& a 2LL decreases as the l%%p'band+idth increases"

H%+e/er, it re0uires a high &re0uenc1 &racti%nal c%ntr%ller thus increases the

hard+are c%mple6it1 and acti/e p%+er c%nsumpti%n"

8


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In this paper, a ne+ &re0uenc1 s1nthesizer +ith /er1 sh%rt &re0uenc1 settling time

and l%+ acti/e p%+er c%nsumpti%n is intr%duced"

-%r sh%rt &re0uenc1 settling time, a t+%'p%int channel c%ntr%l scheme c%mp%sed

%& a direct':5; c%ntr%l (c%mpensati%n'path) and a di/ider c%ntr%l (main'path) is

used"

CHAPTER 3

E:ISTING SYSTE;

3.1 9LOC< DIAGRA;

9


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-igure">"# E6isting 31namic l%gic multiband &le6ible di/ider

#" Wideband !$> prescaler!" 4ultim%dulus >!$>>$*$*8 prescaler

>" S+all%+ 2'c%unter

*" S+all%+ S'c%unter

3.1.1 ;ODULE DESCRIPTION

3.1.1.1 WIDE9AND 2@3 PRESCALER

he E'S25 !$> prescaler rep%rted in c%nsumes large sh%rt'circuit p%+er and has

a higher &re0uenc1 %& %perati%n than that %& !$> prescaler" he +ideband single'phase

cl%c !$> prescaler used in this design c%nsists %& t+% 3'&lip'&l%ps and t+% N;R gates

embedded in the &lip'&l%ps as in -ig" >"!" he &irst N;R gate is embedded in the last stage

%& 3--#, and the sec%nd N;R gate is embedded in the &irst stage %& 3--!" Here, the

transist%rs 4!, 4!, 4*, and 48 in 3--# helps t% eliminate the sh%rt'circuit p%+er

during the di/ide'b1'! %perati%n" he s+itching %& di/isi%n rati%s bet+een ! and > isc%ntr%lled b1 l%gic signal 45"

#


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-ig">"! Wideband Single'2hase 5l%c !$> 2rescaler

When 45 s+itches &r%m J t% #J transist%rs 4!, 4* and 48 in 3--# turns %&&

and the n%des S#, S! and S> s+itch t% l%gic "J Since n%de S> is J and the %ther input

t% the N;R gate embedded in 3--! is Kb, the +ideband prescaler %perates at the di/ide'

b1'! m%de" 3uring this m%de, n%des S#, S! and S> s+itch t% l%gic J and remain at J

&%r the entire di/ide'b1'! %perati%n, thus rem%/ing the s+itching p%+er c%ntributi%n %&

3--#" Since %ne %& the transist%rs is al+a1s ;-- in each stage %& 3--#, the sh%rt'circuit

p%+er in 3--# and the &irst stage %& 3--! is negligible" he t%tal p%+er c%nsumpti%n %&

the prescaler in the di/ide'b1'! m%de is e0ual t% the s+itching p%+er in 3--! and the

sh%rt'circuit p%+er in sec%nd and third stages %& 3--!"

2+ideband'di/ide'b1'!= i=1

n

fclkCLiVdd 2


12/53

in 3--# is J and the +ideband prescaler %perates at the di/ide'b1'> m%de" 3uring the

di/ide'b1'! %perati%n, %nl1 3--! acti/el1 participates in the %perati%n and c%ntributes t%

the t%tal p%+er c%nsumpti%n since all the s+itching acti/ities are bl%ced in 3--#" hus,

the +ideband !$> prescaler has bene&it %& sa/ing m%re than %& p%+er during the

di/ide'b1'! %perati%n"

3.1.1.2 ;ULTI;ODULUS 32@33@4@4B PRESCALER

he pr%p%sed +ideband multim%dulus prescaler +hich can di/ide the input

&re0uenc1 b1 >!, >>, *, and *8 is sh%+n in -ig >">" It is similar t% the >!$>> prescaler

used in, but +ith an additi%nal in/erter and a multiple6er" he pr%p%sed prescaler

per&%rms additi%nal di/isi%ns (di/ide' b1'* and di/ide'b1'*8) +ith%ut an1 e6tra &lip'

&l%p, thus sa/ing a c%nsiderable am%unt %& p%+er and als% reducing the c%mple6it1 %&

multiband di/ider" he multim%dulus prescaler c%nsists %& the +ideband !$> (N#$

(N 4ultim%dulus >!$>>$*$*8 2rescaler

C+%e 1 Se,

#!


13/53

When Sel= , the %utput &r%m the NAN3! gate is directl1 trans&erred t% the input

%& !$> prescaler and the multim%dulus prescaler %perates as the n%rmal >!$>> prescaler,

+here the di/isi%n rati% is c%ntr%lled b1 the l%gic signal 4;3" I& 45=#, the !$>

prescaler %perates in the di/ide'b1'! m%de and +hen 45=, the !$> prescaler %perates in

the di/ide'b1'> m%de"

I& 4;3 =#, the NAN3! gate %utput s+itches t% l%gic #J (45=#)and the +ideband

prescaler %perates in the di/ide' b1'! m%de &%r entire %perati%n" he di/isi%n rati% N

per&%rmed b1 the multim%dulus prescaler is

N = (A3N#) < ((N#! MMMMMMMMM *

Where N=! and A3=#7 is &i6ed &%r the entire design" I& 4;3= , &%r > input

cl%c c1cles 45 remains at l%gic #J, +here +ideband prescaler %perates in di/ide'b1'!

m%de and, &%r three input cl%c c1cles, 45 remains at l%gic J +here the +ideband

prescaler %perates in the di/ide'b1'> m%de" he di/isi%n rati% N MMMMMMMMMM

C+%e 2 Se, 1

When Sel = #, the in/erted %utput %& the NAN3! gate is directl1 trans&erred t% the

input %& !$> prescaler and the multim%dulus prescaler %perates as a *$*8 prescaler,

+here the di/isi%n rati% is c%ntr%lled b1 the l%gic signal 4;3" I& 45 = #, the !$>

prescaler %perates in di/ide'b1'> m%de and +hen 45=, the !$> prescaler %perates in

di/ide'b1'! m%de +hich is 0uite %pp%site t% the %perati%n per&%rmed +hen Sel="

I& 4;3 = #, the di/isi%n rati% N m%de &%r the entire

%perati%n

?i/en b1

N < # = ((A3 (N#


14/53

N = ((A3 ' #) (N#"*"Bl%c 3iagram %& a 'Bit 2r%gram 5%unter

he ripple c%unter is implemented using cascaded 3't1pe &lip'&l%ps, each

arranged in a t%ggle c%n&igurati%n" he %utput %& each &lip'&l%p is used t% cl%c the ne6t

&lip'&l%p" Since the %utput %& each &lip'&l%p in/erts %n e/er1 cl%c c1cle, each &lip'&l%p

#*


15/53

essentiall1 di/ides its cl%c b1 t+%, causing the ne6t stage %& the ripple c%unter t% be

cl%ced at hal& the rate %& the pre/i%us &lip &l%p" Each &lip'&l%p +as designed t% resp%nd

t% the &alling edge %& its cl%c, +hen the %utput %& the pre/i%us stage changes &r%m a # t%

a " In this +a1, an incrementing binar1 c%unt is achie/ed +ith the %utputs %& each &lip'

&l%p &%rming the bits %& the c%unt" Since the pr%gram c%unter c%ntains 'bits, an1 c%unt

bet+een and #! can be set b1 the c%ntr%l signal" It is imp%rtant t% realize h%+e/er that

in %rder t% achie/e a di/isi%n rati% as speci&ied in the e0uati%n DIV=NP+S, the c%ntr%l

signal must be set t%P-1, since the zer%'state is included in the c%unt"

P-C!"&er Im6,eme"&+&("

It is p%ssible t% see the three ma.%r c%mp%nents %& the pr%gram c%unter

implemented using 454L l%gic gates" At the input %& the c%unter, an arra1 %& &lip'&l%ps

is used as the ripple c%unter" he %utputs %& the ripple c%unter, taen &r%m the %utputs %&

each %& the &lip'&l%ps, are &ed int% an arra1 %& CN;R gates" he CN;R gates c%mpare

each bit +ith the c%rresp%nding bit in the c%ntr%l signal, %utputting a l%gical #O +hen the

bits are e0ual" Alth%ugh this l%gic is in/erted c%mpared t% the descripti%n %& the

c%mparat%r in the pre/i%us secti%n, the zer%'detect%r is implemented as a %ne'detect%r

using a tree %& cascaded AN3 gates" In this +a1, the %/erall l%gic %& the circuit is

unchanged, and the %utput pulse can be generated +ith%ut an1 additi%nal l%gic"

An%ther di&&erence seen is a separate %utput, S)+,,) RST, and s%me simple

circuitr1 used t% generate it" S)+,,) RST is used internall1 t% reset the &lip'&l%ps %& the

pr%gram c%unter, and e6ternall1 t% reset the &lip'&l%ps %& the s+all%+ c%unter" Since the

&an'%ut %& the reset signal is high ( &lip'&l%ps in the 25, and 7 in the S5), the reset signal

is br%en int% t+% paths and dri/en using separate 454L bu&&ers" In earl1 simulati%ns,

these bu&&ers +ere absent and the reset signal c%uld n%t pr%/ide en%ugh current t% dri/e

the input capacitance ass%ciated +ith the &lip'&l%ps" S)+,,) RST +as generated using

an appr%ach that guarantees predictable timing %& the reset signal" F!& is tappedJ and

&ed t% the input %& a &lip'&l%p cl%ced b1 F("" ;n the cl%c c1cle immediatel1 &%ll%+ing

F!& g%ing high, the pulse is sampled b1 the &lip'&l%p, generating S)+,,) RST and

resetting b%th the pr%gram c%unter and the s+all%+ c%unter" % ensure that the reset

#


16/53

signal is rem%/ed be&%re the ne6t cl%c c1cle, the reset signal is &ed bac t% its generating

&lip'&l%p thr%ugh a dela1 chain c%mprised %& three bu&&ers"

3.1.1.4 SWALLOW COUNTER

he s+all%+ c%unter, as indicated in -igure >", is used t% c%unt Spulses %& Sl%+

5LF be&%re asserting the m%dulus c%ntr%lsignal and changing the m%dulus %& the 342

t%N" he similarities bet+een the s+all%+ c%unter and the pr%gram c%unter are apparent"

;nce again, the c%unt (7'bits in this case) is maintained using a ripple c%unter c%mprised

%& cascaded &lip'&l%ps cl%ced +ith Sl%+5LF" In additi%n, a c%mparat%r c%mpares each

c%unt bit +ith its c%rresp%nding bit in the c%ntr%l signal, and a zer%'detect%r asserts

m%dulus c%ntr%l +hen all bits are e0ual" H%+e/er, the s+all%+ c%unter d%es n%t reset

+hen the c%unt is reached, but mass the input cl%c using an AN3 gate c%nnected t% the

in/erse %& m%dulus c%ntr%l" As a result, the ripple c%unter st%ps c%unting +hen the c%unt

is reached, and the state %& the circuit is maintained until a reset signal (S+all%+RS) is

recei/ed &r%m the pr%gram c%unter" Since the s+all%+ c%unter c%ntains 7 bits, it is

capable %& an1 c%unt &r%m t% 7*" ;nce again, the c%ntr%l signal must be set t% S-1, since

the zer%'state is included in the c%unt"

-ig">" Bl%c 3iagram %& a 7'Bit S+all%+ 5%unter

#7


17/53

he 7'bit ripple c%unter implemented as an arra1 %& &lip'&l%ps, and cl%ced +ith

the gated cl%c pr%/ided b1 the AN3 %& Sl%+ 5LF and m%dulus c%ntr%l" In additi%n, the

c%mparat%r is implemented as an arra1 %& 454L CN;R gates, +hile the zer%'detect%r is

actuall1 implemented as a %ne'detect%r using a tree %& cascaded AN3 gates" nlie the

pr%gram c%unter h%+e/er, n% additi%nal circuitr1 is necessar1 t% generate the reset as the

reset is recei/ed &r%m the pr%gram c%unter b1 means %& the S+all%+ RS signal"

#


18/53

CHAPTER 4

POWER OPTI;ISATION OF SINGLE-PHASE CLOC


19/53

digital circuits is determined b1 the s+itching and sh%rt circuit p%+er" he s+itching

p%+er is linearl1 pr%p%rti%nal t% the %perating &re0uenc1 and is gi/en b1 the sum %&

s+itching p%+er at each %utput n%de as in

2 s+itching= i=1

n

fclkCLiVdd 2 MMMMMM !

+here n is the number %& s+itching n%des, -cl is the cl%c &re0uenc1, 5Li is the

l%ad capacitance at the %utput n%de %& the ith stage, and :dd is the suppl1 /%ltage"

N%rmall1, the sh%rt'circuit p%+er %ccurs in d1namic circuits +hen there e6ists direct

paths &r%m the suppl1 t% gr%und +hich is gi/en b1

P sc = I sc V dd MMMMMM >

+here Isc is the sh%rt'circuit current" he anal1sis sh%+s that the sh%rt'circuit

p%+er is much higher in E'S25 l%gic circuits than n S25 l%gic circuits" H%+e/er,

S25 l%gic circuits e6hibit higher s+itching p%+er c%mpared t% that %& E'S25 l%gic

circuits due t% high l%ad capacitance" -%r the E'S25 l%gic circuit, the sh%rt'circuit

p%+er is the ma.%r pr%blem" he E'S25 circuit has the merit %& higher %perating

&re0uenc1 than that %& the S25 circuit due t% the reducti%n in l%ad capacitance, but it

c%nsumes signi&icantl1 m%re p%+er than the S25 circuit d%es &%r a gi/en transist%r size"

he &%ll%+ing anal1sis s based %n the latest design using the p%pular and l%+'c%st "#8'

micr%m 54;S pr%cess"

4.2PROPOSED 4@5 PRESCALER

he *$ prescaler rep%rted in c%nsumes large sh%rt circuit p%+er and has a higher

&re0uenc1 %& %perati%n than that %& !$> prescaler" he +ideband single'phase cl%c *$

prescaler used in this design, +hich c%nsists %& three 3'&lip'&l%ps and t+% nand gatesembedded"

he 4ulti prescaler *b1 c%nsist %& -%ur 3'&lip &l%p, t+% Nand gates, and t+% ;R

gates %ne N%t gate +ith main *$ prescaler circuit" he multi m%dulus prescaler %perates

as the n%rmal 7*$7$9$8"

#9


20/53


21/53

4.4 PROPOSED ;ULTI9AND FLE:I9LE DIVIDER

-ig *"> 2r%p%sed 4ultiband -le6ible 3i/ider

;ur pr%p%sed multiband &le6ible di/ider is 5%mbined b1 !$> 2rescaler and *$2rescaler in multi m%dulus 2rescaler" B1 using 4u6 +e can %perate either !$> 2rescaler

and *$ 2rescaler" It +ill %perate >!$>>$*$*8 %r 7*$7$9$8 band+idth"

4.4.1 PROGRA; COUNTER

he pr%gram c%unter is resp%nsible &%r c%unting P pulses %& Sl%+ 5LF be&%re

%utputting a pulse t% the phase$&re0uenc1 detect%r and resetting itsel& and the s+all%+

c%unter" he implementati%n used in this pr%.ect, using a 'bit ripple c%unter, a 'bit

c%mparat%r, and a zer%'detect%r is sh%+n in -igure*"*" he ripple c%unter is cl%ced b1Sl%+5LF, and increments its c%unt b1 %ne each cl%c c1cle" At each stage, the 'bit

c%mparat%r c%mpares each c%unt bit t% the c%rresp%nding bit in the c%ntr%l signal, and

%utputs a &%r each e0ual bit" When the zer%'detect%r detects e0ui/alence in all %& the

bits, indicating that the desired c%unt has been reached, -%ut is dri/en high" ;n the ne6t

cl%c c1cle, the pr%gram c%unter is reset t% zer% and the c%unt is restarted" In additi%n,

!#


22/53

the %utput pulse %n -%utis used t% reset the c%unt %& the s+all%+ c%unter, indicating the

end %& %ne c%mplete c1cle %& the &re0uenc1 di/ider"

-ig"*"* Bl%c 3iagram %& a 'Bit 2r%gram 5%unter

he ripple c%unter is implemented using cascaded 3't1pe &lip'&l%ps, each

arranged in a t%ggle c%n&igurati%n" he %utput %& each &lip'&l%p is used t% cl%c the ne6t

&lip'&l%p" Since the %utput %& each &lip'&l%p in/erts %n e/er1 cl%c c1cle, each &lip'&l%p

essentiall1 di/ides its cl%c b1 t+%, causing the ne6t stage %& the ripple c%unter t% be

cl%ced at hal& the rate %& the pre/i%us &lip &l%p" Each &lip'&l%p +as designed t% resp%nd

t% the &alling edge %& its cl%c, +hen the %utput %& the pre/i%us stage changes &r%m a # t%

a " In this +a1, an incrementing binar1 c%unt is achie/ed +ith the %utputs %& each &lip'

&l%p &%rming the bits %& the c%unt" Since the pr%gram c%unter c%ntains 'bits, an1 c%unt

bet+een and #! can be set b1 the c%ntr%l signal" It is imp%rtant t% realize h%+e/er that

in %rder t% achie/e a di/isi%n rati% as speci&ied in the e0uati%n DIV=NP+S, the c%ntr%l

signal must be set t%P-1, since the zer%'state is included in the c%unt"

!!


23/53

P-C!"&er Im6,eme"&+&("

It is p%ssible t% see the three ma.%r c%mp%nents %& the pr%gram c%unter

implemented using 454L l%gic gates" At the input %& the c%unter, an arra1 %& &lip'&l%ps

is used as the ripple c%unter" he %utputs %& the ripple c%unter, taen &r%m the %utputs %&

each %& the &lip'&l%ps, are &ed int% an arra1 %& CN;R gates" he CN;R gates c%mpare

each bit +ith the c%rresp%nding bit in the c%ntr%l signal, %utputting a l%gical #O +hen the

bits are e0ual" Alth%ugh this l%gic is in/erted c%mpared t% the descripti%n %& the

c%mparat%r in the pre/i%us secti%n, the zer%'detect%r is implemented as a %ne'detect%r

using a tree %& cascaded AN3 gates" In this +a1, the %/erall l%gic %& the circuit is

unchanged, and the %utput pulse can be generated +ith%ut an1 additi%nal l%gic"

An%ther di&&erence seen is a separate %utput, S)+,,) RST, and s%me simple

circuitr1 used t% generate it" S)+,,) RST is used internall1 t% reset the &lip'&l%ps %& the

pr%gram c%unter, and e6ternall1 t% reset the &lip'&l%ps %& the s+all%+ c%unter" Since the

&an'%ut %& the reset signal is high ( &lip'&l%ps in the 25, and 7 in the S5), the reset signal

is br%en int% t+% paths and dri/en using separate 454L bu&&ers" In earl1 simulati%ns,

these bu&&ers +ere absent and the reset signal c%uld n%t pr%/ide en%ugh current t% dri/e

the input capacitance ass%ciated +ith the &lip'&l%ps" S)+,,) RST +as generated using

an appr%ach that guarantees predictable timing %& the reset signal" F!& is tappedJ and

&ed t% the input %& a &lip'&l%p cl%ced b1 F("" ;n the cl%c c1cle immediatel1 &%ll%+ing

F!& g%ing high, the pulse is sampled b1 the &lip'&l%p, generating S)+,,) RST and

resetting b%th the pr%gram c%unter and the s+all%+ c%unter" % ensure that the reset

signal is rem%/ed be&%re the ne6t cl%c c1cle, the reset signal is &ed bac t% its generating

&lip'&l%p thr%ugh a dela1 chain c%mprised %& three bu&&ers"

!>


24/53

4.4.2 SWALLOW COUNTER

he s+all%+ c%unter, as indicated in -igure *", is used t% c%unt Spulses %& Sl%+

5LF be&%re asserting the m%dulus c%ntr%lsignal and changing the m%dulus %& the 342

t%N" he similarities bet+een the s+all%+ c%unter and the pr%gram c%unter are apparent"

;nce again, the c%unt (7'bits in this case) is maintained using a ripple c%unter c%mprised

%& cascaded &lip'&l%ps cl%ced +ith Sl%+5LF" In additi%n, a c%mparat%r c%mpares each

c%unt bit +ith its c%rresp%nding bit in the c%ntr%l signal, and a zer%'detect%r asserts

m%dulus c%ntr%l +hen all bits are e0ual" H%+e/er, the s+all%+ c%unter d%es n%t reset

+hen the c%unt is reached, but mass the input cl%c using an AN3 gate c%nnected t% the

in/erse %& m%dulus c%ntr%l" As a result, the ripple c%unter st%ps c%unting +hen the c%unt

is reached, and the state %& the circuit is maintained until a reset signal (S+all%+RS) is

recei/ed &r%m the pr%gram c%unter" Since the s+all%+ c%unter c%ntains 7 bits, it is

capable %& an1 c%unt &r%m t% 7*" ;nce again, the c%ntr%l signal must be set t% S-1, since

the zer%'state is included in the c%unt"

-ig*"" Bl%c 3iagram %& a 7'Bit S+all%+ 5%unter

!*


25/53

S-C!"&er Im6,eme"&+&("

he 7'bit ripple c%unter implemented as an arra1 %& &lip'&l%ps, and cl%ced +ith

the gated cl%c pr%/ided b1 the AN3 %& Sl%+ 5LF and m%dulus c%ntr%l" In additi%n, the

c%mparat%r is implemented as an arra1 %& 454L CN;R gates, +hile the zer%'detect%r is

actuall1 implemented as a %ne'detect%r using a tree %& cascaded AN3 gates" nlie the

pr%gram c%unter h%+e/er, n% additi%nal circuitr1 is necessar1 t% generate the reset as the

reset is recei/ed &r%m the pr%gram c%unter b1 means %& the S+all%+ RS signal"

4.4.3 CO;PARISON 9ETWEEN ;ULTI;ODULUS 2@3 AND 4@5 PRESCALER

5ase(#

)

SEL=

4;3=

#

N=(A3N#)!

7*

-3=N2


26/53

CHAPTER 5

E:PERI;ENTAL RESULTS

5.1 SI;ULATION RESULTS

5.1.1. D FLIP FLOP

-ig "#"#"Simulati%n Result %& 3 -lip -l%p

5.1.2. ;U:

-ig "#"!"Simulati%n Result %& 4u6

!7


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5.1.3. CO;PARATOR S

-ig "#"> Simulati%n Result %& 5%mparat%r S

5.1.4. CO;PARATOR P

-ig "#"* Simulati%n Result %& 5%mparat%r 2

!


28/53

5.1.5. PROPOSED ;ULTI9AND FREUENCY DIVIDER

-ig "#""Simulati%n result %& 2r%p%sed multiband &re0uenc1 di/ider

5.2 SYNTHESIS RESULTSD

5.2.1 RTL DIAGRA; OF ;ULTI;ODULUS PRESCALER

!8


29/53

-ig""!"# RL diagram %& multim%dulus prescaler

5.2.2 RTL DIAGRA; OF PROPOSED DYNA;IC LOGIC FLE:I9LE DIVIDER

!9


30/53

-ig "!"! RL diagram %& pr%p%sed d1namic l%gic &le6ible di/ider

5.2.3 RTL DIAGRA; OF TOP ;ODULE

-ig "!"> RL diagram %& t%p m%dule

5.2.4 P)er A"+,$%(%

>


31/53

-igure "!"* Result &%r p%+er anal1sis

5.3 CO;PARISON OF RESULTS

>#


32/53

5.3.1 PERFOR;ANCE OF DIFFERENT DIVIDERS

3esign 2arameters E6isting S1stem 2r%p%sed S1stem

2r%cess(um) "#8 "#8Suppl1 :%ltage(/) #"8 #"8

4a6"-re0uenc1(?Hz) "#*'" !"*'!"*8*$'"8!

2%+er(mW)

3i/ide m%de

"!! "##

Res%luti%n ! #,!,,#,!

able (!)" 2er&%rmance %& di&&erent di/iders

CHAPTER >

ADVANTAGES0 DISADVANTAGES AND APPLICATIONS

ADVANTAGES

>!


33/53

he main ad/antages %& the pr%p%sed meth%d can be summarized asD

31namic latches are n%+n t% be &aster and m%re c%mpact than static %nes"

he e6tended true'single'phase'cl%c (E'S25) design all%+s t% dri/e the

d1namic latch +ith a single cl%c phase, thus a/%iding the se+ pr%blem"

DISADVANTAGES

High p%+er c%nsumpti%n is mainl1 due t% the &irst stages %& the &re0uenc1 di/ider

that %&ten dissipates hal& %& the t%tal p%+er" E'S25 ha/ing high %perating &re0uenc1, +hile a true single'phase cl%c (S25)

d1namic circuit, +hich %nl1 c%nsumes p%+er during s+itching, has a l%+er

%perating &re0uenc1

APPLICATIONS

In real time applicati%ns are satellite transmitter and recei/er"

Radi% transmitter, L%cal c%mmunicati%n transmitter (4%bile)"

CHAPTER

CONCLUSION AND FUTURE WOR>


34/53

ma6imum %perating &re0uenc1 %& ! ?Hz, the /alues %& 2 and S'c%unters can actuall1

be pr%grammed t% di/ide range %& &re0uencies +ith &inest res%luti%n %& # 4Hz and

/ariable channel spacing" H%+e/er, since interest lies in the !'!"* and "8!'?Hz

bands %& %perati%n, the 2' and S'c%unters are pr%grammed acc%rdingl1" he pr%p%sed

multiband &le6ible di/ider als% uses an impr%/ed l%adable bit'cell &%r S+all%+ S'c%unter

and c%nsumes a p%+er %& "##mW, and pr%/ides a s%luti%n t% the l%+ p%+er 2LL

s1nthesizers &%r Bluet%%th, Gigbee, IEEE 8!"#"*, and IEEE 8!"##a$b$g WLAN

applicati%ns +ith /ariable channel spacing"

FUTURE WOR*


35/53

ANNE:URE-A

>


36/53

SOFTWARE REUIRE;ENT

:ILIN:

:(,("7, Inc" (NAS3AKD CLNC) is the +%rlds largest supplier %& pr%grammable

l%gic de/ices, the in/ent%r %& the &ield pr%grammable gate arra1 (-2?A) and the &irst

semic%nduct%r c%mpan1 +ith a &abless manu&acturing m%del"

In the Cilin6 s%&t+are +e can d% simulati%n and s1nthesis "he entire pr%cess%r +ill be

implemented using the Cilin6 -2?As s% 1%u +%nt ha/e t% spend time +iring up that part

%& the circuit" Q%u +ill, h%+e/er, ha/e t% +ire the s+itches and lights that are used t%

c%ntr%l the pr%cess%r, and ha/e t% +ire the Cilin6 part itsel& t% the s+itches and lights, butthis sh%uldnt be t%% bad" Q%u +ill als% use the bacplane bus in 1%ur lab it s% that the

riscuit +ill be built %n t+% b%ardsD %ne &%r the Cilin6 chip, and %ne &%r the s+itches and

lights"

he H3L Edit%r &eature pr%/ides e6tensi/e edit and search capabilities +ith language'

speci&ic c%l%r c%ding %& e1+%rds, as +ell as integrated %n'line s1nta6 checing t% scan

:H3L c%de &%r err%rs" he Language Assistant &eature speeds design entr1 b1 pr%/iding

a l%%up list %& t1pical language c%nstructs and c%mm%nl1 used s1nthesis m%dules lie

c%unters, accumulat%rs, and adders"

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VHDL

VHDL VHSI5Hard+areDescripti%nLanguage' IEEE standardized Language

9ASIC CO;PONENTS OFA VHDL ;ODEL

he purp%se %& :H3L descripti%ns is t% pr%/ide a m%del &%r digital circuits and s1stems"

his abstract /ie+ %& the real ph1sical circuit is re&erred t% as entit1" An entit1 n%rmall1

c%nsists %& &i/e basic elements, %r design units"

-ig D Basic 4%del %& :H3L

In :H3L %ne generall1 distinguishes bet+een the e6ternal /ie+ %& a m%dule and its

internal descripti%n" he e6ternal /ie+ is re&lected in the entit1 declarati%n, +hich

represents an inter&ace descripti%n %& a blac b%6" he imp%rtant part %& this inter&ace

descripti%n c%nsists %& signals %/er +hich the indi/idual m%dules c%mmunicate +ith each

%ther"

he internal /ie+ %& a m%dule and, there&%re, its &uncti%nalit1 is described in the

architecture b%d1" his can be achie/ed in /ari%us +a1s" ;ne p%ssibilit1 is gi/en b1

c%ding a beha/i%ral descripti%n +ith a set %& c%ncurrent %r se0uential statements" An%ther

p%ssibilit1 is a structural descripti%n, +hich ser/es as a base &%r the hierarchicall1

designed circuit architectures" Naturall1, these t+% inds %& architectures can als% be

c%mbined" he l%+est hierarch1 le/el, h%+e/er, must c%nsist %& beha/i%ral descripti%ns"

>


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;ne %& the ma.%r :H3L &eatures is the capabilit1 t% deal +ith multiple di&&erent

architectural b%dies bel%nging t% the same entit1 declarati%n" Being able t% in/estigate

di&&erent architectural alternati/es permits the de/el%pment %& s1stems t% be d%ne in an

e&&icient t%p'd%+n manner" he ease %& s+itching bet+een di&&erent architectures has

an%ther ad/antage, namel1, 0uic testing" In this case, it is necessar1 t% bind %ne

architecture t% the entit1 in %rder t% ha/e a uni0ue hierarch1 &%r simulati%n %r s1nthesis"

Which architecture sh%uld be used &%r simulati%n %r s1nthesis in c%n.uncti%n +ith a gi/en

entit1 is speci&ied in the c%n&igurati%n secti%n" I& the architecture b%d1 c%nsists %& a

structural descripti%n, then the binding %& architectures and entities %& the instantiated sub

m%dules, the s%'called c%mp%nents, can als% be &i6ed b1 the c%n&igurati%n statement"

he pacage is the last element menti%ned here" It c%ntains declarati%ns %& &re0uentl1

used data t1pes, c%mp%nents, &uncti%ns, and s% %n" he pacage c%nsists %& a pacage

declarati%n and a pacage b%d1" he declarati%n is used, lie the name implies, &%r

declaring the ab%/e'menti%ned %b.ects" his means, the1 bec%me /isible t% %ther design

units" In the pacage b%d1, the de&initi%n %& these %b.ects can be carried %ut, &%r e6ample,

the de&initi%n %& &uncti%ns %r the assignment %& a /alue t% a c%nstant" he partiti%ning %& a

pacage int% its declarati%n and b%d1 pr%/ides ad/antages in c%mpiling the m%del

descripti%ns"

W'$ VHDL

A design engineer in electr%nic industr1 uses hard+are descripti%n language t% eep pace

+ith the pr%ducti/it1 %& the c%mpetit%rs" With :H3L +e can 0uicl1 describe and

s1nthesize circuits %& se/eral th%usand gates" In additi%n :H3L pr%/ides the capabilities

described as &%ll%+sD

P)er +"* f,e7((,(&$

:H3L has p%+er&ul language c%nstructs +ith +hich t% +rite succinct c%de descripti%n %&

c%mple6 c%ntr%l l%gic" It als% has multiple le/els %& design descripti%n &%r c%ntr%lling

>8


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design implementati%n" It supp%rts design libraries and creati%n %& reusable c%mp%nents"

It pr%/ides 3esign hierarchies t% create m%dular designs" It is %ne language &%rt design

and simulati%n.

De/(#e I"*e6e"*e"& *e%("

:H3L permits t% create a design +ith%ut ha/ing t% &irst ch%%se a de/ice &%r

implementati%n" With %ne design descripti%n, +e can target man1 de/ice architectures"

With%ut being &amiliar +ith it, +e can %ptimize %ur design &%r res%urce %r per&%rmance"

It permits multiple st1le %& design descripti%n"

Pr&+(,(&$

:H3L p%rtabilit1 permits t% simulate the same design descripti%n that +e ha/e

s1nthesized" Simulating a large design descripti%n be&%re s1nthesizing can sa/e

c%nsiderable time" As :H3L is a standard, design descripti%n can be taen &r%m %ne

simulat%r t% an%ther, %ne s1nthesis t%%l t% an%therT %ne plat&%rm t% an%ther'means

descripti%n can be used in multiple pr%.ects"

9e"#'m+r8(" #+6+(,(&(e%

3e/iceindependent design and p%rtabilit1 all%+s benchmaring a design using

di&&erent de/ice architectures and di&&erent s1nthesis t%%l" We can tae a c%mplete design

descripti%n and s1nthesize it, create l%gic &%r it, e/aluate the results and &inall1 ch%%se the

de/ice'a 52L3 %r an -2?A that &its %ur re0uirements"

ASIC ;(r+&("

he e&&icienc1 that :H3L generates, all%+s %ur pr%duct t% hit the maret 0uicl1

i& it has been s1nthesized %n a 52L3 %r -2?A" When pr%ducti%n /alue reaches

appr%priate le/els, :H3L &acilitates the de/el%pment %& applicati%n speci&ic integrated

circuit (ASI5)" S%metimes, the e6act c%de used +ith the 2L3 can be used +ith the ASI5

and because :H3L is a +ell'de&ined language, +e can be assured that %ut ASI5 /end%r

+ill deli/er a de/ice +ith e6pected &uncti%nalit1"

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VHDL DESCRIPTION

In the search %& a standard design and d%cumentati%n &%r the :er1 High Speed Integrated

5ircuits (:HSI5) pr%gram, the nited States 3epartment %& 3e&ense (3;3) n

#98#sp%ns%red a +%rsh%p %n Hard+are 3escripti%n Languages (H3L) at W%%ds H%le,

4assachusetts" In #98>, the 3;3 established re0uirements &%r a standard :HSI5

Hard+are 3escripti%n Language :H3L, its en/ir%nment and its s%&t+are +as a+arded t%

IB4, e6as Instruments and Intermetrics c%rp%rati%ns"

:H3L !" +as released %nl1 a&ter the pr%.ect +as begun" he language +as signi&icantl1

impr%/ed c%rrecting the sh%rtc%ming %& the earlier /ersi%nsT :H3L 7" +as released in

#98*" :H3L #8$##7* &%rmall1 became the IEEE standard Hard+are 3escripti%n

Language in #98"

A :H3L design is de&ined as an ENTITY *e#,+r+&(" and as an ass%ciated

ARCHTECTURE *$" he declarati%n speci&ies its inter&ace and is used b1

architecture b%dies %& design entities at upper le/els %& hierarch1" he architecture b%d1

describes the %perati%n %& a design entit1 b1 speci&1ing its interc%nnecti%n +ith %ther

design entities STRUCTURAL *e%#r(6&("0 b1 its beha/i%r 9EHAVIORAL

*e%#r(6&(", %r b1 a mi6ture %& b%th" he :H3L language gr%ups, sub pr%grams %r

design entities b1 use %& pacages"

-%r cust%mizing generic descripti%ns %& design entities, CONFIGURATIONSare used"

:H3L als% supp%rts libraries and c%ntains c%nstructs &%r accessing pacages, design

entities %r c%n&igurati%ns &r%m /ari%us libraries"

ENTITIES +"* ARCHITECTURES

ENTITY De#,+r+&("

he ENTITYdeclarati%n declares the name, directi%n and data t1pe %& each p%rt %&

c%mp%nent"

S$"&+7 entit1 name is

*


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2%rt ( )T

End nameD

ARCHITECTURE De#,+r+&("

he ARCHITECTUREp%rti%n %& a :H3L descripti%n describes the beha/i%r %& the

c%mp%nent"

S$"&+7 architecture Uarchitecture name V %& Uentit1 nameV is

Begin

he 9EGINO that &%ll%+s the signal declarati%n mars the start %& the

architecture b%d1" he &%ll%+s a pr%cess declarati%n, mared b1 the e1+%rd PROCESS

and an ensuring 9EGIN"

he ENDstatement ending the architecture must be acc%mpanies b1 the name %& the

architecture +hich must match the name sh%+n in the &irst %& the architecture"

Se!e"&(+, Pr#e%%("

Se0uential statements are statements that e6ecute seriall1, %ne a&ter %ther" In architecture

&%r an entit1, all statement are c%ncurrent, in :H3L, the pr%cess statements can e6ist in

the architecture +here all statements are se0uential"

S$"&+7

pr%cess'labelDX pr%cess (sensiti/it1 list)X

2r%cess'declarati/e'partT

Begin

2r%cess'statement'partDD=

Se0uential statementsYT

End pr%cess pr%cess'labelXT

A Pr#e%%statement has a declarati%n secti%n and a statement part in declarati%n

secti%n t1pes, /ariables, c%nstants, subpr%grams, etc", can be declared" Statements part

c%ntains %nl1 se0uential statements +hich c%nsist %& 5ASE statements, IF THEN ELSE

statements, L;;2 statements, etc"

*#


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Se"%(&(/(&$ ,(%&

his list de&ines the signals that +ill cause the statements inside the pr%cess statements t%

e6ecute +hene/er %ne %r m%re elements %& the list change /alue, i"e", list %& signal that the

pr%cess is sensiti/e t%" 5hanges in the /alues %& these signals +ill cause t% pr%cess t% be

in/%ed"

Se!e"&(+, S&+&eme"&%

Se0uential statements e6ist inside the b%undaries %& a pr%cess statement, as +ell as in sub

pr%grams" he se0uential statements that are generall1 used areD

IF

CASE

LOOP

ASSERT

WAIT

IF %&+&eme"&

S$"&+7 I- (c%nditi%n) HEN

Se0uenceP%&PstatementsT

ELSE c%nditi%n HEN

Se0uence %&P statements TY

ELSE

Se0uenceP%&PstatementsTX

EN3 I-T

he I- statement start +ith the e1+%rd IFand ends +ith the e1+%rds END IF"

here are als% t+% %pti%nal clausesD the1 are the ELSEIFclause and the ELSE clause"

he c%nditi%nal c%nstruct in all cases is a B%%lean e6pressi%n" his is an e6pressi%n that

*!


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e/aluates t% either true %r &alse" Whene/er the c%nditi%n e/aluates t% a true /alue, the

se0uence %& statements &%ll%+ing are e6ecuted"IFc%nditi%n is true %r &alse the se0uence

%& statements &%r the ELSEclause is e6ecuted, i& %ne e6its" he IFstatement can ha/e

multiple ELSE IF statements parts, %nl1 %ne ELSE statement part, bet+een each

statement part can e6ist m%re than %ne se0uential statement"

CASE S&+&eme"&

he 5ASE statement is used +hene/er a single e6pressi%n /alue can be used t% select

bet+een a numbers %& acti%ns"

S$"&+7 5ASE e6pressi%n is

5asePstatemantPalternati/eT

Z5asePstatemantPalternati/e TY

EN3 5ASET

Alternati/eD WHEN ch%ice=V

Se0uenceP%&PstatementsT

Where ch%iceDD=

simplePe6pressi%n

discretePrangeelementPsimple Pname

;HERS

A 5ASE statement c%nsists %& the e1b%ard 5ASE &%ll%+ed b1 an e6pressi%n and the

e1b%ard is" he e6pressi%n +ill either return a /alue that matches %ne %& the ch%ices in a

WHENstatement part %r a match an %thers clause" A&ter these statements are e6ecuted,

c%ntr%l is trans&erred t% the statements &%ll%+ing the END CASEclause

he 5ASE statement +ill e6ecute the pr%per statement depending %n the /alue %& input

("%&r!#&(".I& the /alue %& ("%&r!#&("is %ne %& the ch%ices listed in the WHENclause

is e6ecuted"

*>


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ANNE:URE-9

**


45/53

SOURCE CODE

BI5ELL

entit1 bitcell is 2%rt ( cl,pi,sp,ldb,ld# D in S3PL;?I5T

0,0bDin%ut stdPl%gicD=)T

end bitcellT

architecture Beha/i%ral %& bitcell is

begin

pr%cess(cl)

begin

i& cle/ent and cl=# theni& ldb=# then

0U=piT

0bU=n%t(pi)Tend i&T

end i&T

end pr%cessTend Beha/i%ralT

5LF3I:!

entit1 clPdi/ is p%rt (

c%ut D%ut stdPl%gicT

c%untbD%ut stdPl%gicTenable Din stdPl%gicT

cl Din stdPl%gicT

reset Din stdPl%gic )T

end entit1Tarchitecture rtl %& clPdi/ is

signal clPdi/ DstdPl%gicT

begin

pr%cess (cl, reset) begin

i& (reset = #) then clPdi/ U= T

elsi& (risingPedge(cl)) then i& (enable = #) then

clPdi/ U= n%t clPdi/T

end i&T end i&T

end pr%cessT

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c%ut U= clPdi/T

c%untbU=n%t(clPdi/)T

end architectureT

5LF3I:>

ENIQ di/idePb1> IS2;R (

cl D IN S3PL;?I5T

resetPn D IN S3PL;?I5T%PclPb1>D ; S3PL;?I5

)T

EN3 di/idePb1>T

AR5HIE5RE Arch ;- di/idePb1> IS

SI?NAL 5;NER D NSI?NE3(# 3;WN; )T

SI?NAL di/P# D S3PL;?I5T

SI?NAL di/P! D S3PL;?I5TSI?NAL clPl%+Pcnt D S3PL;?I5T

SI?NAL clPhighPcnt D S3PL;?I5T

BE?IN

'' 5%unter generati%n

2R;5ESS(cl,resetPn)

BE?IN

I- (resetPn = ) HEN 5;NER U= [##[T

ELSI- RISIN?PE3?E(cl) HEN

I- 5;NER = [#[ HEN 5;NER U= [[T

ELSE

5;NER U= 5;NER < #T EN3 I-T

EN3 I-T

EN3 2R;5ESST

'' clPr generati%n

2R;5ESS(cl,resetPn)

BE?IN I- (resetPn = ) HEN

clPl%+Pcnt U= T

clPhighPcnt U= T ELSI- RISIN?PE3?E(cl) HEN

I- 5;NER = [[ HEN

clPl%+Pcnt U= #T

ELSE

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clPl%+Pcnt U= T

EN3 I-T

I- 5;NER = [#[ HEN clPhighPcnt U= #T

ELSE

clPhighPcnt U= T EN3 I-T

EN3 I-T

EN3 2R;5ESST

'' di/P# generati%n

2R;5ESS(cl,resetPn)

BE?IN I- (resetPn = ) HEN

di/P# U= T

ELSI- RISIN?PE3?E(cl) HEN

I- clPl%+Pcnt = # HEN di/P# U= N; di/P#T

EN3 I-T EN3 I-T

EN3 2R;5ESST

'' clP& generati%n

2R;5ESS(cl,resetPn)

BE?IN

I- (resetPn = ) HEN di/P! U= T

ELSI- -ALLIN?PE3?E(cl) HEN

I- clPhighPcnt = # HEN di/P! U= N; di/P!T

EN3 I-T

EN3 I-T EN3 2R;5ESST

%PclPb1> U= di/P# C;R di/P!T

EN3 ArchT

3LA5H

entit1 dlatch is

2%rt ( cl,d D in S3PL;?I5T0,0barD%ut stdPl%gic)T

end dlatchT

architecture Beha/i%ral %& dlatch is

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c%mp%nent nandgate is

2%rt ( a,b D in S3PL;?I5T

cDin%ut stdPl%gic)Tend c%mp%nentT

c%mp%nent n%tgate is

2%rt ( a D in S3PL;?I5TbD%ut stdPl%gic)T

end c%mp%nentT

signal ncl,m#,m!,m>,m*,s#,s!,s>,s*DstdPl%gic D=Tbegin

uDnandgate p%rt map(d,cl,m#)T

u#Dnandgate p%rt map(m#,cl,m!)T

u!Dnandgate p%rt map(m#,m*,m>)Tu>Dnandgate p%rt map(m>,m!,m*)T

u*Dn%tgate p%rt map(cl,ncl)T

uDnandgate p%rt map(m>,ncl,s#)T

u7Dnandgate p%rt map(ncl,m*,s!)TuDnandgate p%rt map(s#,s*,s>)T

u8Dnandgate p%rt map(s>,s!,s*)T

0U=s>T0barU=s*T

end Beha/i%ralT

NAN3?AEentit1 nandgate is

2%rt ( a,b D in S3PL;?I5T

cDin%ut stdPl%gic)Tend nandgateT

architecture Beha/i%ral %& nandgate isbegin

cU=a nand bT

end Beha/i%ralT

25;NERentit1 pc%unter is

2%rt ( cl D in S3PL;?I5T

%pD%ut stdPl%gicP/ect%r(7 d%+nt% ))Tend pc%unterT

architecture Beha/i%ral %& pc%unter is

signal c%DstdPl%gicP/ect%r(7 d%+nt% )D=[[T

*8


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begin

pr%cess(cl)begin

i& cle/ent and cl=# then

c%U=c%,s*,s,s7 D in S3PL;?I5T

m%d#Din%ut stdPl%gic)T

end c%mp%nentTsignal c%unDstdPl%gicP/ect%r(7 d%+nt% )D=[[T

begin

hhDpc%unter p%rt map(cl,c%un)Thh#Dsc%unter p%rt map(cl,c%un(),c%un(#),c%un(!),c%un(>),c%un(*),c%un(),m%ds)T

end Beha/i%ralT

4C

entit1 mu6!# is

2%rt ( a,b,sel D in S3PL;?I5T

% D %ut S3PL;?I5)Tend mu6!#T

architecture Beha/i%ral %& mu6!# is

begin

+ith sel select%U=a +hen ,

b +hen #,

+hen %thersT

*9


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end Beha/i%ralT

2RES5ALERentit1 prescalar is

2%rt (cl,mcDin S3PL;?I5T

%ut&,0b!Din%ut stdPl%gicD=)Tend prescalarT

architecture Beha/i%ral %& prescalar isc%mp%nent dlatch is

2%rt ( cl,d D in S3PL;?I5T

0,0barD%ut stdPl%gic)T

end c%mp%nentTsignal 6n%r!%p,ints,0,0bDstdPl%gicD=T

begin

Ddlatch p%rt map(cl,0b!,0,0b)T

intsU=0 6n%r mcT6n%r!%pU=ints 6n%r %ut&T

#Ddlatch p%rt map(cl,6n%r!%p,%ut&,0b!)Tend Beha/i%ralT

S5;NERentit1 sc%unter is

2%rt (cl,s#,s!,s>,s*,s,s7 D in S3PL;?I5T

m%d#Din%ut stdPl%gic)T

end sc%unterT

architecture Beha/i%ral %& sc%unter is

c%mp%nent bitcell is 2%rt ( cl,pi,sp,ldb,ld# D in S3PL;?I5T

0,0bDin%ut stdPl%gicD=)T

end c%mp%nentTsignal

n%r%p,n%r%p#,nand%p,nand%p#,0#,0!,0>,0*,0,07,0b#,0b!,0b>,0b*,0b,0b7DstdPl%gicD=

T

signal ldb,ld#,m%d#bDstdPl%gicD=#Tbegin

0Dbitcell p%rt map(cl,s#,m%d#,ldb,ld#,0#,0b#)T

0#Dbitcell p%rt map(0#,s!,m%d#,ldb,ld#,0!,0b!)T0!Dbitcell p%rt map(0!,s>,m%d#,ldb,ld#,0>,0b>)T

0>Dbitcell p%rt map(0>,s*,m%d#,ldb,ld#,0*,0b*)T

0*Dbitcell p%rt map(0*,s,m%d#,ldb,ld#,0,0b)T0Dbitcell p%rt map(0,s7,m%d#,ldb,ld#,07,0b7)T

n%r%p#U=0* n%r 0T

n%r%pU=n%r%p# n%r 07T


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nand%p#U=n%r%p nand 0b>T

nand%pU=nand%p# nand 0b!T

07Dbitcell p%rt map(cl,,ldb,ld#,m%d#,m%d#b)Tend Beha/i%ralT

;24;3LEentit1 t%pm%d is

2%rt ( cl,rst,en#,sel D in S3PL;?I5T

0#,0!,0>,0*Din%ut stdPl%gicD=)T

end t%pm%dT

architecture Beha/i%ral %& t%pm%d isc%mp%nent pr%p%sedmultim%d is

2%rt ( cl,rst,m%ds,en#,sel D in S3PL;?I5T

0#,0!,0>,0*Din%ut stdPl%gicD=)T

end c%mp%nentTc%mp%nent c%untersp is

2%rt (cl D in S3PL;?I5Tm%dsDin%ut stdPl%gic)T

end c%mp%nentT

signal m%dsDstdPL%gicD=#Tbegin

%%Dc%untersp p%rt map(cl,m%ds)T

%%#Dpr%p%sedmultim%d p%rt map(cl,rst,m%ds,en#,sel,0#,0!,0>,0*)T

end Beha/i%ralT

REFERENCES

#


52/53

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