RAM/Peripheral Interfacing device for 8085 and 8088

Presented By-

Siddharth Chauhan

INTRODUCTION

The 8155 is a RAM and I/O chip to be used in the 8085 and 8088 MPU system. The RAM is designed with 2K bit static cells organized as 256*8. They have a maximum access time of 440ns.

INTRODUCTION

There are 3 basic I/O ports. One of the three can be programmed to be status pins, thus allowing to the other two ports to operate in handshake mode A 14 bit counter/timer is also included in the chip to provide either a square wave or terminal count pulse for the CPU system depending on the timer mode. The programmable I/O ports can be operated by BASIC Mode and STROBE Mode

INTERFACING I/O AND PERIPHERAL DEVICES:

Data transfer from input device to processor: The

input device will load the data to the port. When the port receives a data, it sends message to the processor to read the data. The processor will read the data from the port. After a data have been read by the processor the input device will load the next data into the port.

INTERFACING I/O AND PERIPHERAL DEVICES:

Data transfer from processor to output device: The

processor will load the data to the port. The port will send a message to the output device to read the data. The output device will read the data from the port. After the data have been read by the output device the processor can load the next data to the port

FEATURES

Single +5V Power Supply. Access Time 330ns. Internal Address Latch. 2 Programmable 8bit I/O ports and 1 programmable 6bit I/O port. 256*8 bit RAM. Programmable 8bit binary Counter/Timer. Multiplexed 8bit Address/Data bus. Chip Enable active low. 40 pin DIP.

DC Characteristics

AC Characteristics

AC Characteristics

BLOCK DIAGRAM

PIN-DIAGRAMAD0-AD7 RESET CE-bar or CE ALE RD-bar WR-bar IO/Mbar PA0-7 PB0-7 PC0-5 TIMER-IN I/O I I I I I I I/O I/O I/O I Addr/Data bus mux'd Reset input Chip enable (55/56) Address latch enable Read input Write input I/O or memory section Port A (8 bit) Port B (8 bit) Port C (6 bit) Timer input Timer output

TIMER-OUT-bar O

PIN NAMES AND DESCRIPTION

RESET(I/P): The width of reset high should be two clock cycles in 8155. AD 0~7(I/P,O/P and tri-state): Theses are three state address/data lines that interface with the lower order MPU address/data bus. The 8 bit address can be applied to the memory section or the I/O section depending upon the polarity of the IO/M` signal. CE: Chip Enable is active low. RD: reading input from the memory or the Input peripheral. Active low. WR: writing output to the memory or the O/P peripheral. Active low. ALE: Address Latch Enable. Works on the falling edge. PA 0~7 / PB 0~7 : These 8 pins are general purpose I/O pins. The input output direction is set by the command register. PC 0~5: These 6 pins can function either as input port, output port or the control signals for Port A and Port B. Programming is done via command register.

Pin Names And Description

The control Signals are :-

Timer In: Input to timer counter. Timer Out: Output to timer counter. Vcc Vss (Ground)

The Command Register

The command register consists of latches. Four bits define the mode of the ports (0~3) 2 bits (4~5) define the enable or disable interrupts from Port C when its acts as control port. The last 2 bits are for the timer (6~7) The contents of the command register can be altered at any time by using I/O address XXXX000 during write operation

COMMAND REGISTER

Its also called the control word. D0, D1: mode for PA and PB, 0=i/p, 1=o/p D2, D3: mode for PC D4, D5: interrupt enable for PA and PB, 0=disable 1=enable D6, D7: Timer command: 00: No effect 01: Stop if running else no effect 10: Stop after terminal count (TC) if running, else no effect 11: Start if not running, reload at TC if running.

D7

D6

D5 IEB

D4 IEA

D3 PC

D2

D1 PB

D0 PA

Timer command

Status Register

The MPU can read the status of the ports and Timer using via status register. The address control register and status register are the same except for the read and write signals. Consists of 7 latches, one for each bit. First 6 (0~5) for the status of the ports. The last (6) for the status of the timer.

I/O SECTION

PA Register: This register can either be programmed to input or output port depending upon the status of the contents of the C/S register. Also depending upon the command it can work in the BASIC or STROBE Mode. The address of the register is XXXXX001. PB Register: Its the same as PA register. Its address is XXXXX010. PC Register: Its a 6Bit register with the address XXXXX011. It can be programmed to be either Input/output Port or to be the control register for Port A and Port B by properly programming the AD2 and AD3 bits of the C/S Register. When PC 0~5 is used as control port, 3 bits are assigned to Port A and 3 to Port B. The 1st bit is an interrupt. The 2nd is an output signal indicating weather the buffer is full or empty. 3rd is an in put signal to accept a Strobe from the Strobed Input Mode.

Structure of Ports A & B within 8155

I/O Section

When Port is programmed in either Mode 3 or Mode 4, the control signals for PA and PB as initialized as below:

I/O Addressing Scheme

PORT Control Assignment

Port Control AssignmentPort C bits (D2, D3): ALT 1 2 3 4 D3 0 1 0 1 D2 0 1 1 0 PC5 I O O PC4 I O O PC3 I O O INtr-B PC2 I O PC1 I O PC0 I O INTR-A INTR-A

STB-Abar BF-A STB-Abar BF-A

STB-Bbar BF-B

I - input O - output

TIMER

The Timer is a 14 bit down-counter that counts the timer input pulses and provides either a square wave or pulse when the terminal count is reached. Address for the Low order byte of register : XXXXX100 Address for the high order byte of register : XXXXX101 To Program the Timer, the COUNT LENGTH REGISTER is loaded first, one byte at a time, by selecting the timer addresses. Bits 0~13 specify the count of next count Bits 14~15 specify the Timer Output Mode. The value of the count length register may have any value from 2H through 3FFFH on bits 0~13.

MSB: M2 LSB: T7 T6 T5 T4 T3 T2 T1 T0 M1 T13 T12 T11 T10 T9 T8

TIMER MODES

There are 4 basic Timer Modes which may be defined by M1 and M2 :0 0: Single square wave of wavelength TC/2 (TC/2,TC/2 if TC even; [TC+1/2],[TC-1/2] if TC odd) 0 1: Square waves of wavelength TC (TC/2,TC/2 if TC even; [TC+1/2],[TC-1/2] if TC odd) 1 0: Single pulseonthe TC'th clock pulse 1 1: Single pulseonevery TC'th clock pulse.

Asymmetrical Count 5

In case of an odd numbered count, the first half cycle of the square wave output, which is high, is one count longer than the second (low) half cycle.

Timer Mode Select

Bits 6~7 (TM2 and TM1) of command register contents are used to start or stop the counter.

TWICE COUNTER

The timer circuit on the 8155 chip is designed to be square wave timer, not an event counter. To achieve this it counts down by two in completing one cycle. Its registers dont contain the values directly representing the number of TIMER IN pulses being received, Counter value 1 cant be loaded as the initial value in the count register as the timer operates with the terminal count value of 10.

#NOTE: when operating as a square wave generator, it operates as a frequency divider with the output frequency equal to the input frequency divided by count number.

HANDSHAKING MODE

The ports A and B can be used in handshaking mode with port C providing the handshaking signals. (STB) : STROBE is an input signal from the peripheral to the 8155. It indicates the MPU that the data to be read is already sent on the port lines of 8155. Upon activation of the signal 8155 loads the data from the input port lines to the input buffer of the port. BF: This is an active high signal, indicating the presence of data byte in the port. INTR: Its a high signal sent from the 8155 to the 8085 indicating that the data from the input device is ready on the input buffer. The signal is reset with the falling edge of read signal. IE: Interrupt enable signal is vital to activate the interrupt.

HANDSHAKING MODE

TIMING DIAGRAMS

Tss: (min) 200ns Tsbf: 400ns Trdi: 400ns Trbe: 400ns

STROBED INPUT MODE

INPUT MODE

Port A in input mode with handshake signal.

TIMING DIAGRAMS

STROBED OUTPUT MODE

OUTPUT MODE

Port B in output mode with handshake signal.

TIMING DIAGRAMS.

TIMER OUT WAVEFORM

TIMING DIAGRAMS.

BASIC OUTPUT MODETwp: 400ns

TIMING DIAGRAMS.

BASIC INPUT MODETpr: 70ns Trp: 50ns

TIMING DIAGRAMS.

READ CYCLET la (min): 80ns (address hold time after latch) T al (min) : 80ns (address to latch setup time) Tll (min) : 100ns (latch enable width)

TIMING DIAGRAMS

WRITE CYCLE

INTERFACING 8085 with 8155

DIMENSIONS (Intel 8155)