80C51 Family 80C51 family hardware descriptionoregonstate.edu/instruct/ece473/8051_hw.pdf · 2002....

80C51 family hardware description

Phlips Semiconductors

80C51 Family

1March 1995

HARDWARE DESCRIPTIONThis chapter provides a detailed descriptionof the 80C51 microcontroller (see Figure 1).Included in this description are:

• The port drivers and how they function bothas ports and, for Ports 0 and 2, in busoperations

• The Timers/Counters

• The Serial Interface

• The Interrupt System

• Reset

• The Reduced Power Modes in CMOSdevices

• The EPROM version of the 80C51

Port 0Drivers

Port 2Drivers

RAM AddressRegister RAM

Port 0Latch

Port 2Latch

EPROM/ROM

BRegister

ACC

TMP2 TMP1 ProgramAddressRegister

Buffer

PCIncrementer

ProgramCounter

DPTR

TL1

Interrupt, SerialPort, and Timer

Blocks

PSW

StackPointer

ALU

Port 3 Latch

Port 3Drivers

Port 1 Latch

Port 1Drivers

Timingand

Control

InstructionRegister

PSEN

EA

RST

ALE

P0.0-P0.7 P2.0-P2.7

P1.0-P1.7 P3.0-P3.7

Oscillator

XTAL1 XTAL2

PD

VCC

VSS

PCON SCON TMOD TCON

T2CON TH0 TL0 TH1

SBUF IE IP

SU00529

Figure 1. 80C51 Architecture


80C51 Family 80C51 family hardware description

March 1995 2

Special Function RegistersA Map of the on-chip memory area called theSpecial Function Register (SFR) space isshown in Figure 2.

Note that in the SFRs not all of the addressesare occupied. Unoccupied addresses are notimplemented on the chip. Read accesses tothese addresses will in general return randomdata, and write accesses will have no effect.

User software should not write 1s to theseunimplemented locations, since they may beused in other 80C51 Family derivativeproducts to invoke new features. Thefunctions of the SFRs are described in thetext that follows.

AccumulatorACC is the Accumulator register. Themnemonics for Accumulator-Specificinstructions, however, refer to theAccumulator simply as A.

B RegisterThe B register is used during multiply anddivide operations. For other instructions it canbe treated as another scratch pad register.

Program Status W ordThe PSW register contains program statusinformation as detailed in Figure 3.

Stack PointerThe Stack Pointer register is 8 bits wide. It isincremented before data is stored during

PUSH and CALL executions. While the stackmay reside anywhere in on-chip RAM, theStack Pointer is initialized to 07H after areset. This causes the stack to begin atlocations 08H.

Data PointerThe Data Pointer (DPTR) consists of a highbyte (DPH) and a low byte (DPL). Itsintended function is to hold a 16-bit address.It may be manipulated as a 16-bit register oras two independent 8-bit registers.

Ports 0 to 3P0, P1, P2, and P3 are the SFR latches ofPorts 0, 1, 2, and 3, respectively. Writing aone to a bit of a port SFR (P0, P1, P2, or P3)causes the corresponding port output pin toswitch high. Writing a zero causes the portoutput pin to switch low. When used as aninput, the external state of a port pin will beheld in the port SFR (i.e., if the external stateof a pin is low, the corresponding port SFR bitwill contain a 0; if it is high, the bit will containa 1).

Serial Data BufferThe Serial Buffer is actually two separateregisters, a transmit buffer and a receivebuffer. When data is moved to SBUF, it goesto the transmit buffer and is held for serialtransmission. (Moving a byte to SBUF is what

initiates the transmission.) When data ismoved from SBUF, it comes from the receivebuffer.

Timer Registers Basic to 80C51Register pairs (TH0, TL0), and (TH1, TL1)are the 16-bit Counting registers forTimer/Counters 0 and 1, respectively.

Control Register for the 80C51Special Function Registers IP, IE, TMOD,TCON, SCON, and PCON contain controland status bits for the interrupt system, theTimer/Counters, and the serial port. They aredescribed in later sections.

Port Structures and OperationAll four ports in the 80C51 are bidirectional.Each consists of a latch (Special FunctionRegisters P0 through P3), an output driver,and an input buffer.

The output drivers of Ports 0 and 2, and theinput buffers of Port 0, are used in accessesto external memory. In this application, Port 0outputs the low byte of the external memoryaddress, time-multiplexed with the byte beingwritten or read.

Port 2 outputs the high byte of the externalmemory address when the address is 16 bitswide. Otherwise, the Port 2 pins continue toemit the P2 SFR content.

F8

F0

E8

E0

D8

D0

C8

C0

B8

B0

A8

A0

98

90

88

80

B

ACC

PSW

IP

P3

IE

P2

P1

FF

F7

EF

E7

DF

D7

CF

C7

BF

B7

AF

A7

9F

97

8F

87

BIT ADDRESSABLE

8 BYTES

SCON SBUF

TCON TMOD TL0 TL1 TH0 TH1

P0 SP DPL DPH PCON

SU00530

Figure 2. 80C51 SFR Memory Map



March 1995 3

CY AC F0 RS1 RS OV — P

LSBMSB

BIT SYMBOL FUNCTIONPSW.7 CY Carry flag.PSW.6 AC Auxilliary Carry flag. (For BCD operations.)PSW.5 F0 Flag 0. (Available to the user for general purposes.)PSW.4 RS1 Register bank select control bit 1.

Set/cleared by software to determine working register bank. (See Note.)PSW.3 RS0 Register bank select control bit 0.

Set/cleared by software todetermine working register bank. (See Note.)PSW.2 OV Overflow flag.PSW.1 — User-definable flag.PSW.0 P Parity flag.

Set/cleared by hardware each instruction cycle to indicate an odd/evennumber of “one” bits in the Accumulator, i.e., even parity.

NOTE: The contents of (RS1, RS0) enable the working register banks as follows:(0,0)— Bank 0 (00H–07H)(0,1)— Bank 1 (08H–0fH)(1,0)— Bank 2 (10H–17H)(1,1)— Bank 3 (18H–17H)

SU00531

Figure 3. Program Status W ord (PSW) Register

All the Port 3 pins are multifunctional. Theyare not only port pins, but also serve thefunctions of various special features as listedbelow:

Port Pin Alternate FunctionP3.0 RxD (serial input port)P3.1 TxD (serial output port)P3.2 INT0 (external interrupt)P3.3 INT1 (external interrupt)P3.4 T0 (Timer/Counter 0 external input)P3.5 T1 (Timer/Counter 1 external input)P3.6 WR (external Data Memory write

strobe)P3.7 RD (external Data Memory read strobe)

The alternate functions can only be activatedif the corresponding bit latch in the port SFRcontains a 1. Otherwise the port pin remainsat 0.

I/O ConfigurationsFigure 4 shows a functional diagram of atypical bit latch and I/O buffer in each of thefour ports. The bit latch (one bit in the port’sSFR) is represented as a Type D flip-flop,which will clock in a value from the internalbus in response to a “write to latch” signalfrom the CPU. The level of the port pin itselfis placed on the internal bus in response to a“read pin” signal from the CPU. Someinstructions that read a port activate the “readlatch” signal, and others activate the “readpin” signal.

As shown in Figure 4, the output drivers ofPort 0 and 2 are switchable to an internalADDR and ADDR/DATA bus by an internal

CONTROL signal for use in external memoryaccesses. During external memory accesses,the P2 SFR remains unchanged, but the P0SFR gets 1s written to it.

Also shown in Figure 4 is that if a P3 bit latchcontains a 1, then the output level iscontrolled by the signal labeled “alternateoutput function.” The actual P3.X pin level isalways available to the pin’s alternate inputfunction, if any.

Ports 1, 2, and 3 have internal pullups, andPort 0 has open drain outputs. Each I/O linecan be independently used as an input or anoutput. (Port 0 and 2 may not be used asgeneral purpose I/O when being used as theADDR/DATA BUS for external memory duringnormal operation.) To be used as an input,the port bit latch must contain a 1, whichturns off the output driver FET. Then, forPorts 1, 2, and 3, the pin is pulled high by aweak internal pullup, and can be pulled lowby an external source.

Port 0 differs in that its internal pullups arenot active during normal port operation. Thepullup FET in the P0 output driver (seeFigure 4) is used only when the port is emitting1s during external memory accesses.Otherwise the pullup FET is off. ConsequentlyP0 lines that are being used as output portlines are open drain. Writing a 1 to the bitlatch leaves both output FETs off, so the pinfloats. In that condition it can be used as ahigh-impedance input.

Because Ports 1, 2, and 3 have fixed internalpullups, they are sometimes called “quasi-

bidirectional” ports. When configured asinputs they pull high and will source current(IIL, in the data sheets) when externallypulled low. Port 0, on the other hand, isconsidered “true” bidirectional, because whenconfigured as an input it floats.

All the port latches in the 80C51 have 1swritten to them by the reset function. If a 0 issubsequently written to a port latch, it can bereconfigured as an input by writing a 1 to it.

Writing to a PortIn the execution of an instruction thatchanges the value in a port latch, the newvalue arrives at the latch during S6P2 of thefinal cycle of the instruction. However, portlatches are in fact sampled by their outputbuffers only during Phase 1 of an clockperiod. (During Phase 2 the output bufferholds the value it saw during the previousPhase 1). Consequently, the new value in theport latch won’t actually appear at the outputpin until the next Phase 1, which will be atS1P1 of the next machine cycle.

If the change requires a 0-to-1 transition inPort 1, 2, or 3, an additional pullup is turnedon during S1P1 and S1P2 of the cycle inwhich the transition occurs. This is done toincrease the transition speed. The extrapullup can source about 100 times thecurrent that the normal pullup can. It shouldbe noted that the internal pullups arefield-effect transistors, not linear resistors.The pullup arrangements are shown inFigure 5.



March 1995 4

D QP0.XLatch

CL Q MUX

ADDR/Data

ControlReadLatch

Int. Bus

Write toLatch

ReadPin

P0.XPin

VCC

a. Port 0 Bit

D QP2.XLatch

CL Q

MUX

ADDR/Data

ControlReadLatch

Int. Bus

Write toLatch

ReadPin

P2.XPin

VCC

c. Port 2 Bit

InternalPullup*

D QP1.XLatch

CL Q

ReadLatch

Int. Bus

Write toLatch

ReadPin

P1.XPin

VCC

InternalPullup*

b. Port 1 Bit

D QP3.XLatch

CL Q

ReadLatch

Int. Bus

Write toLatch

ReadPin

P3.XPin

VCC

InternalPullup*

d. Port 3 Bit

AlternateOutput

Function

AlternateInput

Function

SU00532

*See Figure 5 for details of the internal pullup.Figure 4. 80C51 Port Bit Latches and I/O Buffers

In the NMOS 8051 part, the fixed part of thepullup is a depletion mode transistor with thegate wired to the source. This transistor willallow the pin to source about 0.25mA whenshorted to ground. In parallel with the fixedpullup is an enhancement mode transistor,which is activated during S1 whenever theport bit does a 0-to-1 transition. During thisinterval, if the port pin is shorted to ground,this extra transistor will allow the pin tosource an additional 30mA.

In the CMOS 80C51, the pullup consists ofthree pFETs. It should be noted that ann-channel FET (nFET) is turned on when alogical 1 is applied to its gate, and is turnedoff when a logical 0 is applied to its gate. Ap-channel FET (pFET) is the opposite: it is onwhen its gate sees a 0, and off when its gatesees a 1.

pFET1 in Figure 5 is the transistor that isturned on for 2 oscillator periods after a0-to-1 transition in the port latch. While it’son, it turns on pFET3 (a weak pullup),through the inverter. This inverter and pFET3form a latch which holds the 1.

Note that if the pin is emitting a 1, a negativeglitch on the pin from some external sourcecan turn off pFET3, causing the pin to go intoa float state. pFET2 is a very weak pullupwhich is on whenever the nFET is off, intraditional CMOS style. It’s only about 1/10the strength of pFET1. Its function is torestore a 1 to the pin in the event the pin hada 1 and lost it to a glitch.

Port Loading and InterfacingThe output buffers of Ports 1, 2, and 3 caneach drive 4 LS TTL inputs. These ports on

NMOS versions can be driven in a normalmanner by a TTL or NMOS circuit. BothNMOS and CMOS pins can be driven byopen-collector and open-drain outputs, butnote that 0-to-1 transitions will not be fast.

In the NMOS device, if the pin is driven by anopen-collector output, a 0-to-1 transition willhave to be driven by the relatively weakdepletion mode FET in Figure 5a. In theCMOS device, an input 0 turns off pulluppFET3, leaving only the very weak pulluppFET2 to drive the transition.

Port 0 output buffers can each drive 8 LS TTLinputs. They do, however, require externalpullups to drive NMOS inputs, except whenbeing used as the ADDRESS/DATA bus forexternal memory.



March 1995 5

VCC

a. NMOS Configuration.The enhancement mode transistor is turned on for 2 oscillator periods after Q makes a 0-to-1 transition.

Q

2 Osc. Periods

Enhancement Mode FET

Depletion Mode FET

PortPin

VSS

VCC

b. CMOS Configuration.pFET1 is turned on for 2 oscillator periods after Q makes a 0-to-1 transition.

During this time, pFET1 also turns on pFET3 through the inverter to form a latch which holds the 1. pFET2 is also on.

Q

2 Osc. Periods

PortPin

n

From PortLatch

VCC VCC

P1 P2 P3

Input Data

Read Port Pin

From PortLatch

SU00533

Figure 5. Ports 1 and 3 NMOS and CMOS Internal Pullup Configurations(Port 2 is similar except that it holds the strong pullup on while emitting 1s that are address bits. See Accessing External Memory.)

Read-Modify-W rite FeatureSome instructions that read a port read thelatch and others read the pin. Which ones dowhich? The instructions that read the latchrather than the pin are the ones that read avalue, possibly change it, and then rewrite itto the latch. These are called“read-modify-write” instructions. Theinstructions listed below areread-modify-write instructions. When thedestination operand is a port, or a port bit,these instructions read the latch rather thanthe pin:

ANL (logical AND, e.g., ANL P1,A)ORL (logical OR, e.g., ORL P2,A)

XRL (logical EX-OR, e.g., XRL P3,A)JBC (jump if bit = 1 and clear bit,

e.g., JBC P1.1,LABEL)CPL (complement bit, e.g., CPL P3.0)INC (increment, e.g., INC P2)DEC (decrement, e.g., DEC P2)DJNZ (decrement and jump if not

zero, e.g., DJNZ P3,LABEL)MOV PX.Y,C (move carry bit to bit Y of Port X)CLR PX.Y (clear bit Y of Port X)SET PX.Y (set bit Y of Port X)

It is not obvious that the last threeinstructions in this list are read-modify-writeinstructions, but they are. They read the port

byte, all 8 bits, modify the addressed bit, thenwrite the new byte back to the latch.

The reason that read-modify-writeinstructions are directed to the latch ratherthan the pin is to avoid a possiblemisinterpretation of the voltage level at thepin. For example, a port bit might be used todrive the base of a transistor. When a 1 iswritten to the bit, the transistor is turned on. Ifthe CPU then reads the same port bit at thepin rather than the latch, it will read the basevoltage of the transistor and interpret it as a0. Reading the latch rather than the pin willreturn the correct value of 1.



March 1995 6

Accessing External MemoryAccesses to external memory are of twotypes: accesses to external Program Memoryand accesses to external Data Memory.Accesses to external Program Memory usesignal PSEN (program store enable) as theread strobe. Accesses to external DataMemory use RD or WR (alternate functionsof P3.7 and P3.6) to strobe the memory.Fetches from external Program Memoryalways use a 16-bit address. Accesses toexternal Data Memory can use either a 16-bitaddress (MOVX @ DPTR) or an 8-bitaddress (MOVX @Ri).

Whenever a 16-bit address is used, the highbyte of the address comes out on Port 2,where it is held for the duration of the read orwrite cycle. Note that the Port 2 drivers usethe strong pullups during the entire time thatthey are emitting address bits that are 1s.This is during the execution of a MOVX@DPTR instruction. During this time the Port2 latch (the Special Function Register) doesnot have to contain 1s, and the contents ofthe Port 2 SFR are not modified. If theexternal memory cycle is not immediatelyfollowed by another external memory cycle,the undisturbed contents of the Port 2 SFRwill reappear in the next cycle.

If an 8-bit address is being used (MOVX@Ri), the contents of the Port 2 SFR remainat the Port 2 pins throughout the externalmemory cycle. This will facilitate paging.

In any case, the low byte of the address istime-multiplexed with the data byte on Port 0.The ADDR/DATA signals drive both FETs inthe Port 0 output buffers. Thus, in thisapplication the Port 0 pins are not open-drainoutputs, and do not require external pullups.ALE (Address Latch Enable) should be usedto capture the address byte into an externallatch. The address byte is valid at thenegative transition of ALE. Then, in a writecycle, the data byte to be written appears onPort 0 just before WR is activated, andremains there until after WR is deactivated. Ina read cycle, the incoming byte is acceptedat Port 0 just before the read strobe isdeactivated.

During any access to external memory, theCPU writes 0FFH to the Port 0 latch (theSpecial Function Register), thus obliteratingwhatever information the Port 0 SFR mayhave been holding.

External Program Memory is accessed undertwo conditions: Whenever signal EA is active;or whenever the program counter (PC)contains a number that is larger than 0FFFH(in the 80C51).

This require that the ROMless versions haveEA wired low to enable the lower 4k programbytes to be fetched from external memory.

When the CPU is executing out of externalProgram Memory, all 8 bits of Port 2 arededicated to an output function and may notbe used for general purpose I/O. Duringexternal program fetches they output the highbyte of the PC. During this time the Port 2drivers use the strong pullups to emit PC bitsthat are 1s.

Timer/CountersThe 80C51 has two 16-bit Timer/Counterregisters: Timer 0 and Timer 1. Both can beconfigured to operate either as timers orevent counters (see Figure 6).

In the “Timer” function, the register isincremented every machine cycle. Thus, onecan think of it as counting machine cycles.Since a machine cycle consists of 12oscillator periods, the count rate is 1/12 of theoscillator frequency.

In the “Counter” function, the register isincremented in response to a 1-to-0 transitionat its corresponding external input pin, T0 orT1. In this function, the external input issampled during S5P2 of every machinecycle.

When the samples show a high in one cycleand a low in the next cycle, the count isincremented. The new count value appears inthe register during S3P1 of the cyclefollowing the one in which the transition wasdetected. Since it takes 2 machine cycles (24oscillator periods) to recognize a 1-to-0transition, the maximum count rate is 1/24 ofthe oscillator frequency. There are norestrictions on the duty cycle of the externalinput signal, but to ensure that a given level issampled at least once before it changes, itshould be held for at least one full cycle. Inaddition to the “Timer” or “Counter” selection,Timer 0 and Timer 1 have four operatingmodes from which to select.

Timer 0 and T imer 1The “Timer” or “Counter” function is selectedby control bits C/T in the Special FunctionRegister TMOD. These two Timer/Countershave four operating modes, which areselected by bit-pairs (M1, M0) in TMOD.Modes 0, 1, and 2 are the same for bothTimers/Counters. Mode 3 is different. Thefour operating modes are described in thefollowing text.

Mode 0Putting either Timer into Mode 0 makes itlook like an 8048 Timer, which is an 8-bitCounter with a divide-by-32 prescaler.

Figure 7 shows the Mode 0 operation as itapplies to Timer 1.

In this mode, the Timer register is configuredas a 13-bit register. As the count rolls overfrom all 1s to all 0s, it sets the Timer interruptflag TF1. The counted input is enabled to theTimer when TR1 = 1 and either GATE = 0 orINT1 = 1. (Setting GATE = 1 allows the Timerto be controlled by external input INT1, tofacilitate pulse width measurements). TR1 isa control bit in the Special Function RegisterTCON (Figure 8). GATE is in TMOD.

The 13-bit register consists of all 8 bits ofTH1 and the lower 5 bits of TL1. The upper 3bits of TL1 are indeterminate and should beignored. Setting the run flag (TR1) does notclear the registers.

Mode 0 operation is the same for the Timer 0as for Timer 1. Substitute TR0, TF0, andINT0 for the corresponding Timer 1 signals inFigure 7. There are two different GATE bits,one for Timer 1 (TMOD.7) and one for Timer0 (TMOD.3).

Mode 1Mode 1 is the same as Mode 0, except thatthe Timer register is being run with all 16 bits.

Mode 2Mode 2 configures the Timer register as an8-bit Counter (TL1) with automatic reload, asshown in Figure 9. Overflow from TL1 notonly sets TF1, but also reloads TL1 with thecontents of TH1, which is preset by software.The reload leaves TH1 unchanged.

Mode 2 operation is the same forTimer/Counter 0.

Mode 3Timer 1 in Mode 3 simply holds its count. Theeffect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0as two separate counters. The logic for Mode3 on Timer 0 is shown in Figure 10. TL0 usesthe Timer 0 control bits: C/T, GATE, TR0,INT0, and TF0. TH0 is locked into a timerfunction (counting machine cycles) and takesover the use of TR1 and TF1 from Timer 1.Thus, TH0 now controls the “Timer 1”interrupt.

Mode 3 is provided for applications requiringan extra 8-bit timer on the counter. WithTimer 0 in Mode 3, an 80C51 can look like ithas three Timer/Counters. When Timer 0 is inMode 3, Timer 1 can be turned on and off byswitching it out of and into its own Mode 3, orcan still be used by the serial port as a baudrate generator, or in fact, in any applicationnot requiring an interrupt.



March 1995 7

GATE C/T M1 M0 GATE C/T M1 M0

LSBMSB

GATE Gating control when set. Timer/Counter “x” is enabled only while “INTx” pin is high and “TRx” control pin is set. when cleared Timer “x” is enabled whenever “TRx” control bit is set.

C/T Timer or Counter Selector cleared for Timer operation (input from in=ternal system clock.) Set for Counter operation (input from “Tx” input pin).

M1 M0 OPERATING0 0 8048 Timer “TLx” serves as 5-bit prescaler.0 1 16-bit Timer/Counter “THx” and “TLx” are cascaded; there is no prescaler.1 0 8-bit auto-reload Timer/Counter “THx” holds a value which is to be reloaded

into “TLx” each time it overflows.1 1 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only controlled by Timer 1 control bits.1 1 (Timer 1) Timer/Counter 1 stopped. SU00534

TIMER 1 TIMER 0

Figure 6. T imer/Counter Mode Control (TMOD) Register

INT1 Pin

Osc. ÷12

T1 Pin

Gate

TR1

TL1(5 Bits)

TH1(8 Bits) TF1 Interrupt

Control

C/T = 0

C/T = 1

SU00535

Figure 7. T imer/Counter Mode 0: 13-Bit Counter

IT0

LSBMSB

BIT SYMBOL FUNCTIONTCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software.TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off.TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software.TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off.TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.TCON.2 IT1 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered

external interrupts.TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.TCON.0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level

triggered external interrupts.

SU00536

IE0IT1IE1TR0TF0TR1TF1

Figure 8. T imer/Counter Control (TCON) Register



March 1995 8

Osc. ÷12

T1 Pin

TL1(8 Bits) TF1 Interrupt

Control

C/T = 0

C/T = 1

TH1(8 Bits)

Reload

INT1 Pin

Gate

TR1

SU00537

Figure 9. T imer/Counter Mode 2: 8-Bit Auto-Load

Osc. ÷12

T0 Pin

TL0(8 Bits) TF0 Interrupt

Control

C/T = 0

C/T = 1

1/12 fOSC

TH0(8 Bits) TF1 Interrupt1/12 fOSC

Control

TR1

1/12 fOSC

INT0 Pin

Gate

TR0

SU00538

Figure 10. T imer/Counter 0 Mode 3: T wo 8-Bit Counters



March 1995 9

Standard Serial InterfaceThe serial port is full duplex, meaning it cantransmit and receive simultaneously. It is alsoreceive-buffered, meaning it can commencereception of a second byte before apreviously received byte has been read fromthe register. (However, if the first byte stillhasn’t been read by the time reception of thesecond byte is complete, one of the bytes willbe lost.) The serial port receive and transmitregisters are both accessed at SpecialFunction Register SBUF. Writing to SBUFloads the transmit register, and reading SBUFaccesses a physically separate receiveregister.

The serial port can operate in 4 modes:

Mode 0: Serial data enters and exitsthrough RxD. TxD outputs the shift clock. 8bits are transmitted/received (LSB first). Thebaud rate is fixed at 1/12 the oscillatorfrequency.

Mode 1: 10 bits are transmitted (throughTxD) or received (through RxD): a start bit(0), 8 data bits (LSB first), and a stop bit (1).On receive, the stop bit goes into RB8 inSpecial Function Register SCON. The baudrate is variable.

Mode 2: 11 bits are transmitted (throughTxD) or received (through RxD): start bit (0),8 data bits (LSB first), a programmable 9thdata bit, and a stop bit (1). On Transmit, the9th data bit (TB8 in SCON) can be assignedthe value of 0 or 1. Or, for example, the paritybit (P, in the PSW) could be moved into TB8.On receive, the 9th data bit goes into RB8 inSpecial Function Register SCON, while thestop bit is ignored. The baud rate isprogrammable to either 1/32 or 1/64 theoscillator frequency.

Mode 3: 11 bits are transmitted (throughTxD) or received (through RxD): a start bit(0), 8 data bits (LSB first), a programmable9th data bit, and a stop bit (1). In fact, Mode 3is the same as Mode 2 in all respects exceptbaud rate. The baud rate in Mode 3 isvariable.

In all four modes, transmission is initiated byany instruction that uses SBUF as adestination register. Reception is initiated inMode 0 by the condition RI = 0 and REN = 1.Reception is initiated in the other modes bythe incoming start bit if REN = 1.

Multiprocessor CommunicationsModes 2 and 3 have a special provision formultiprocessor communications. In thesemodes, 9 data bits are received. The 9th onegoes into RB8. Then comes a stop bit. Theport can be programmed such that when thestop bit is received, the serial port interruptwill be activated only if RB8 = 1. This featureis enabled by setting bit SM2 in SCON. Away to use this feature in multiprocessorsystems is as follows:

When the master processor wants to transmita block of data to one of several slaves, itfirst sends out an address byte whichidentifies the target slave. An address bytediffers from a data byte in that the 9th bit is 1in an address byte and 0 in a data byte. WithSM2 = 1, no slave will be interrupted by adata byte. An address byte, however, willinterrupt all slaves, so that each slave canexamine the received byte and see if it isbeing addressed. The addressed slave willclear its SM2 bit and prepare to receive thedata bytes that will be coming. The slavesthat weren’t being addressed leave theirSM2s set and go on about their business,ignoring the coming data bytes.

SM2 has no effect in Mode 0, and in Mode 1can be used to check the validity of the stopbit. In a Mode 1 reception, if SM2 = 1, thereceive interrupt will not be activated unless avalid stop bit is received.

Serial Port Control RegisterThe serial port control and status register isthe Special Function Register SCON, shownin Figure 11. This register contains not onlythe mode selection bits, but also the 9th databit for transmit and receive (TB8 and RB8),and the serial port interrupt bits (TI and RI).

Baud RatesThe baud rate in Mode 0 is fixed: Mode 0Baud Rate = Oscillator Frequency / 12. Thebaud rate in Mode 2 depends on the value ofbit SMOD in Special Function RegisterPCON. If SMOD = 0 (which is the value onreset), the baud rate is 1/64 the oscillatorfrequency. If SMOD = 1, the baud rate is 1/32the oscillator frequency.

Mode 2 Baud Rate =

2SMOD

64 (Oscillator Frequency)

In the 80C51, the baud rates in Modes 1 and3 are determined by the Timer 1 overflowrate.

Using T imer 1 to Generate Baud RatesWhen Timer 1 is used as the baud rategenerator, the baud rates in Modes 1 and 3are determined by the Timer 1 overflow rateand the value of SMOD as follows:

Mode 1, 3 Baud Rate =

2SMOD

32 (Timer 1 Overflow Rate)

The Timer 1 interrupt should be disabled inthis application. The Timer itself can beconfigured for either “timer” or “counter”operation, and in any of its 3 running modes.In the most typical applications, it isconfigured for “timer” operation, in theauto-reload mode (high nibble of TMOD =0010B). In that case the baud rate is given bythe formula:

Mode 1, 3 Baud Rate =

2SMOD

32

Oscillator Frequency12 [256 (TH1)]

One can achieve very low baud rates withTimer 1 by leaving the Timer 1 interruptenabled, and configuring the Timer to run asa 16-bit timer (high nibble of TMOD =0001B), and using the Timer 1 interrupt to doa 16-bit software reload. Figure 12 listsvarious commonly used baud rates and howthey can be obtained from Timer 1.



March 1995 10

SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not beactivated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was notreceived. In Mode 0, SM2 should be 0.

REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,RB8 is not used.

TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the othermodes, in any serial transmission. Must be cleared by software.

RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the othermodes, in any serial reception (except see SM2). Must be cleared by software.

MSB LSB

SM0 SM1 SM2 REN TB8 RB8 TI RI

Where SM0, SM1 specify the serial port mode, as follows:

SM0 SM1 Mode Description Baud Rate0 0 0 shift register fosc/ 120 1 1 8-bit UART variable1 0 2 9-bit UART fosc/64 or fosc/321 1 3 9-bit UART variable

SU00120

Figure 1 1. Serial Port Control (SCON) Register

Baud Rate fOSC SMODTimer 1

Baud Rate fOSC SMODC/T Mode Reload Value

Mode 0 Max: 1.67MHz 20MHz X X X X

Mode 2 Max: 625k 20MHz 1 X X XMode 1, 3 Max: 104.2k 20MHz 1 0 2 FFH

19.2k 11.059MHz 1 0 2 FDH9.6k 11.059MHz 0 0 2 FDH4.8k 11.059MHz 0 0 2 FAH2.4k 11.059MHz 0 0 2 F4H1.2k 11.059MHz 0 0 2 E8H

137.5 11.986MHz 0 0 2 1DH110 6MHz 0 0 2 72H110 12MHz 0 0 1 FEEBH

Figure 12. T imer 1 Generated Commonly Used Baud Rates

More About Mode 0Serial data enters and exits through RxD.TxD outputs the shift clock. 8 bits aretransmitted/received: 8 data bits (LSB first).The baud rate is fixed a 1/12 the oscillatorfrequency.

Figure 13 shows a simplified functionaldiagram of the serial port in Mode 0, andassociated timing.

Transmission is initiated by any instructionthat uses SBUF as a destination register. The“write to SBUF” signal at S6P2 also loads a 1into the 9th position of the transmit shiftregister and tells the TX Control block tocommence a transmission. The internaltiming is such that one full machine cycle will

elapse between “write to SBUF” andactivation of SEND.

SEND enables the output of the shift registerto the alternate output function line of P3.0and also enable SHIFT CLOCK to thealternate output function line of P3.1. SHIFTCLOCK is low during S3, S4, and S5 of everymachine cycle, and high during S6, S1, andS2. At S6P2 of every machine cycle in whichSEND is active, the contents of the transmitshift are shifted to the right one position.

As data bits shift out to the right, zeros comein from the left. When the MSB of the databyte is at the output position of the shiftregister, then the 1 that was initially loadedinto the 9th position, is just to the left of the

MSB, and all positions to the left of thatcontain zeros. This condition flags the TXControl block to do one last shift and thendeactivate SEND and set T1. Both of theseactions occur at S1P1 of the 10th machinecycle after “write to SBUF.”

Reception is initiated by the conditionREN = 1 and R1 = 0. At S6P2 of the nextmachine cycle, the RX Control unit writes thebits 11111110 to the receive shift register, andin the next clock phase activates RECEIVE.

RECEIVE enable SHIFT CLOCK to thealternate output function line of P3.1. SHIFTCLOCK makes transitions at S3P1 and S6P1of every machine cycle. At S6P2 of everymachine cycle in which RECEIVE is active,



March 1995 11

the contents of the receive shift register areshifted to the left one position. The value thatcomes in from the right is the value that wassampled at the P3.0 pin at S5P2 of the samemachine cycle.

As data bits come in from the right, 1s shiftout to the left. When the 0 that was initiallyloaded into the rightmost position arrives atthe leftmost position in the shift register, itflags the RX Control block to do one last shiftand load SBUF. At S1P1 of the 10th machinecycle after the write to SCON that cleared RI,RECEIVE is cleared as RI is set.

More About Mode 1Ten bits are transmitted (through TxD), orreceived (through RxD): a start bit (0), 8 databits (LSB first), and a stop bit (1). On receive,the stop bit goes into RB8 in SCON. In the80C51 the baud rate is determined by theTimer 1 overflow rate.

Figure 14 shows a simplified functionaldiagram of the serial port in Mode 1, andassociated timings for transmit receive.

Transmission is initiated by any instructionthat uses SBUF as a destination register. The“write to SBUF” signal also loads a 1 into the9th bit position of the transmit shift registerand flags the TX Control unit that atransmission is requested. Transmissionactually commences at S1P1 of the machinecycle following the next rollover in thedivide-by-16 counter. (Thus, the bit times aresynchronized to the divide-by-16 counter, notto the “write to SBUF” signal.)

The transmission begins with activation ofSEND which puts the start bit at TxD. One bittime later, DATA is activated, which enablesthe output bit of the transmit shift register toTxD. The first shift pulse occurs one bit timeafter that.

As data bits shift out to the right, zeros areclocked in from the left. When the MSB of thedata byte is at the output position of the shiftregister, then the 1 that was initially loadedinto the 9th position is just to the left of theMSB, and all positions to the left of thatcontain zeros. This condition flags the TXControl unit to do one last shift and thendeactivfate SEND and set TI. This occurs atthe 10th divide-by-16 rollover after “write toSBUF.”

Reception is initiated by a detected 1-to-0transition at RxD. For this purpose RxD issampled at a rate of 16 times whatever baudrate has been established. When a transitionis detected, the divide-by-16 counter isimmediately reset, and 1FFH is written intothe input shift register. Resetting thedivide-by-16 counter aligns its rollovers withthe boundaries of the incoming bit times.

The 16 states of the counter divide each bittime into 16ths. At the 7th, 8th, and 9thcounter states of each bit time, the bitdetector samples the value of RxD. Thevalue accepted is the value that was seen inat least 2 of the 3 samples. This is done fornoise rejection. If the value accepted duringthe first bit time is not 0, the receive circuitsare reset and the unit goes back to lookingfor another 1-to-0 transition. This is to providerejection of false start bits. If the start bitproves valid, it is shifted into the input shiftregister, and reception of the rest of the framewill proceed.

As data bits come in from the right, 1s shiftout to the left. When the start bit arrives at theleftmost position in the shift register (which inmode 1 is a 9-bit register), it flags the RXControl block to do one last shift, load SBUFand RB8, and set RI. The signal to loadSBUF and RB8, and to set RI, will begenerated if, and only if, the followingconditions are met at the time the final shiftpulse is generated.:1. R1 = 0, and2. Either SM2 = 0,

or the received stop bit = 1.

If either of these two conditions is not met,the received frame is irretrievably lost. If bothconditions are met, the stop bit goes intoRB8, the 8 data bits go into SBUF, and RI isactivated. At this time, whether the aboveconditions are met or not, the unit goes backto looking for a 1-to-0 transition in RxD.

More About Modes 2 and 3Eleven bits are transmitted (through TxD), orreceived (through RxD): a start bit (0), 8 databits (LSB first), a programmable 9th data bit,and a stop bit (1). On transmit, the 9th databit (TB8) can be assigned the value of 0 or 1.On receive, the 9the data bit goes into RB8 inSCON. The baud rate is programmable toeither 1/32 or 1/64 the oscillator frequency inMode 2. Mode 3 may have a variable baudrate generated from Timer 1.

Figures 15 and 16 show a functional diagramof the serial port in Modes 2 and 3. Thereceive portion is exactly the same as inMode 1. The transmit portion differs fromMode 1 only in the 9th bit of the transmit shiftregister.

Transmission is initiated by any instructionthat uses SBUF as a destination register. The“write to SBUF” signal also loads TB8 into the9th bit position of the transmit shift registerand flags the TX Control unit that atransmission is requested. Transmissioncommences at S1P1 of the machine cyclefollowing the next rollover in the divide-by-16counter. (Thus, the bit times are

synchronized to the divide-by-16 counter, notto the “write to SBUF” signal.)

The transmission begins with activation ofSEND, which puts the start bit at TxD. Onebit time later, DATA is activated, whichenables the output bit of the transmit shiftregister to TxD. The first shift pulse occursone bit time after that. The first shift clocks a1 (the stop bit) into the 9th bit position of theshift register. Thereafter, only zeros areclocked in. Thus, as data bits shift out to theright, zeros are clocked in from the left. WhenTB8 is at the output position of the shiftregister, then the stop bit is just to the left ofTB8, and all positions to the left of thatcontain zeros. This condition flags the TXControl unit to do one last shift and thendeactivate SEND and set TI. This occurs atthe 11th divide-by-16 rollover after “write toSUBF.”

Reception is initiated by a detected 1-to-0transition at RxD. For this purpose RxD issampled at a rate of 16 times whatever baudrate has been established. When a transitionis detected, the divide-by-16 counter isimmediately reset, and 1FFH is written to theinput shift register.

At the 7th, 8th, and 9th counter states of eachbit time, the bit detector samples the value ofR-D. The value accepted is the value thatwas seen in at least 2 of the 3 samples. If thevalue accepted during the first bit time is not0, the receive circuits are reset and the unitgoes back to looking for another 1-to-0transition. If the start bit proves valid, it isshifted into the input shift register, andreception of the rest of the frame willproceed.

As data bits come in from the right, 1s shiftout to the left. When the start bit arrives at theleftmost position in the shift register (which inModes 2 and 3 is a 9-bit register), it flags theRX Control block to do one last shift, loadSBUF and RB8, and set RI.

The signal to load SBUF and RB8, and to setRI, will be generated if, and only if, thefollowing conditions are met at the time thefinal shift pulse is generated.1. RI = 0, and2. Either SM2 = 0,

or the received 9th data bit = 1.

If either of these conditions is not met, thereceived frame is irretrievably lost, and RI isnot set. If both conditions are met, thereceived 9th data bit goes into RB8, and thefirst 8 data bits go into SBUF. One bit timelater, whether the above conditions were metor not, the unit goes back to looking for a1-to-0 transition at the RxD input.



March 1995 12

80C51 Internal Bus

SBUF

Zero Detector

D QS

CL

Write to

SBUF

TX Control

TX Clock Send

ShiftStart

S6

RX Control

Start

Shift

ReceiveRX Clock

T1

R1

SerialPort

Interrupt

1 1 1 1 1 1 1 0

Input Shift Register

REN

RI

LoadSBUF

Shift

ShiftClock

RxDP3.0 AltOutput

Function

TxDP3.1 AltOutput

Function

SBUF

ReadSBUF

80C51 Internal Bus

RxDP3.0 Alt

InputFunction

Write to SBUF

S6P2Send

Shift

RxD (Data Out) D0 D1 D2 D3 D4 D5 D6 D7

Transmit

TxD (Shift Clock)

TIS3P1 S6P1

Write to SCON (Clear RI)

RI

Receive

Shift

RxD (Data In) D0 D1 D2 D3 D4 D5 D6

TxD (Shift Clock)

S5P2

Receive

D7

ALE

S4 . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1 S6. . . . S1

SU00539

Figure 13. Serial Port Mode 0



March 1995 13

80C51 Internal Bus

SBUF

Zero Detector

D QS

CL

Write to

SBUF

TX Control

TX Clock Send

DataStart

RX ControlStart

RX Clock RI

T1

SerialPort

Interrupt

Input Shift Register(9 Bits)

LoadSBUF

Shift

SBUF

ReadSBUF

80C51 Internal Bus

TxD

TB8

÷ 16

1-to-0TransitionDetector

Sample

÷ 2

Timer 1Overflow

SMOD = 1SMOD = 0

Shift

Bit Detector

Transmit

Send

S1P1

Shift

TXClock

Write to SBUF

Start BitTxD Stop BitD0 D1 D2 D3 D4 D5 D6 D7

TI

RxD

RXClock

÷ 16 Reset

StartBitRxD Stop BitD0 D1 D2 D3 D4 D5 D6 D7

Bit DetectorSample Times

Shift

RI

Receive

Data

÷ 16

LoadSBUF

Shift

1FFH

SU00540




March 1995 14

80C51 Internal Bus

SBUF

Zero Detector

D QS

CL

Write to

SBUF

TX Control

TX Clock Send

DataStart

RX ControlStart

LoadSBUF

RX Clock

T1

SerialPort

Interrupt


LoadSBUF

Shift

SBUF

ReadSBUF

80C51 Internal Bus

TxD

TB8

÷ 16


Sample

÷ 2

SMOD = 1

SMOD = 0

Shift

Bit Detector

RxD

Stop BitGen.

Mode 2

Phase 2 Clock(1/2 fOSC)

R1

÷ 16

Shift

1FFH

Transmit

Send

S1P1

Shift

TXClock

Write to SBUF


TI

RXClock

÷ 16 Reset



Shift

RI

Receive

Data

(SMOD isPCON.7)

TB8

RB8

Stop Bit Gen.

SU00541




March 1995 15

80C51 Internal Bus

SBUF

Zero Detector

D QS

CL

Write to

SBUF

TX Control

TX Clock Send

DataStart

RX ControlStart

RX Clock

T1

SerialPort

Interrupt


LoadSBUF

Shift

SBUF

ReadSBUF

80C51 Internal Bus

TxD

TB8

÷ 16


Sample

÷ 2

Timer 1Overflow

SMOD = 1SMOD = 0

Shift

Bit Detector

RxD

R1

÷ 16

LoadSBUF

Shift

1FFH

Transmit

Send

S1P1

Shift

TXClock

Write to SBUF


TI

RXClock

÷ 16 Reset



Shift

RI

Receive

Data

TB8

RB8

Stop Bit Gen.

SU00542




March 1995 16

IE0

IE1

INT0 IT0

TF0

INT1 IT1

TF1

RI

TI

InterruptSources

0

1

0

1

SU00543

Figure 17. 80C51 Interrupt Sources

InterruptsThe 80C51 provides 5 interrupt sources.These are shown in Figure 17. The ExternalInterrupts INT0 and INT1 can each be eitherlevel-activated or transition-activated,depending on bits IT0 and IT1 in RegisterTCON. The flags that actually generate theseinterrupts are bits IE0 and IE1 in TCON.When an external interrupt is generated, theflag that generated it is cleared by thehardware when the service routine isvectored to only if the interrupt wastransition-activated. If the interrupt waslevel-activated, then the external requestingsource is what controls the request flag,rather than the on-chip hardware.

The Timer 0 and Timer 1 Interrupts aregenerated by TF0 and TF1, which are set bya rollover in their respective Timer/Counterregisters (except see Timer 0 in Mode 3).When a timer interrupt is generated, the flagthat generated it is cleared by the on-chiphardware when the service routine isvectored to.

The Serial Port Interrupt is generated by thelogical OR of RI and TI. Neither of these flagsis cleared by hardware when the serviceroutine is vectored to. In fact, the serviceroutine will normally have to determinewhether it was RI or TI that generated theinterrupt, and the bit will have to be cleared insoftware.

All of the bits that generate interrupts can beset or cleared by software, with the sameresult as though it had been set or cleared byhardware. That is, interrupts can begenerated or pending interrupts can becanceled in software.

Each of these interrupt sources can beindividually enabled or disabled by setting orclearing a bit in Special Function Register IE(Figure 18). IE also contains a global disablebit, EA, which disables all interrupts at once.

Priority Level StructureEach interrupt source can also be individuallyprogrammed to one of two priority levels bysetting or clearing a bit in Special FunctionRegister IP (Figure 19). A low-priorityinterrupt can itself be interrupted by ahigh-priority interrupt, but not by anotherlow-priority interrupt. A high-priority interruptcan’t be interrupted by any other interruptsource.

If two request of different priority levels arereceived simultaneously, the request ofhigher priority level is serviced. If requests ofthe same priority level are receivedsimultaneously, an internal polling sequencedetermines which request is serviced. Thuswithin each priority level there is a secondpriority structure determined by the pollingsequence as follows:

Source Priority W ithin Level1. IE0 (highest)2. TF03. IE14. TF15. RI+TI (lowest)

Note that the “priority within level” structure isonly used to resolve simultaneous requestsof the same priority level.

The IP register contains a number ofunimplemented bits. IP.7, IP.6, and IP.5 arereserved in the 80C51. User software shouldnot write 1s to these positions, since theymay be used in other 8051 Family products.

How Interrupts Are HandledThe interrupt flags are sampled at S5P2 ofevery machine cycle. The samples are polledduring the following machine cycle. If one ofthe flags was in a set condition at S5P2 of thepreceding cycle, the polling cycle will find itand the interrupt system will generate anLCALL to the appropriate service routine,provided this hardware-generated LCALL isnot blocked by any of the followingconditions:1. An interrupt of equal or higher priority

level is already in progress.

2. The current (polling) cycle is not the finalcycle in the execution of the instruction inprogress.

3. The instruction in progress is RETI or anywrite to the IE or IP registers.

Any of these three conditions will block thegeneration of the LCALL to the interruptservice routine. Condition 2 ensures that theinstruction in progress will be completedbefore vectoring to any service routine.Condition 3 ensures that if the instruction inprogress is RETI or any access to IE or IP,then at least one more instruction will beexecuted before any interrupt is vectored to.

The polling cycle is repeated with eachmachine cycle, and the values polled are thevalues that were present at S5P2 of theprevious machine cycle. Note that if aninterrupt flag is active but not beingresponded to for one of the above conditions,if the flag is not still active when the blockingcondition is removed, the denied interrupt willnot be serviced. In other words, the fact thatthe interrupt flag was once active but notserviced is not remembered. Every pollingcycle is new.



March 1995 17

EX0

LSBMSB

BIT SYMBOL FUNCTIONIE.7 EA Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt

source is individually enabled or disabled by setting or clearing its enable bit.IE.6 — Reserved.IE.5 — Reserved.IE.4 ES Enables or disables the Serial Port interrupt. If ES=0, the Serial Port interrupt is disabled.IE.3 ET1 Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled.IE.2 EX1 Enables or disables External Interrupt 1. If EX1=0, External interrupt 1 is disabled.IE.1 ET0 Enables or disables the Timer 0 Overflow interrupt. If ET0=0, the Timer 0 interrupt is disabled.IE.0 EX0 Enables or disables External interrupt 0. If EX0=0, External interrupt 0 is disabled.

SU00544

ET0EX1ET1ESXXEA

Figure 18. Interrupt Enable Register (IE)

PX0

LSBMSB

BIT SYMBOL FUNCTIONIP.7 — Reserved.IP.6 — Reserved.IP.5 — Reserved.IP.4 PS Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level.IP.3 PT1 Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level.IP.2 PX1 Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level.IP.1 PT0 Enables or disables the Timer 0 interrupt priority level. PT0=1 programs it to the higher priority level.IP.0 PX0 Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level.

SU00545

PT0PX1PT1PSXXX

Figure 19. Interrupt Priority Register (IP)

. . . .

C1 C2 C3 C4 C5 . . . .

. . . .

InterruptsAre Polled

Long Call toInterrupt

Vector Address

Interrupt Routineε

InterruptGoesActive

. . . . . . . . .

InterruptLatched

This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.

S5P2 S6. . . . . . . . .

SU00546

Figure 20. Interrupt Response T iming Diagram

The polling cycle/LCALL sequence isillustrated in Figure 20.

Note that if an interrupt of higher priority levelgoes active prior to S5P2 of the machinecycle labeled C3 in Figure 20, then inaccordance with the above rules it will bevectored to during C5 and C6, without any

instruction of the lower priority routine havingbeen executed.

Thus the processor acknowledges aninterrupt request by executing ahardware-generated LCALL to theappropriate servicing routine. In some casesit also clears the flag that generated the

interrupt, and in other cases it doesn’t. Itnever clears the Serial Port flag. This has tobe done in the user’s software. It clears anexternal interrupt flag (IE0 or IE1) only if itwas transition-activated. Thehardware-generated LCALL pushes thecontents of the Program Counter on to the



March 1995 18

stack (but it does not save the PSW) andreloads the PC with an address that dependson the source of the interrupt being vectoredto, as shown below:

Source V ector AddressIE0 0003HTF0 000BHIE1 0013HTF1 001BHRI+TI 0023H

Execution proceeds from that location untilthe RETI instruction is encountered. TheRETI instruction informs the processor thatthis interrupt routine is no longer in progress,then pops the top two bytes from the stackand reloads the Program Counter. Executionof the interrupted program continues fromwhere it left off.

Note that a simple RET instruction would alsohave returned execution to the interruptedprogram, but it would have left the interruptcontrol system thinking an interrupt was stillin progress, making future interruptsimpossible.

External InterruptsThe external sources can be programmed tobe level-activated or transition-activated bysetting or clearing bit IT1 or IT0 in RegisterTCON. If ITx = 0, external interrupt x istriggered by a detected low at the INTx pin. IfITx = 1, external interrupt x is edge triggered.In this mode if successive samples of theINTx pin show a high in one cycle and a lowin the next cycle, interrupt request flag IEx inTCON is set. Flag bit IEx then requests theinterrupt.

Since the external interrupt pins are sampledonce each machine cycle, an input high orlow should hold for at least 12 oscillatorperiods to ensure sampling. If the externalinterrupt is transition-activated, the externalsource has to hold the request pin high for atleast one cycle, and then hold it low for atleast one cycle. This is done to ensure thatthe transition is seen so that interrupt requestflag IEx will be set. IEx will be automaticallycleared by the CPU when the service routineis called.

If the external interrupt is level-activated, theexternal source has to hold the request activeuntil the requested interrupt is actuallygenerated. Then it has to deactivate therequest before the interrupt service routine iscompleted, or else another interrupt will begenerated.

Response T imeThe INT0 and INT1 levels are inverted andlatched into IE0 and IE1 at S5P2 of every

machine cycle. The values are not actuallypolled by the circuitry until the next machinecycle. If a request is active and conditions areright for it to be acknowledged, a hardwaresubroutine call to the requested serviceroutine will be the next instruction to beexecuted. The call itself takes two cycles.Thus, a minimum of three complete machinecycles elapse between activation of anexternal interrupt request and the beginningof execution of the first instruction of theservice routine. Figure 20 shows interruptresponse timings.

A longer response time would result if therequest is blocked by one of the 3 previouslylisted conditions. If an interrupt of equal orhigher priority level is already in progress, theadditional wait time obviously depends on thenature of the other interrupt’s service routine.If the instruction in progress is not in its finalcycle, the additional wait time cannot be morethe 3 cycles, since the longest instructions(MUL and DIV) are only 4 cycles long, and ifthe instruction in progress is RETI or anaccess to IE or IP, the additional wait timecannot be more than 5 cycles (a maximum ofone more cycle to complete the instruction inprogress, plus 4 cycles to complete the nextinstruction if the instruction is MUL or DIV).

Thus, in a single-interrupt system, theresponse time is always more than 3 cyclesand less than 9 cycles.

Single-Step OperationThe 80C51 interrupt structure allowssingle-step execution with very little softwareoverhead. As previously noted, an interruptrequest will not be responded to while aninterrupt of equal priority level is still inprogress, nor will it be responded to afterRETI until at least one other instruction hasbeen executed. Thus, once an interruptroutine has been entered, it cannot bere-entered until at least one instruction of theinterrupted program is executed. One way touse this feature for single-step operation is toprogram one of the external interrupts (e.g.,INT0) to be level-activated. The serviceroutine for the interrupt will terminate with thefollowing code:

JNB P3.2,$ ;Wait Till INT0 Goes HighJB P3.2,$ ;Wait Till INT0 Goes LowRETI ;Go Back and Execute One

Instruction

Now if the INT0 pin, which is also the P3.2pin, is held normally low, the CPU will go rightinto the External Interrupt 0 routine and stay

there until INT0 is pulsed (from low to high tolow). Then it will execute RETI, go back tothe task program, execute one instruction,and immediately re-enter the ExternalInterrupt 0 routine to await the next pulsing ofP3.2. One step of the task program isexecuted each time P3.2 is pulsed.

ResetThe reset input is the RST pin, which is theinput to a Schmitt Trigger. A reset isaccomplished by holding the RST pin high forat least two machine cycles (24 oscillatorperiods), while the oscillator is running. TheCPU responds by generating an internalreset, with the timing shown in Figure 21.

The external reset signal is asynchronous tothe internal clock. The RST pin is sampledduring State 5 Phase 2 of every machinecycle. The port pins will maintain their currentactivities for 19 oscillator periods after a logic1 has been sampled at the RST pin; that is,for 19 to 31 oscillator periods after theexternal reset signal has been applied to theRST pin.

The internal reset algorithm writes 0s to allthe SFRs except the port latches, the StackPointer, and SBUF. The port latches areinitialized to FFH, the Stack Pointer to 07H,and SBUF is indeterminate. Table 1 lists theSFR reset values. The internal RAM is notaffected by reset. On power up the RAMcontent is indeterminate.

Table 1. 80C51 SFR Reset Values

REGISTER RESET VALUE

PC 000HACC 00HB 00HPSW 00HSP 07HDPTR 0000HP0–P3 FFHIP XXX00000BIE 0XX00000BTMOD 00HTCON 00HTH0 00HTL0 00HTH1 00HTL1 00HSCON 00HSBUF IndeterminatePCON (NMOS) 0XXXXXXXBPCON (CMOS) 0XXX0000B



March 1995 19

S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4

12 Osc. Periods

Sample RST Sample RST

Internal Reset Signal

ALE:

RST:

PSEN:

Inst. Addr. Inst. Addr. Inst. Addr. Inst. Addr. Inst. Addr.

11 Osc. Periods 19 Osc. Periods

P0:

SU00547

Figure 21. Reset Timing

Power-on ResetAn automatic reset can be obtained whenVCC is turned on by connecting the RST pinto VCC through a 10µf capacitor and to VSSthrough an 8.2k resistor, providing the VCCrise time does not exceed 1 millisecond andthe oscillator start-up time does not exceed10 milliseconds. This power-on reset circuit isshown in Figure 22. The CMOS devices donot require the 8.2k pulldown resistor,although its presence does no harm.

When power is turned on, the circuit holdsthe RST pin high for an amount of time thatdepends on the value of the capacitor andthe rate at which it charges. To ensure a goodreset, the RST pin must be high long enoughto allow the oscillator time to start-up(normally a few ms) plus two machine cycles.

Note that the port pins will be in a randomstate until the oscillator has started and theinternal reset algorithm has written 1s tothem.

With this circuit, reducing VCC quickly to 0causes the RST pin voltage to momentarilyfall below 0V. However, this voltage isinternally limited, and will not harm thedevice.

Power-Saving Modes ofOperationFor applications where power consumption iscritical the CMOS version provides powerreduced modes of operation as a standardfeature. The power down mode in NMOSdevices is no longer a standard feature.

CMOS Power Reduction ModeCMOS versions have two power reducingmodes, Idle and Power Down. The inputthrough which backup power is suppliedduring these operations is VCC. Figure 23shows the internal circuitry which implementsthese features. In the Idle modes (IDL = 1),the oscillator continues to run and theInterrupt, Serial Port, and Timer blockscontinue to be clocked, but the clock signal isgated off to the CPU. In Power Down (PD =1), the oscillator is frozen. The Idle andPower Down Modes are activated by settingbits in Special Function Register PCON. Theaddress of this register is 87H. Figure 24details its contents.

In the NMOS devices the PCON register onlycontains SMOD. The other four bits areimplemented only in the CMOS devices. Usersoftware should never write 1s tounimplemented bits, since they may be usedin other 80C51 Family products.

Idle ModeAn instruction that sets PCON.0 causes thatto be the last instruction executed beforegoing into the Idle mode, the internal clocksignal is gated off to the CPU but not to theInterrupt, Timer, and Serial Port functions.The CPU status is preserved in its entirety;the Stack Pointer, Program Counter, ProgramStatus Word, Accumulator, and all otherregisters maintain their data during Idle. Theport pins hold the logical states they had atthe time Idle was activated. ALE and PSENhold at logic high levels.

There are two ways to terminate the Idle.Activation of any enabled interrupt will cause

PCON.0 to be cleared by hardware,terminating the Idle mode. The interrupt willbe serviced, and following RETI, the nextinstruction to be executed will be the onefollowing the instruction that put the deviceinto Idle.

The flag bits GF0 and GF1 can be used togive an indication if an interrupt occurredduring normal operation or during an Idle. Forexample, an instruction that activates Idlecan also set one or both flag bits. When Idleis terminated by an interrupt, the interruptservice routine can examine the flag bits. Theother way of terminating the Idle mode is witha hardware reset. Since the clock oscillator isstill running, the hardware reset needs to beheld active for only two machine cycles (24oscillator periods) to complete the reset.

The signal at the RST pin clears the IDL bitdirectly and asynchronously. At this time theCPU resumes program execution from whereit left off; that is, at the instruction followingthe one that invoked the Idle Mode. As shownin Figure 21, two or three machine cycles ofprogram execution may take place before theinternal reset algorithm takes control. On-chiphardware inhibits access to the internal RAMduring this time, but access to the port pins isnot inhibited, so, the insertion of 3 NOPinstructions is recommended following theinstruction that invokes idle mode. Toeliminate the possibility of unexpectedoutputs at the port pins, the instructionfollowing the one that invokes Idle should notbe one that writes to a port pin or to externalData RAM.



March 1995 20

10µf

VCC

VCC

80C51

RST

VSS

8.2kΩ

SU00548

Figure 22. Power-On Reset Circuit

Osc.

ClockGen.

Interrupt,Serial Port,Timer Blocks

PDCPU

IDL

XTAL2 XTAL1

SU00549

Figure 23. Idle and Power Down Hardware

IDL

LSBMSB

BIT SYMBOL FUNCTIONPCON.7 SMOD Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the

Serial Port is used in modes 1, 2, or 3.PCON.6 — Reserved.PCON.5 — Reserved.PCON.4 — Reserved.PCON.3 GF1 General-purpose flag bit.PCON.2 GF0 General-purpose flag bit.PCON.1 PD Power-Down bit. Setting this bit activates power-down operation.PCON.0 IDL Idle mode bit. Setting this bit activate idle mode operation.

If 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XXX0000).In the NMOS devices, the PCON register only contains SMOD. The other four bits are implemented only in the CMOSdevices. User software should never write 1s to unimplemented bits, since they may be used in future products.

SU00550

PDGF0GF1———SMOD

Figure 24. Power Control (PCON) Register



March 1995 21

Power-Down ModeAn instruction that sets PCON.1 causes thatto be the last instruction executed beforegoing into the Power Down mode. In thePower Down mode, the on-chip oscillator isstopped. With the clock frozen, all functionsare stopped, the contents of the on-chip RAMand Special Function Registers aremaintained. The port pins output the valuesheld by their respective SFRs. The ALE andPSEN output are held low.

The only exit from Power Down is a hardwarereset. Reset redefines all the SFRs, but doesnot change the on-chip RAM.

In the Power Down mode of operation, VCCcan be reduced to as low as 2V. Care mustbe taken, however, to ensure that VCC is notreduced before the Power Down mode isinvoked, and that VCC is restored to itsnormal operating level, before the PowerDown mode is terminated. The reset thatterminates Power Down also frees theoscillator. The reset should not be activatedbefore VCC is restored to its normal operatinglevel, and must be held active long enough toallow the oscillator to restart and stabilize(normally less than 10ms).

ONCE ModeThe ONCE (“on-circuit emulation”) modefacilitates testing and debugging of systemsusing the device without the device having tobe removed from the circuit. The ONCEmode is invoked by:1. Pull ALE low while the device in in reset

and PSEN is high;

2. Hold ALE low as RST is deactivated.

While the device is in the ONCE mode, thePort 0 pins go into a float state, and the other

port pins and ALE and PSEN are weaklypulled high. The oscillator circuit remainsactive. While the device is in this mode, anemulator or test CPU can be used to drivethe circuit. Normal operation is restored aftera normal reset is applied.

The On-Chip Oscillators

NMOS VersionThe on-chip oscillator circuitry for the NMOSmembers of the 80C51 family is a singlestage linear inverter (Figure 25), intended foruse as a crystal-controlled, positivereactance oscillator (Figure 26). In thisapplication the crystal is operated in itsfundamental response mode as an inductivereactance in parallel resonance withcapacitance external to the crystal.

The crystal specifications and capacitancevalues (C1 and C2 in Figure 26) are notcritical. 30pF can be used in these positionsat any frequency with good quality crystals. Aceramic resonator can be used in place ofthe crystal in cost-sensitive applications.When a ceramic resonator is used, C1 andC2 are normally selected to be of somewhathigher values, typically, 47pF. Themanufacturer of the ceramic resonator shouldbe consulted for recommendation on thevalues of these capacitors.

To drive the NMOS parts with an externalclock source, apply the external clock signalto XTAL2, and ground XTAL1, as shown inFigure 27. A pullup resistor may be used (toincrease noise margin), but is optional if VOHof the driving gate exceeds the VIH minimumspecification of XTAL.

CMOS VersionsThe on-chip oscillator circuitry for the 80C51,shown in Figure 28, consists of a single stage

linear inverter intended for use as acrystal-controlled, positive reactanceoscillator in the same manner as the NMOSparts. However, there are some importantdifferences.

One difference is that the 80C51 is able toturn off its oscillator under software control(by writing a 1 to the PD bit in PCON).Another difference is that, in the 80C51, theinternal clocking circuitry is driven by thesignal at XTAL1, whereas in the NMOSversions it is by the signal at XTAL2.

The feedback resistor Rf in Figure 28consists of paralleled n- and p-channel FETscontrolled by the PD bit, such that Rf isopened when PD = 1. The diodes D1 and D2,which act as clamps to VCC and VSS, areparasitic to the Rf FETs. The oscillator can beused with the same external components asthe NMOS versions, as shown in Figure 29.Typically, C1 = C2 = 30pF when the feedbackelement is a quartz crystal, and C1 = C2 =47pF when a ceramic resonator is used.

When a crystal is used at frequencies above25MHz, C1 and C2 should be in the range of20pF to 25pF.

To drive the CMOS parts with an externalclock source, apply the external clock signalto XTAL1, and leave XTAL2 float, as shownin Figure 30.

The reason for this change from the way theNMOS part is driven can be seen bycomparing Figures 26 and 28. In the NMOSdevices the internal timing circuits are drivenby the signal at XTAL2. In the CMOS devicesthe internal timing circuits are driven by thesignal at XTAL1.

XTAL2

XTAL1

VSS

VCC

TO INTERNALTIMING CIR-CUITS

SUBST.

Q3

Q4

Q2

Q1

SU00551

Figure 25. On-Chip Oscillator in the NMOS V ersion of the 8051 Family



March 1995 22

XTAL2

VSS

TO INTERNALTIMING CIRCUITS

XTAL18051

C1 C2

Q1

Q2

Q3, Q4

QUARTZ CRYSTAL ORCERAMIC RESONATOR

SU00552

Figure 26. Using the NMOS On-Chip Oscillator

EXTERNALOSCILLATORSIGNAL

VSS

VCC

TTL GATE WITH TOTEM-POLE OUTPUT

8051

XTAL2

XTAL1

SU00553

Figure 27. Driving the NMOS 8051 Family Parts with an External Clock

•

XTAL2XTAL1 •

VSS

VCC

•

• •

Q2

Q3Q1

400Ω

Q4PD

D1

D2

•Rf


SU00554

Figure 28. On-Chip Oscillator Circuitry in the CMOS V ersion of the 80C51 Family



March 1995 23

XTAL2

VSS


XTAL180C51

C1 C2

Rf

QUARTZ CRYSTAL ORCERAMIC RESONATOR

VCCPD

SU00555

Figure 29. Using the CMOS On-Chip Oscillator

VSS

XTAL1EXTERNALOSCILLATORSIGNAL

XTAL2

80C51

NC

CMOS GATE

SU00556

Figure 30. Driving the CMOS Family Parts with an External Clock Source

Internal TimingFigures 31 through 34 show when thevarious strobe and port signals are clockedinternally. The figures do not show rise andfall times of the signals, nor do they showpropagation delays between the XTAL2signal and events at other pins.

Rise and fall times are dependent on theexternal loading that each pin must drive.They are often taken to be something in theneighborhood of 10ns, measured between0.8V and 2.0V.

Propagation delays are different for differentpins. For a given pin they vary with pinloading, temperature, VCC, andmanufacturing lot. If the XTAL2 waveform istaken as the timing reference, prop delaysmay vary up to ±200%.

The AC Timings section of the data sheets donot reference any timing to the XTAL2waveform. Rather, they relate the criticaledges of control and input signals to eachother. The timings published in the datasheets include the effects of propagationdelays under the specified test conditions.

80C51 Pin DescriptionsALE/PROG: Address Latch Enable outputpulse for latching the low byte of the addressduring accesses to external memory. ALE isemitted at a constant rate of 1/6 of theoscillator frequency, for external timing orclocking purposes, even when there are noaccesses to external memory. (However, oneALE pulse is skipped during each access toexternal Data Memory.) This pin is also theprogram pulse input (PROG) during EPROMprogramming.

PSEN: Program Store Enable is the readstrobe to external Program Memory. Whenthe device is executing out of externalProgram Memory, PSEN is activated twiceeach machine cycle (except that two PSENactivations are skipped during accesses toexternal Data Memory). PSEN is notactivated when the device is executing out ofinternal Program Memory.

EA/VPP: When EA is held high the CPUexecutes out of internal Program Memory(unless the Program Counter exceeds0FFFH in the 80C51). Holding EA low forcesthe CPU to execute out of external memoryregardless of the Program Counter value. Inthe 80C31, EA must be externally wired low.

In the EPROM devices, this pin also receivesthe programming supply voltage (VPP) duringEPROM programming.

XTAL1: Input to the inverting oscillatoramplifier.

XTAL2: Output from the inverting oscillatoramplifier.

Port 0: Port 0 is an 8-bit open drainbidirectional port. As an open drain outputport, it can sink eight LS TTL loads. Port 0pins that have 1s written to them float, and inthat state will function as high impedanceinputs. Port 0 is also the multiplexedlow-order address and data bus duringaccesses to external memory. In thisapplication it uses strong internal pullupswhen emitting 1s. Port 0 emits code bytesduring program verification. In thisapplication, external pullups are required.

Port 1: Port 1 is an 8-bit bidirectional I/O portwith internal pullups. Port 1 pins that have 1swritten to them are pulled high by the internalpullups, and in that state can be used asinputs. As inputs, port 1 pins that areexternally being pulled low will source currentbecause of the internal pullups.



March 1995 24

Port 2: Port 2 is an 8-bit bidirectional I/O portwith internal pullups. Port 2 emits thehigh-order address byte during accesses toexternal memory that use 16-bit addresses.In this application, it uses the strong internalpullups when emitting 1s.

Port 3: Port 3 is an 8-bit bidirectional I/O portwith internal pullups. It also serves thefunctions of various special features of the80C51 Family as follows:

Port Pin Alternate FunctionP3.0 RxD (serial input port)P3.1 TxD (serial output port)P3.2 INT0 (external interrupt 0)P3.3 INT1 (external interrupt 1)P3.4 T0 (timer 0 external input)P3.5 T1 (timer 1 external input)P3.6 WR (external data memory

write strobe)P3.7 RD (external data memory

read strobe)

VCC: Supply voltage

VSS: Circuit ground potential

XTAL2:

P1 P2State 1 State 2 State 3 State 4 State 5 State 6 State 1 State 2

P1 P2 P1 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

ALE:

PSEN:

PCLOut

PCLOut

PCLOutP0:

Data Sampled Data Sampled Data Sampled

PCH Out PCH Out PCH OutP2:

P2

SU00557

Figure 31. External Program Memory Fetches

XTAL2:

P1 P2State 4 State 5 State 6 State 1 State 2 State 3 State 4 State 5

P1 P2 P1 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

ALE:

RD:

P0:

Float

DPH or P2 SFR Out PCH or P2SFR

P2:

P2

DPL or RIOut

Data Sampled

Float

PCL Out if ProgramMemory Is External

PCH or P2SFR

SU00558

Figure 32. External Data Memory Read Cycle



March 1995 25

XTAL2:

P1 P2

State 4 State 5 State 6 State 1 State 2 State 3 State 4 State 5

P1 P2 P1 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

ALE:

WR:

P0:

DPH or P2 SFR Out PCH or P2SFR

P2:

P2

DPL or RIOut

PCL Out if ProgramMemory Is External

PCH or P2SFR

Data Out PCLOut

SU00559

Figure 33. External Data Memory W rite Cycle

XTAL2:

P1 P2

State 4 State 5 State 6 State 1 State 2 State 3 State 4 State 5

P1 P2 P1 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

Old DataMOV Port, SRC:

P2

P0, P1

P2, P3, RST

P0, P1

P2, P3, RST

RXD Pin Sampled RXD Sampled

New Data

Inputs Sampled:

Serial PortShift Clock(Mode 0):

SU00560

Figure 34. Port Operation

80C51 Family 80C51 family hardware descriptionoregonstate.edu/instruct/ece473/8051_hw.pdf · 2002....

Documents

Transcript of 80C51 Family 80C51 family hardware descriptionoregonstate.edu/instruct/ece473/8051_hw.pdf · 2002....