8096 microcontrol

11
LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA UNIT- 7 (Notes) 7.1 FEATURE OF 8096/80196 MICROCONTROLLER 16 BIT microcontroller. It performs 16 bit processing Princeton Architecture Continuous address space for SFRs, Registers, Internal RAM & ROM and external memory Register based arithmetic and logic operations 16 BIT stack pointer BIU & MUX unit 4 byte instruction queue 5 ports P0,P1,P2,P3 & P4 Timers, serial ports, ADC & PWM Interrupt control circuit and watch dog timer 16 KB ROM/EPROM starting from address 2000H Timers are 16 bit with the facility of input capture and out compare The ports are multiplexed Faculty : S V Altaf Page 1

Transcript of 8096 microcontrol

Page 1: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

UNIT- 7 (Notes)

7.1 FEATURE OF 8096/80196 MICROCONTROLLER

• 16 BIT microcontroller. It performs 16 bit processing• Princeton Architecture• Continuous address space for SFRs, Registers, Internal RAM & ROM and external memory• Register based arithmetic and logic operations• 16 BIT stack pointer• BIU & MUX unit• 4 byte instruction queue• 5 ports P0,P1,P2,P3 & P4• Timers, serial ports, ADC & PWM• Interrupt control circuit and watch dog timer• 16 KB ROM/EPROM starting from address 2000H• Timers are 16 bit with the facility of input capture and out compare• The ports are multiplexed

Faculty : S V Altaf Page 1

Page 2: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

• P0 is multiplexed with analog inputs

P1 is multiplexed with PWM & PTS signalsP2 is multiplexed with serial port and timer signals

• P3 & P4 have alternate functions in expanded mode of operation• P3 has AD00-AD07• P4 has AD00-AD15• 1ST 24 bytes of memory is for SFRs. There are 4 horizontal windows.

Each window is of 24 bytes each and address of 24 bytes will be the same for all 4 windows. So we can say window 0,window1, window2, window3.

• Page 0 addresses is from 00 to FFH• First 512 bytes between 0000 to 01FFH are divided into vertical windows• These windows are 16 of 32 bytes each, 8 of 64 bytes each or 4 of 128 bytes each

7.2 OPERATIONAL FEATURES

• It does 16 bits operations on 1 instruction cycle• It does not have separate data and code memory

Data memory contains variableCode memory contains code

• Both operands can be registers• PWM can be used as DAC• Facility which will continuously check whether CPU is properly working or not (Watch dog

timer)• PTS Peripheral Transaction Server

7.3 MEMORY MAP OF 80196 KC

Faculty : S V Altaf Page 2

Page 3: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

7.4 SFRs of 80196KC

S Special function Registers are available from address 0000H-0017H i.e. 24 addresses. Out of these 24 addresses,9 addresses are common to horizontal window 0 (read), horizontal window 0 (write), horizontal window 1(Read ) and horizontal window 15.

• Registers common to all windows are given below. ADD (Hex) SFR 0000-0001H R00008H Int_mask0009H INT_pending0012H INT_pend10013H INT_mask10014H WSR

• Registers of Horizontal window 0 (read) and window 0 (write)

ADD (Hex) SFR 0002 AD_command(write)0002 AD_Result_L0 (read)

Faculty : S V Altaf Page 3

Page 4: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

0003 HSI_mode (write)0003 AD_result_high(read)0004-0005 HS0_Time (Write)0004-0005 HS0_Time (read)0006 HS0_Command (write)0006 HS0_status (read)0007 SBUF000A Watchdog (Write)000B I0C2(Write)000A-000B Timer 1 (Read)000C-000D Timer 2 (read)000E Baud rate (write)000E P0 (read)000F P1 (read/write)0010 P2 (read/write)0011 SP_Control (write)0011 SP_stat (read)0015 10C0(write)0015 10S0(read)0016 10C1 (write)0016 10S1 (read)0017 10S2 (Read/write)

• Horizontal window 1 (read/write)

ADD (Hex) SFR 0003 AD_Time0004 PTSSEL_L00005 PTSSEL_H00006 PTSSRV_L00007 PTSSRV_H0000C 10C30016 PWM2 control0017 PWM1 control

Unused addresses are reserved for future expansion. Common addresses are same as earlier

Faculty : S V Altaf Page 4

Page 5: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

SFRs at horizontal window 15

ADD (Hex) SFR 000C T2 Capture_L00016 T2 Capture_L0

7.5 PORTS OF 80196

It has got 5 ports P0,P1,P2,P3,P4. P0, P1and P2 are SFRs and P3 & P4 are outside SFR area. All the ports have got different functions in single chip mode or extended mode of operation.

• PORT P0 – This is a general purpose port which is read only in single chip mode. In expanded mode of operation ,it is used to accept analog inputs at P0.0 to P0.7, P0.7 is also used as external interrupt under the control of register.

• PORT P1 – This port is a general purpose quasi bidirectional port in single chip mode operation. In extended mode P1.5-P1.7 are used by PTS controlling the DMA operation. P1.3 & P1.4 are used for PWM1 and PWM2 in extended mode operation.

• PORT P2 – P2 is a general purpose bidirectional port. In extended mode operation P2.5

is used for PWM0. P2.3 & P2.4 are used as inputs, T2 clock & T2 reset of timer 2. P2.2 is used for external interrupts. P2.0 & P2.1 are used as data and clock for synchronous serial communication. For asynchronous communication they are used as T*D and R*D.

• PORT P3 – It is outside SFR. Its address is 1FFEH. It is a quasi bi directional port. During

extended operation it carries AD00-AD07 bits.

• PORT P4 – This is also outside SFR its address is 1FFFH. It is similar to P3 in single chip mode but in expanded mode of operation it carries signals AD8-AD15.

7.6 WINDOW SELECTION REGISTER (WSR)

• WSR is one of the important SFR which is used to select horizontal windows and vertical windows.

Faculty : S V Altaf Page 5

Page 6: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

Faculty : S V Altaf Page 6

Page 7: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

• The 4 LSBs of WSR are used to select the horizontal window. The four bit value will indicate

window number. • 3 bits of WSR i.e. BIT4,5 & 6 will decide the vertical window configuration. If BIT4 is set it will

select 4 vertical windows, if bit5 is set it will select 8 vertical windows and if bit6 is set it will select 16 vertical windows.

• Once a vertical window is selected the memory location within a window will be selected by the instruction directly

7.7 TIMERS, HSIs & HSOs

• T1 is a 16 bit free running timer• Input to the timer comes from internal clock

Faculty : S V Altaf Page 7

Page 8: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

• It always runs and cannot be reset• It is used to generate accurate time delays and to arrive at time of the day• It is used mainly for HSIs

o 4HSIso FIFO is used to store time of captureo 8 entries of FIFOo Each entry is 20 bitso 16 bits are for time and 4 bits are for the type of HIS

• It is rarely used for HSO operation • The input capture is a high speed signal • Its input signal is connected to micro controller• It can capture very fast events also • 4 different events can be captured simultaneously• T2 is a 16 bit internal or external counter

o Used mainly for HSOso 6 HSOso Compares entries in CAM o Each entry is 23 bitso 16 bits for comparison datao 7 bits for command

• T2 has nothing to do with real time operation • The CAM memory means content addressable memory. • Memory location is not addressed by CPU address• Width of the memory location is user defined• Memory location is read when a part of memory location data is equal to input data• Status and control registers are used to control and read information of timer 1 and timer 2• There are 4 software timers

o The overflows of software timers are indicated by ISO1.0 – ISO1.3o Hardware counters are not used and instead memory locations are used

7.8 INTERRUPTS

• 18 groups of interrupts• 3 NMI groups• 15 general interrupt groups• Priority scheme is implemented

Faculty : S V Altaf Page 8

Page 9: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

• Masking facility is provided. 2 levels of masking is available. The higher level is by bit 9 of

PSW and secondary level is by individual bits of INT mask and INT mask1 registers.• Each interrupt has a specific vector. The vector area is from 2000H – 2014H & 2030H-203FH• Priority of interrupt is fixed as INT0 being higher priority and INT17 being lowest priority• Each interrupt is indicated by a flag. For example – FIFO full flag• Details of each interrupt group

o Group 0 External HWo Group 1 HSIo Group 2 External HWo Group 3 Timer 2 overflowo Group 4 Timer 2, T2 captureo Group 5 HSI,FIFO HALF FULL o Group 6 Serial Port, RI flago Group 7 Serial Port, TI flag o Group 8 Illegal codeo Group 9 Instruction trap o Group 10 External HWo Group 11 Serial Port, TI or RIo Group 12 HSOo Group 13 HSIo Group 14 HSO.0-HSO.5o Group 16 ADCo Group 17 T1 or T2 overflow

7.9 ADDRESSING MODES

• Implicit address modeo PUSHFo SETC

• Immediate addressing modeo LD AX,#55AHo ADD AX,NUM,#1234H

• Direct addressing modeo LD AL,P0o ADD BX,NUM1,NUM2

• Indirect addressing modeo Without port increment

Faculty : S V Altaf Page 9

Page 10: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

LD AX,[SI]

o Width post increment LD AX,[SI]+

o Index Long LD AX,[SI+offset]

o Index short LD AX,DISP[SI]

7.10 INSTRUCTIONS OF 80196

• Maximum number of operands can be upto 3• The memory locations are treated as registers• Each memory location used should be given a name• These names to be used in the instructions• Data transfer instructions

o LDo STo PUSHo POP

• Arithmetic Instructionso ADDo ADCo SUBo SUBBo MULTIPLYo MULTIPLY SIGN NUMBERSo DIVIDEo DIVIDE SIGN NUMBERS

• DATA Manipulation instructions

o CLRo EXTo NOT

• BIT Manipulation instructions

o SETCo CLRC

Faculty : S V Altaf Page 10

Page 11: 8096 microcontrol

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY MCA

o EIDI

• Logical instructions

o ANDo ORo XOR

• Program control flow instructions

o CALL SCALL LCALL

o JMP SJMP LJMP

o Conditional jump based on flags

• Miscellaneous instructionso RSTo TRAP

Faculty : S V Altaf Page 11